atsam4ls8a_pac/crccu/
mr.rs1#[doc = "Register `MR` reader"]
2pub struct R(crate::R<MR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MR` writer"]
17pub struct W(crate::W<MR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ENABLE` reader - CRC Computation Enable"]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - CRC Computation Enable"]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
41#[doc = "Field `COMPARE` reader - CRC Compare"]
42pub type COMPARE_R = crate::BitReader<bool>;
43#[doc = "Field `COMPARE` writer - CRC Compare"]
44pub type COMPARE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
45#[doc = "Field `PTYPE` reader - Polynomial Type"]
46pub type PTYPE_R = crate::FieldReader<u8, PTYPESELECT_A>;
47#[doc = "Polynomial Type\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49#[repr(u8)]
50pub enum PTYPESELECT_A {
51 #[doc = "0: `0`"]
52 CCITT8023 = 0,
53 #[doc = "1: `1`"]
54 CASTAGNOLI = 1,
55 #[doc = "2: `10`"]
56 CCITT16 = 2,
57}
58impl From<PTYPESELECT_A> for u8 {
59 #[inline(always)]
60 fn from(variant: PTYPESELECT_A) -> Self {
61 variant as _
62 }
63}
64impl PTYPE_R {
65 #[doc = "Get enumerated values variant"]
66 #[inline(always)]
67 pub fn variant(&self) -> Option<PTYPESELECT_A> {
68 match self.bits {
69 0 => Some(PTYPESELECT_A::CCITT8023),
70 1 => Some(PTYPESELECT_A::CASTAGNOLI),
71 2 => Some(PTYPESELECT_A::CCITT16),
72 _ => None,
73 }
74 }
75 #[doc = "Checks if the value of the field is `CCITT8023`"]
76 #[inline(always)]
77 pub fn is_ccitt8023(&self) -> bool {
78 *self == PTYPESELECT_A::CCITT8023
79 }
80 #[doc = "Checks if the value of the field is `CASTAGNOLI`"]
81 #[inline(always)]
82 pub fn is_castagnoli(&self) -> bool {
83 *self == PTYPESELECT_A::CASTAGNOLI
84 }
85 #[doc = "Checks if the value of the field is `CCITT16`"]
86 #[inline(always)]
87 pub fn is_ccitt16(&self) -> bool {
88 *self == PTYPESELECT_A::CCITT16
89 }
90}
91#[doc = "Field `PTYPE` writer - Polynomial Type"]
92pub type PTYPE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, PTYPESELECT_A, 2, O>;
93impl<'a, const O: u8> PTYPE_W<'a, O> {
94 #[doc = "`0`"]
95 #[inline(always)]
96 pub fn ccitt8023(self) -> &'a mut W {
97 self.variant(PTYPESELECT_A::CCITT8023)
98 }
99 #[doc = "`1`"]
100 #[inline(always)]
101 pub fn castagnoli(self) -> &'a mut W {
102 self.variant(PTYPESELECT_A::CASTAGNOLI)
103 }
104 #[doc = "`10`"]
105 #[inline(always)]
106 pub fn ccitt16(self) -> &'a mut W {
107 self.variant(PTYPESELECT_A::CCITT16)
108 }
109}
110#[doc = "Field `DIVIDER` reader - Bandwidth Divider"]
111pub type DIVIDER_R = crate::FieldReader<u8, u8>;
112#[doc = "Field `DIVIDER` writer - Bandwidth Divider"]
113pub type DIVIDER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, u8, 4, O>;
114impl R {
115 #[doc = "Bit 0 - CRC Computation Enable"]
116 #[inline(always)]
117 pub fn enable(&self) -> ENABLE_R {
118 ENABLE_R::new((self.bits & 1) != 0)
119 }
120 #[doc = "Bit 1 - CRC Compare"]
121 #[inline(always)]
122 pub fn compare(&self) -> COMPARE_R {
123 COMPARE_R::new(((self.bits >> 1) & 1) != 0)
124 }
125 #[doc = "Bits 2:3 - Polynomial Type"]
126 #[inline(always)]
127 pub fn ptype(&self) -> PTYPE_R {
128 PTYPE_R::new(((self.bits >> 2) & 3) as u8)
129 }
130 #[doc = "Bits 4:7 - Bandwidth Divider"]
131 #[inline(always)]
132 pub fn divider(&self) -> DIVIDER_R {
133 DIVIDER_R::new(((self.bits >> 4) & 0x0f) as u8)
134 }
135}
136impl W {
137 #[doc = "Bit 0 - CRC Computation Enable"]
138 #[inline(always)]
139 #[must_use]
140 pub fn enable(&mut self) -> ENABLE_W<0> {
141 ENABLE_W::new(self)
142 }
143 #[doc = "Bit 1 - CRC Compare"]
144 #[inline(always)]
145 #[must_use]
146 pub fn compare(&mut self) -> COMPARE_W<1> {
147 COMPARE_W::new(self)
148 }
149 #[doc = "Bits 2:3 - Polynomial Type"]
150 #[inline(always)]
151 #[must_use]
152 pub fn ptype(&mut self) -> PTYPE_W<2> {
153 PTYPE_W::new(self)
154 }
155 #[doc = "Bits 4:7 - Bandwidth Divider"]
156 #[inline(always)]
157 #[must_use]
158 pub fn divider(&mut self) -> DIVIDER_W<4> {
159 DIVIDER_W::new(self)
160 }
161 #[doc = "Writes raw bits to the register."]
162 #[inline(always)]
163 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
164 self.0.bits(bits);
165 self
166 }
167}
168#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"]
169pub struct MR_SPEC;
170impl crate::RegisterSpec for MR_SPEC {
171 type Ux = u32;
172}
173#[doc = "`read()` method returns [mr::R](R) reader structure"]
174impl crate::Readable for MR_SPEC {
175 type Reader = R;
176}
177#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"]
178impl crate::Writable for MR_SPEC {
179 type Writer = W;
180 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
182}
183#[doc = "`reset()` method sets MR to value 0"]
184impl crate::Resettable for MR_SPEC {
185 const RESET_VALUE: Self::Ux = 0;
186}