Type Definition atsam4ls8a_pac::iisc::mr::W

type W = W<u32, MR>;

Writer for register MR

Implementations

impl W

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - Master/Slave/Controller Mode

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 2:4 - Data Word Length

pub fn rxmono(&mut self) -> RXMONO_W<'_>

Bit 8 - Receiver Mono

pub fn rxdma(&mut self) -> RXDMA_W<'_>

Bit 9 - Single or Multiple DMA Channels for Receiver

pub fn rxloop(&mut self) -> RXLOOP_W<'_>

Bit 10 - Loop-back Test Mode

pub fn txmono(&mut self) -> TXMONO_W<'_>

Bit 12 - Transmitter Mono

pub fn txdma(&mut self) -> TXDMA_W<'_>

Bit 13 - Single or Multiple DMA Channels for Transmitter

pub fn txsame(&mut self) -> TXSAME_W<'_>

Bit 14 - Transmit Data when Underrun

pub fn imckfs(&mut self) -> IMCKFS_W<'_>

Bits 24:29 - Master Clock to fs Ratio

pub fn imckmode(&mut self) -> IMCKMODE_W<'_>

Bit 30 - Master Clock Mode

pub fn iws24(&mut self) -> IWS24_W<'_>

Bit 31 - IWS Data Slot Width