atsam4ls4c_pac/spi/
cr.rs

1#[doc = "Register `CR` writer"]
2pub struct W(crate::W<CR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "SPI Enable\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum SPIENSELECT_AW {
25    #[doc = "0: No effect."]
26    _0 = 0,
27    #[doc = "1: Enables the SPI to transfer and receive data."]
28    _1 = 1,
29}
30impl From<SPIENSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: SPIENSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `SPIEN` writer - SPI Enable"]
37pub type SPIEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, SPIENSELECT_AW, O>;
38impl<'a, const O: u8> SPIEN_W<'a, O> {
39    #[doc = "No effect."]
40    #[inline(always)]
41    pub fn _0(self) -> &'a mut W {
42        self.variant(SPIENSELECT_AW::_0)
43    }
44    #[doc = "Enables the SPI to transfer and receive data."]
45    #[inline(always)]
46    pub fn _1(self) -> &'a mut W {
47        self.variant(SPIENSELECT_AW::_1)
48    }
49}
50#[doc = "SPI Disable\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum SPIDISSELECT_AW {
53    #[doc = "0: No effect."]
54    _0 = 0,
55    #[doc = "1: Disables the SPI.All pins are set in input mode and no data is received or transmitted.If a transfer is in progress, the transfer is finished before the SPI is disabled.If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled."]
56    _1 = 1,
57}
58impl From<SPIDISSELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: SPIDISSELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `SPIDIS` writer - SPI Disable"]
65pub type SPIDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, SPIDISSELECT_AW, O>;
66impl<'a, const O: u8> SPIDIS_W<'a, O> {
67    #[doc = "No effect."]
68    #[inline(always)]
69    pub fn _0(self) -> &'a mut W {
70        self.variant(SPIDISSELECT_AW::_0)
71    }
72    #[doc = "Disables the SPI.All pins are set in input mode and no data is received or transmitted.If a transfer is in progress, the transfer is finished before the SPI is disabled.If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled."]
73    #[inline(always)]
74    pub fn _1(self) -> &'a mut W {
75        self.variant(SPIDISSELECT_AW::_1)
76    }
77}
78#[doc = "SPI Software Reset\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum SWRSTSELECT_AW {
81    #[doc = "0: No effect."]
82    _0 = 0,
83    #[doc = "1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed."]
84    _1 = 1,
85}
86impl From<SWRSTSELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: SWRSTSELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `SWRST` writer - SPI Software Reset"]
93pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, SWRSTSELECT_AW, O>;
94impl<'a, const O: u8> SWRST_W<'a, O> {
95    #[doc = "No effect."]
96    #[inline(always)]
97    pub fn _0(self) -> &'a mut W {
98        self.variant(SWRSTSELECT_AW::_0)
99    }
100    #[doc = "Reset the SPI. A software-triggered hardware reset of the SPI interface is performed."]
101    #[inline(always)]
102    pub fn _1(self) -> &'a mut W {
103        self.variant(SWRSTSELECT_AW::_1)
104    }
105}
106#[doc = "Field `FLUSHFIFO` writer - Flush FIFO command"]
107pub type FLUSHFIFO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
108#[doc = "Last Transfer\n\nValue on reset: 0"]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum LASTXFERSELECT_AW {
111    #[doc = "0: No effect."]
112    _0 = 0,
113    #[doc = "1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed."]
114    _1 = 1,
115}
116impl From<LASTXFERSELECT_AW> for bool {
117    #[inline(always)]
118    fn from(variant: LASTXFERSELECT_AW) -> Self {
119        variant as u8 != 0
120    }
121}
122#[doc = "Field `LASTXFER` writer - Last Transfer"]
123pub type LASTXFER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, LASTXFERSELECT_AW, O>;
124impl<'a, const O: u8> LASTXFER_W<'a, O> {
125    #[doc = "No effect."]
126    #[inline(always)]
127    pub fn _0(self) -> &'a mut W {
128        self.variant(LASTXFERSELECT_AW::_0)
129    }
130    #[doc = "The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, thisallows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TDtransfer has completed."]
131    #[inline(always)]
132    pub fn _1(self) -> &'a mut W {
133        self.variant(LASTXFERSELECT_AW::_1)
134    }
135}
136impl W {
137    #[doc = "Bit 0 - SPI Enable"]
138    #[inline(always)]
139    #[must_use]
140    pub fn spien(&mut self) -> SPIEN_W<0> {
141        SPIEN_W::new(self)
142    }
143    #[doc = "Bit 1 - SPI Disable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn spidis(&mut self) -> SPIDIS_W<1> {
147        SPIDIS_W::new(self)
148    }
149    #[doc = "Bit 7 - SPI Software Reset"]
150    #[inline(always)]
151    #[must_use]
152    pub fn swrst(&mut self) -> SWRST_W<7> {
153        SWRST_W::new(self)
154    }
155    #[doc = "Bit 8 - Flush FIFO command"]
156    #[inline(always)]
157    #[must_use]
158    pub fn flushfifo(&mut self) -> FLUSHFIFO_W<8> {
159        FLUSHFIFO_W::new(self)
160    }
161    #[doc = "Bit 24 - Last Transfer"]
162    #[inline(always)]
163    #[must_use]
164    pub fn lastxfer(&mut self) -> LASTXFER_W<24> {
165        LASTXFER_W::new(self)
166    }
167    #[doc = "Writes raw bits to the register."]
168    #[inline(always)]
169    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
170        self.0.bits(bits);
171        self
172    }
173}
174#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
175pub struct CR_SPEC;
176impl crate::RegisterSpec for CR_SPEC {
177    type Ux = u32;
178}
179#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
180impl crate::Writable for CR_SPEC {
181    type Writer = W;
182    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
184}
185#[doc = "`reset()` method sets CR to value 0"]
186impl crate::Resettable for CR_SPEC {
187    const RESET_VALUE: Self::Ux = 0;
188}
atsam4ls4c_pac/spi/cr.rs

atsam4ls4c_pac/spi/
cr.rs
