atsam4ls4c_pac/scif/
dfll0conf.rs

1#[doc = "Register `DFLL0CONF` reader"]
2pub struct R(crate::R<DFLL0CONF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DFLL0CONF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DFLL0CONF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DFLL0CONF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DFLL0CONF` writer"]
17pub struct W(crate::W<DFLL0CONF_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DFLL0CONF_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DFLL0CONF_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DFLL0CONF_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Enable"]
40pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
41#[doc = "Field `MODE` reader - Mode Selection"]
42pub type MODE_R = crate::BitReader<bool>;
43#[doc = "Field `MODE` writer - Mode Selection"]
44pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
45#[doc = "Field `STABLE` reader - Stable DFLL Frequency"]
46pub type STABLE_R = crate::BitReader<bool>;
47#[doc = "Field `STABLE` writer - Stable DFLL Frequency"]
48pub type STABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
49#[doc = "Field `LLAW` reader - Lose Lock After Wake"]
50pub type LLAW_R = crate::BitReader<bool>;
51#[doc = "Field `LLAW` writer - Lose Lock After Wake"]
52pub type LLAW_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
53#[doc = "Field `CCDIS` reader - Chill Cycle Disable"]
54pub type CCDIS_R = crate::BitReader<bool>;
55#[doc = "Field `CCDIS` writer - Chill Cycle Disable"]
56pub type CCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
57#[doc = "Field `QLDIS` reader - Quick Lock Disable"]
58pub type QLDIS_R = crate::BitReader<bool>;
59#[doc = "Field `QLDIS` writer - Quick Lock Disable"]
60pub type QLDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
61#[doc = "Field `RANGE` reader - Range Value"]
62pub type RANGE_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `RANGE` writer - Range Value"]
64pub type RANGE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLL0CONF_SPEC, u8, u8, 2, O>;
65#[doc = "Field `FCD` reader - Fuse Calibration Done"]
66pub type FCD_R = crate::BitReader<bool>;
67#[doc = "Field `FCD` writer - Fuse Calibration Done"]
68pub type FCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DFLL0CONF_SPEC, bool, O>;
69#[doc = "Field `CALIB` reader - Calibration Value"]
70pub type CALIB_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `CALIB` writer - Calibration Value"]
72pub type CALIB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLL0CONF_SPEC, u8, u8, 4, O>;
73impl R {
74    #[doc = "Bit 0 - Enable"]
75    #[inline(always)]
76    pub fn en(&self) -> EN_R {
77        EN_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - Mode Selection"]
80    #[inline(always)]
81    pub fn mode(&self) -> MODE_R {
82        MODE_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - Stable DFLL Frequency"]
85    #[inline(always)]
86    pub fn stable(&self) -> STABLE_R {
87        STABLE_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - Lose Lock After Wake"]
90    #[inline(always)]
91    pub fn llaw(&self) -> LLAW_R {
92        LLAW_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 5 - Chill Cycle Disable"]
95    #[inline(always)]
96    pub fn ccdis(&self) -> CCDIS_R {
97        CCDIS_R::new(((self.bits >> 5) & 1) != 0)
98    }
99    #[doc = "Bit 6 - Quick Lock Disable"]
100    #[inline(always)]
101    pub fn qldis(&self) -> QLDIS_R {
102        QLDIS_R::new(((self.bits >> 6) & 1) != 0)
103    }
104    #[doc = "Bits 16:17 - Range Value"]
105    #[inline(always)]
106    pub fn range(&self) -> RANGE_R {
107        RANGE_R::new(((self.bits >> 16) & 3) as u8)
108    }
109    #[doc = "Bit 23 - Fuse Calibration Done"]
110    #[inline(always)]
111    pub fn fcd(&self) -> FCD_R {
112        FCD_R::new(((self.bits >> 23) & 1) != 0)
113    }
114    #[doc = "Bits 24:27 - Calibration Value"]
115    #[inline(always)]
116    pub fn calib(&self) -> CALIB_R {
117        CALIB_R::new(((self.bits >> 24) & 0x0f) as u8)
118    }
119}
120impl W {
121    #[doc = "Bit 0 - Enable"]
122    #[inline(always)]
123    #[must_use]
124    pub fn en(&mut self) -> EN_W<0> {
125        EN_W::new(self)
126    }
127    #[doc = "Bit 1 - Mode Selection"]
128    #[inline(always)]
129    #[must_use]
130    pub fn mode(&mut self) -> MODE_W<1> {
131        MODE_W::new(self)
132    }
133    #[doc = "Bit 2 - Stable DFLL Frequency"]
134    #[inline(always)]
135    #[must_use]
136    pub fn stable(&mut self) -> STABLE_W<2> {
137        STABLE_W::new(self)
138    }
139    #[doc = "Bit 3 - Lose Lock After Wake"]
140    #[inline(always)]
141    #[must_use]
142    pub fn llaw(&mut self) -> LLAW_W<3> {
143        LLAW_W::new(self)
144    }
145    #[doc = "Bit 5 - Chill Cycle Disable"]
146    #[inline(always)]
147    #[must_use]
148    pub fn ccdis(&mut self) -> CCDIS_W<5> {
149        CCDIS_W::new(self)
150    }
151    #[doc = "Bit 6 - Quick Lock Disable"]
152    #[inline(always)]
153    #[must_use]
154    pub fn qldis(&mut self) -> QLDIS_W<6> {
155        QLDIS_W::new(self)
156    }
157    #[doc = "Bits 16:17 - Range Value"]
158    #[inline(always)]
159    #[must_use]
160    pub fn range(&mut self) -> RANGE_W<16> {
161        RANGE_W::new(self)
162    }
163    #[doc = "Bit 23 - Fuse Calibration Done"]
164    #[inline(always)]
165    #[must_use]
166    pub fn fcd(&mut self) -> FCD_W<23> {
167        FCD_W::new(self)
168    }
169    #[doc = "Bits 24:27 - Calibration Value"]
170    #[inline(always)]
171    #[must_use]
172    pub fn calib(&mut self) -> CALIB_W<24> {
173        CALIB_W::new(self)
174    }
175    #[doc = "Writes raw bits to the register."]
176    #[inline(always)]
177    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178        self.0.bits(bits);
179        self
180    }
181}
182#[doc = "DFLL0 Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfll0conf](index.html) module"]
183pub struct DFLL0CONF_SPEC;
184impl crate::RegisterSpec for DFLL0CONF_SPEC {
185    type Ux = u32;
186}
187#[doc = "`read()` method returns [dfll0conf::R](R) reader structure"]
188impl crate::Readable for DFLL0CONF_SPEC {
189    type Reader = R;
190}
191#[doc = "`write(|w| ..)` method takes [dfll0conf::W](W) writer structure"]
192impl crate::Writable for DFLL0CONF_SPEC {
193    type Writer = W;
194    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196}
197#[doc = "`reset()` method sets DFLL0CONF to value 0"]
198impl crate::Resettable for DFLL0CONF_SPEC {
199    const RESET_VALUE: Self::Ux = 0;
200}
atsam4ls4c_pac/scif/dfll0conf.rs

atsam4ls4c_pac/scif/
dfll0conf.rs
