atsam4ls4b_pac/usbc/
uesta2.rs

1#[doc = "Register `UESTA2` reader"]
2pub struct R(crate::R<UESTA2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UESTA2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UESTA2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UESTA2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `TXINI` reader - Transmitted IN Data Interrupt"]
17pub type TXINI_R = crate::BitReader<bool>;
18#[doc = "Field `RXOUTI` reader - Received OUT Data Interrupt"]
19pub type RXOUTI_R = crate::BitReader<bool>;
20#[doc = "Field `RXSTPI` reader - Received SETUP Interrupt"]
21pub type RXSTPI_R = crate::BitReader<bool>;
22#[doc = "Field `NAKOUTI` reader - NAKed OUT Interrupt"]
23pub type NAKOUTI_R = crate::BitReader<bool>;
24#[doc = "Field `NAKINI` reader - NAKed IN Interrupt"]
25pub type NAKINI_R = crate::BitReader<bool>;
26#[doc = "Field `STALLEDI` reader - STALLed Interrupt"]
27pub type STALLEDI_R = crate::BitReader<bool>;
28#[doc = "Field `DTSEQ` reader - Data Toggle Sequence"]
29pub type DTSEQ_R = crate::FieldReader<u8, u8>;
30#[doc = "Field `RAMACERI` reader - Ram Access Error Interrupt"]
31pub type RAMACERI_R = crate::BitReader<bool>;
32#[doc = "Field `NBUSYBK` reader - Number Of Busy Banks"]
33pub type NBUSYBK_R = crate::FieldReader<u8, u8>;
34#[doc = "Field `CURRBK` reader - Current Bank"]
35pub type CURRBK_R = crate::FieldReader<u8, u8>;
36#[doc = "Field `CTRLDIR` reader - Control Direction"]
37pub type CTRLDIR_R = crate::BitReader<CTRLDIRSELECT_A>;
38#[doc = "Control Direction\n\nValue on reset: 0"]
39#[derive(Clone, Copy, Debug, PartialEq, Eq)]
40pub enum CTRLDIRSELECT_A {
41    #[doc = "0: `0`"]
42    OUT = 0,
43    #[doc = "1: `1`"]
44    IN = 1,
45}
46impl From<CTRLDIRSELECT_A> for bool {
47    #[inline(always)]
48    fn from(variant: CTRLDIRSELECT_A) -> Self {
49        variant as u8 != 0
50    }
51}
52impl CTRLDIR_R {
53    #[doc = "Get enumerated values variant"]
54    #[inline(always)]
55    pub fn variant(&self) -> CTRLDIRSELECT_A {
56        match self.bits {
57            false => CTRLDIRSELECT_A::OUT,
58            true => CTRLDIRSELECT_A::IN,
59        }
60    }
61    #[doc = "Checks if the value of the field is `OUT`"]
62    #[inline(always)]
63    pub fn is_out(&self) -> bool {
64        *self == CTRLDIRSELECT_A::OUT
65    }
66    #[doc = "Checks if the value of the field is `IN`"]
67    #[inline(always)]
68    pub fn is_in(&self) -> bool {
69        *self == CTRLDIRSELECT_A::IN
70    }
71}
72impl R {
73    #[doc = "Bit 0 - Transmitted IN Data Interrupt"]
74    #[inline(always)]
75    pub fn txini(&self) -> TXINI_R {
76        TXINI_R::new((self.bits & 1) != 0)
77    }
78    #[doc = "Bit 1 - Received OUT Data Interrupt"]
79    #[inline(always)]
80    pub fn rxouti(&self) -> RXOUTI_R {
81        RXOUTI_R::new(((self.bits >> 1) & 1) != 0)
82    }
83    #[doc = "Bit 2 - Received SETUP Interrupt"]
84    #[inline(always)]
85    pub fn rxstpi(&self) -> RXSTPI_R {
86        RXSTPI_R::new(((self.bits >> 2) & 1) != 0)
87    }
88    #[doc = "Bit 3 - NAKed OUT Interrupt"]
89    #[inline(always)]
90    pub fn nakouti(&self) -> NAKOUTI_R {
91        NAKOUTI_R::new(((self.bits >> 3) & 1) != 0)
92    }
93    #[doc = "Bit 4 - NAKed IN Interrupt"]
94    #[inline(always)]
95    pub fn nakini(&self) -> NAKINI_R {
96        NAKINI_R::new(((self.bits >> 4) & 1) != 0)
97    }
98    #[doc = "Bit 6 - STALLed Interrupt"]
99    #[inline(always)]
100    pub fn stalledi(&self) -> STALLEDI_R {
101        STALLEDI_R::new(((self.bits >> 6) & 1) != 0)
102    }
103    #[doc = "Bits 8:9 - Data Toggle Sequence"]
104    #[inline(always)]
105    pub fn dtseq(&self) -> DTSEQ_R {
106        DTSEQ_R::new(((self.bits >> 8) & 3) as u8)
107    }
108    #[doc = "Bit 11 - Ram Access Error Interrupt"]
109    #[inline(always)]
110    pub fn ramaceri(&self) -> RAMACERI_R {
111        RAMACERI_R::new(((self.bits >> 11) & 1) != 0)
112    }
113    #[doc = "Bits 12:13 - Number Of Busy Banks"]
114    #[inline(always)]
115    pub fn nbusybk(&self) -> NBUSYBK_R {
116        NBUSYBK_R::new(((self.bits >> 12) & 3) as u8)
117    }
118    #[doc = "Bits 14:15 - Current Bank"]
119    #[inline(always)]
120    pub fn currbk(&self) -> CURRBK_R {
121        CURRBK_R::new(((self.bits >> 14) & 3) as u8)
122    }
123    #[doc = "Bit 17 - Control Direction"]
124    #[inline(always)]
125    pub fn ctrldir(&self) -> CTRLDIR_R {
126        CTRLDIR_R::new(((self.bits >> 17) & 1) != 0)
127    }
128}
129#[doc = "Endpoint Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uesta2](index.html) module"]
130pub struct UESTA2_SPEC;
131impl crate::RegisterSpec for UESTA2_SPEC {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [uesta2::R](R) reader structure"]
135impl crate::Readable for UESTA2_SPEC {
136    type Reader = R;
137}
138#[doc = "`reset()` method sets UESTA2 to value 0x0100"]
139impl crate::Resettable for UESTA2_SPEC {
140    const RESET_VALUE: Self::Ux = 0x0100;
141}
atsam4ls4b_pac/usbc/uesta2.rs

atsam4ls4b_pac/usbc/
uesta2.rs
