atsam4ls4b_pac/pm/
icr.rs

1#[doc = "Register `ICR` writer"]
2pub struct W(crate::W<ICR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<ICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<ICR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<ICR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CFD` writer - Clock Failure Detected Interrupt Status Clear"]
23pub type CFD_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
24#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Status Clear"]
25pub type CKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
26#[doc = "Field `WAKE` writer - Wake up Interrupt Status Clear"]
27pub type WAKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
28#[doc = "Field `AE` writer - Access Error Interrupt Status Clear"]
29pub type AE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
30impl W {
31    #[doc = "Bit 0 - Clock Failure Detected Interrupt Status Clear"]
32    #[inline(always)]
33    #[must_use]
34    pub fn cfd(&mut self) -> CFD_W<0> {
35        CFD_W::new(self)
36    }
37    #[doc = "Bit 5 - Clock Ready Interrupt Status Clear"]
38    #[inline(always)]
39    #[must_use]
40    pub fn ckrdy(&mut self) -> CKRDY_W<5> {
41        CKRDY_W::new(self)
42    }
43    #[doc = "Bit 8 - Wake up Interrupt Status Clear"]
44    #[inline(always)]
45    #[must_use]
46    pub fn wake(&mut self) -> WAKE_W<8> {
47        WAKE_W::new(self)
48    }
49    #[doc = "Bit 31 - Access Error Interrupt Status Clear"]
50    #[inline(always)]
51    #[must_use]
52    pub fn ae(&mut self) -> AE_W<31> {
53        AE_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"]
63pub struct ICR_SPEC;
64impl crate::RegisterSpec for ICR_SPEC {
65    type Ux = u32;
66}
67#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"]
68impl crate::Writable for ICR_SPEC {
69    type Writer = W;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
72}
73#[doc = "`reset()` method sets ICR to value 0"]
74impl crate::Resettable for ICR_SPEC {
75    const RESET_VALUE: Self::Ux = 0;
76}
atsam4ls4b_pac/pm/icr.rs

atsam4ls4b_pac/pm/
icr.rs
