atsam4ls4b_pac/pm/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CFD` writer - Clock Failure Detected Interrupt Enable"]
23pub type CFD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
24#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"]
25pub type CKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
26#[doc = "Wake up Interrupt Enable\n\nValue on reset: 0"]
27#[derive(Clone, Copy, Debug, PartialEq, Eq)]
28pub enum WAKESELECT_AW {
29    #[doc = "0: No effect"]
30    _0 = 0,
31    #[doc = "1: Disable Interrupt."]
32    _1 = 1,
33}
34impl From<WAKESELECT_AW> for bool {
35    #[inline(always)]
36    fn from(variant: WAKESELECT_AW) -> Self {
37        variant as u8 != 0
38    }
39}
40#[doc = "Field `WAKE` writer - Wake up Interrupt Enable"]
41pub type WAKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, WAKESELECT_AW, O>;
42impl<'a, const O: u8> WAKE_W<'a, O> {
43    #[doc = "No effect"]
44    #[inline(always)]
45    pub fn _0(self) -> &'a mut W {
46        self.variant(WAKESELECT_AW::_0)
47    }
48    #[doc = "Disable Interrupt."]
49    #[inline(always)]
50    pub fn _1(self) -> &'a mut W {
51        self.variant(WAKESELECT_AW::_1)
52    }
53}
54#[doc = "Field `AE` writer - Access Error Interrupt Enable"]
55pub type AE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
56impl W {
57    #[doc = "Bit 0 - Clock Failure Detected Interrupt Enable"]
58    #[inline(always)]
59    #[must_use]
60    pub fn cfd(&mut self) -> CFD_W<0> {
61        CFD_W::new(self)
62    }
63    #[doc = "Bit 5 - Clock Ready Interrupt Enable"]
64    #[inline(always)]
65    #[must_use]
66    pub fn ckrdy(&mut self) -> CKRDY_W<5> {
67        CKRDY_W::new(self)
68    }
69    #[doc = "Bit 8 - Wake up Interrupt Enable"]
70    #[inline(always)]
71    #[must_use]
72    pub fn wake(&mut self) -> WAKE_W<8> {
73        WAKE_W::new(self)
74    }
75    #[doc = "Bit 31 - Access Error Interrupt Enable"]
76    #[inline(always)]
77    #[must_use]
78    pub fn ae(&mut self) -> AE_W<31> {
79        AE_W::new(self)
80    }
81    #[doc = "Writes raw bits to the register."]
82    #[inline(always)]
83    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
84        self.0.bits(bits);
85        self
86    }
87}
88#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
89pub struct IER_SPEC;
90impl crate::RegisterSpec for IER_SPEC {
91    type Ux = u32;
92}
93#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
94impl crate::Writable for IER_SPEC {
95    type Writer = W;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
98}
99#[doc = "`reset()` method sets IER to value 0"]
100impl crate::Resettable for IER_SPEC {
101    const RESET_VALUE: Self::Ux = 0;
102}
atsam4ls4b_pac/pm/ier.rs

atsam4ls4b_pac/pm/
ier.rs
