atsam4ls4a_pac/pdca/
pwlat0.rs

1#[doc = "Register `PWLAT0` reader"]
2pub struct R(crate::R<PWLAT0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PWLAT0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PWLAT0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PWLAT0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `LAT` reader - Maximum transfer initiation cycles counted since last reset"]
17pub type LAT_R = crate::FieldReader<u16, u16>;
18impl R {
19    #[doc = "Bits 0:15 - Maximum transfer initiation cycles counted since last reset"]
20    #[inline(always)]
21    pub fn lat(&self) -> LAT_R {
22        LAT_R::new((self.bits & 0xffff) as u16)
23    }
24}
25#[doc = "Channel0 Write Max Latency\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwlat0](index.html) module"]
26pub struct PWLAT0_SPEC;
27impl crate::RegisterSpec for PWLAT0_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [pwlat0::R](R) reader structure"]
31impl crate::Readable for PWLAT0_SPEC {
32    type Reader = R;
33}
34#[doc = "`reset()` method sets PWLAT0 to value 0"]
35impl crate::Resettable for PWLAT0_SPEC {
36    const RESET_VALUE: Self::Ux = 0;
37}
atsam4ls4a_pac/pdca/pwlat0.rs

atsam4ls4a_pac/pdca/
pwlat0.rs
