atsam4ls2c_pac/tc0/
ccr.rs

1#[doc = "Register `CCR%s` writer"]
2pub struct W(crate::W<CCR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CCR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CCR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Counter Clock Enable Command\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum CLKENSELECT_AW {
25    #[doc = "0: No effect."]
26    _0 = 0,
27    #[doc = "1: Enables the clock if CLKDIS is not 1."]
28    _1 = 1,
29}
30impl From<CLKENSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: CLKENSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `CLKEN` writer - Counter Clock Enable Command"]
37pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, CLKENSELECT_AW, O>;
38impl<'a, const O: u8> CLKEN_W<'a, O> {
39    #[doc = "No effect."]
40    #[inline(always)]
41    pub fn _0(self) -> &'a mut W {
42        self.variant(CLKENSELECT_AW::_0)
43    }
44    #[doc = "Enables the clock if CLKDIS is not 1."]
45    #[inline(always)]
46    pub fn _1(self) -> &'a mut W {
47        self.variant(CLKENSELECT_AW::_1)
48    }
49}
50#[doc = "Counter Clock Disable Command\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum CLKDISSELECT_AW {
53    #[doc = "0: No effect."]
54    _0 = 0,
55    #[doc = "1: Disables the clock."]
56    _1 = 1,
57}
58impl From<CLKDISSELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: CLKDISSELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `CLKDIS` writer - Counter Clock Disable Command"]
65pub type CLKDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, CLKDISSELECT_AW, O>;
66impl<'a, const O: u8> CLKDIS_W<'a, O> {
67    #[doc = "No effect."]
68    #[inline(always)]
69    pub fn _0(self) -> &'a mut W {
70        self.variant(CLKDISSELECT_AW::_0)
71    }
72    #[doc = "Disables the clock."]
73    #[inline(always)]
74    pub fn _1(self) -> &'a mut W {
75        self.variant(CLKDISSELECT_AW::_1)
76    }
77}
78#[doc = "Software Trigger Command\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum SWTRGSELECT_AW {
81    #[doc = "0: No effect."]
82    _0 = 0,
83    #[doc = "1: A software trigger is performed:the counter is reset and clock is started."]
84    _1 = 1,
85}
86impl From<SWTRGSELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: SWTRGSELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `SWTRG` writer - Software Trigger Command"]
93pub type SWTRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, SWTRGSELECT_AW, O>;
94impl<'a, const O: u8> SWTRG_W<'a, O> {
95    #[doc = "No effect."]
96    #[inline(always)]
97    pub fn _0(self) -> &'a mut W {
98        self.variant(SWTRGSELECT_AW::_0)
99    }
100    #[doc = "A software trigger is performed:the counter is reset and clock is started."]
101    #[inline(always)]
102    pub fn _1(self) -> &'a mut W {
103        self.variant(SWTRGSELECT_AW::_1)
104    }
105}
106impl W {
107    #[doc = "Bit 0 - Counter Clock Enable Command"]
108    #[inline(always)]
109    #[must_use]
110    pub fn clken(&mut self) -> CLKEN_W<0> {
111        CLKEN_W::new(self)
112    }
113    #[doc = "Bit 1 - Counter Clock Disable Command"]
114    #[inline(always)]
115    #[must_use]
116    pub fn clkdis(&mut self) -> CLKDIS_W<1> {
117        CLKDIS_W::new(self)
118    }
119    #[doc = "Bit 2 - Software Trigger Command"]
120    #[inline(always)]
121    #[must_use]
122    pub fn swtrg(&mut self) -> SWTRG_W<2> {
123        SWTRG_W::new(self)
124    }
125    #[doc = "Writes raw bits to the register."]
126    #[inline(always)]
127    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
128        self.0.bits(bits);
129        self
130    }
131}
132#[doc = "Channel Control Register Channel\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"]
133pub struct CCR_SPEC;
134impl crate::RegisterSpec for CCR_SPEC {
135    type Ux = u32;
136}
137#[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"]
138impl crate::Writable for CCR_SPEC {
139    type Writer = W;
140    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
141    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
142}
143#[doc = "`reset()` method sets CCR%s to value 0"]
144impl crate::Resettable for CCR_SPEC {
145    const RESET_VALUE: Self::Ux = 0;
146}
atsam4ls2c_pac/tc0/ccr.rs

atsam4ls2c_pac/tc0/
ccr.rs
