atsam4ls2c_pac/ast/
clock.rs

1#[doc = "Register `CLOCK` reader"]
2pub struct R(crate::R<CLOCK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLOCK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLOCK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLOCK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLOCK` writer"]
17pub struct W(crate::W<CLOCK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLOCK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLOCK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLOCK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CEN` reader - Clock Enable"]
38pub type CEN_R = crate::BitReader<CENSELECT_A>;
39#[doc = "Clock Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum CENSELECT_A {
42    #[doc = "0: The clock is disabled"]
43    _0 = 0,
44    #[doc = "1: The clock is enabled"]
45    _1 = 1,
46}
47impl From<CENSELECT_A> for bool {
48    #[inline(always)]
49    fn from(variant: CENSELECT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl CEN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> CENSELECT_A {
57        match self.bits {
58            false => CENSELECT_A::_0,
59            true => CENSELECT_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == CENSELECT_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == CENSELECT_A::_1
71    }
72}
73#[doc = "Field `CEN` writer - Clock Enable"]
74pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLOCK_SPEC, CENSELECT_A, O>;
75impl<'a, const O: u8> CEN_W<'a, O> {
76    #[doc = "The clock is disabled"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(CENSELECT_A::_0)
80    }
81    #[doc = "The clock is enabled"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(CENSELECT_A::_1)
85    }
86}
87#[doc = "Field `CSSEL` reader - Clock Source Selection"]
88pub type CSSEL_R = crate::FieldReader<u8, CSSELSELECT_A>;
89#[doc = "Clock Source Selection\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91#[repr(u8)]
92pub enum CSSELSELECT_A {
93    #[doc = "0: Slow clock"]
94    SLOWCLOCK = 0,
95    #[doc = "1: 32 kHz clock"]
96    _32KHZCLK = 1,
97    #[doc = "2: PB clock"]
98    PBCLOCK = 2,
99    #[doc = "3: Generic clock"]
100    GCLK = 3,
101    #[doc = "4: 1kHz clock from 32 kHz oscillator"]
102    _1KHZCLK = 4,
103}
104impl From<CSSELSELECT_A> for u8 {
105    #[inline(always)]
106    fn from(variant: CSSELSELECT_A) -> Self {
107        variant as _
108    }
109}
110impl CSSEL_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub fn variant(&self) -> Option<CSSELSELECT_A> {
114        match self.bits {
115            0 => Some(CSSELSELECT_A::SLOWCLOCK),
116            1 => Some(CSSELSELECT_A::_32KHZCLK),
117            2 => Some(CSSELSELECT_A::PBCLOCK),
118            3 => Some(CSSELSELECT_A::GCLK),
119            4 => Some(CSSELSELECT_A::_1KHZCLK),
120            _ => None,
121        }
122    }
123    #[doc = "Checks if the value of the field is `SLOWCLOCK`"]
124    #[inline(always)]
125    pub fn is_slowclock(&self) -> bool {
126        *self == CSSELSELECT_A::SLOWCLOCK
127    }
128    #[doc = "Checks if the value of the field is `_32KHZCLK`"]
129    #[inline(always)]
130    pub fn is_32khzclk(&self) -> bool {
131        *self == CSSELSELECT_A::_32KHZCLK
132    }
133    #[doc = "Checks if the value of the field is `PBCLOCK`"]
134    #[inline(always)]
135    pub fn is_pbclock(&self) -> bool {
136        *self == CSSELSELECT_A::PBCLOCK
137    }
138    #[doc = "Checks if the value of the field is `GCLK`"]
139    #[inline(always)]
140    pub fn is_gclk(&self) -> bool {
141        *self == CSSELSELECT_A::GCLK
142    }
143    #[doc = "Checks if the value of the field is `_1KHZCLK`"]
144    #[inline(always)]
145    pub fn is_1khzclk(&self) -> bool {
146        *self == CSSELSELECT_A::_1KHZCLK
147    }
148}
149#[doc = "Field `CSSEL` writer - Clock Source Selection"]
150pub type CSSEL_W<'a, const O: u8> =
151    crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, CSSELSELECT_A, 3, O>;
152impl<'a, const O: u8> CSSEL_W<'a, O> {
153    #[doc = "Slow clock"]
154    #[inline(always)]
155    pub fn slowclock(self) -> &'a mut W {
156        self.variant(CSSELSELECT_A::SLOWCLOCK)
157    }
158    #[doc = "32 kHz clock"]
159    #[inline(always)]
160    pub fn _32khzclk(self) -> &'a mut W {
161        self.variant(CSSELSELECT_A::_32KHZCLK)
162    }
163    #[doc = "PB clock"]
164    #[inline(always)]
165    pub fn pbclock(self) -> &'a mut W {
166        self.variant(CSSELSELECT_A::PBCLOCK)
167    }
168    #[doc = "Generic clock"]
169    #[inline(always)]
170    pub fn gclk(self) -> &'a mut W {
171        self.variant(CSSELSELECT_A::GCLK)
172    }
173    #[doc = "1kHz clock from 32 kHz oscillator"]
174    #[inline(always)]
175    pub fn _1khzclk(self) -> &'a mut W {
176        self.variant(CSSELSELECT_A::_1KHZCLK)
177    }
178}
179impl R {
180    #[doc = "Bit 0 - Clock Enable"]
181    #[inline(always)]
182    pub fn cen(&self) -> CEN_R {
183        CEN_R::new((self.bits & 1) != 0)
184    }
185    #[doc = "Bits 8:10 - Clock Source Selection"]
186    #[inline(always)]
187    pub fn cssel(&self) -> CSSEL_R {
188        CSSEL_R::new(((self.bits >> 8) & 7) as u8)
189    }
190}
191impl W {
192    #[doc = "Bit 0 - Clock Enable"]
193    #[inline(always)]
194    #[must_use]
195    pub fn cen(&mut self) -> CEN_W<0> {
196        CEN_W::new(self)
197    }
198    #[doc = "Bits 8:10 - Clock Source Selection"]
199    #[inline(always)]
200    #[must_use]
201    pub fn cssel(&mut self) -> CSSEL_W<8> {
202        CSSEL_W::new(self)
203    }
204    #[doc = "Writes raw bits to the register."]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.0.bits(bits);
208        self
209    }
210}
211#[doc = "Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"]
212pub struct CLOCK_SPEC;
213impl crate::RegisterSpec for CLOCK_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [clock::R](R) reader structure"]
217impl crate::Readable for CLOCK_SPEC {
218    type Reader = R;
219}
220#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"]
221impl crate::Writable for CLOCK_SPEC {
222    type Writer = W;
223    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
224    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225}
226#[doc = "`reset()` method sets CLOCK to value 0"]
227impl crate::Resettable for CLOCK_SPEC {
228    const RESET_VALUE: Self::Ux = 0;
229}
atsam4ls2c_pac/ast/clock.rs

atsam4ls2c_pac/ast/
clock.rs
