atsam4ls2c_pac/twim0/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RXRDY` writer - RHR Data Ready"]
23pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
24#[doc = "Field `TXRDY` writer - THR Data Ready"]
25pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
26#[doc = "Field `CRDY` writer - Ready for More Commands"]
27pub type CRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
28#[doc = "Field `CCOMP` writer - Command Complete"]
29pub type CCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
30#[doc = "Field `IDLE` writer - Master Interface is Idle"]
31pub type IDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
32#[doc = "Field `BUSFREE` writer - Two-wire Bus is Free"]
33pub type BUSFREE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
34#[doc = "Field `ANAK` writer - NAK in Address Phase Received"]
35pub type ANAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
36#[doc = "Field `DNAK` writer - NAK in Data Phase Received"]
37pub type DNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
38#[doc = "Field `ARBLST` writer - Arbitration Lost"]
39pub type ARBLST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
40#[doc = "Field `SMBALERT` writer - SMBus Alert"]
41pub type SMBALERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
42#[doc = "Field `TOUT` writer - Timeout"]
43pub type TOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
44#[doc = "Field `PECERR` writer - PEC Error"]
45pub type PECERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
46#[doc = "Field `STOP` writer - Stop Request Accepted"]
47pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
48#[doc = "Field `HSMCACK` writer - ACK in HS-mode Master Code Phase Received"]
49pub type HSMCACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
50impl W {
51    #[doc = "Bit 0 - RHR Data Ready"]
52    #[inline(always)]
53    #[must_use]
54    pub fn rxrdy(&mut self) -> RXRDY_W<0> {
55        RXRDY_W::new(self)
56    }
57    #[doc = "Bit 1 - THR Data Ready"]
58    #[inline(always)]
59    #[must_use]
60    pub fn txrdy(&mut self) -> TXRDY_W<1> {
61        TXRDY_W::new(self)
62    }
63    #[doc = "Bit 2 - Ready for More Commands"]
64    #[inline(always)]
65    #[must_use]
66    pub fn crdy(&mut self) -> CRDY_W<2> {
67        CRDY_W::new(self)
68    }
69    #[doc = "Bit 3 - Command Complete"]
70    #[inline(always)]
71    #[must_use]
72    pub fn ccomp(&mut self) -> CCOMP_W<3> {
73        CCOMP_W::new(self)
74    }
75    #[doc = "Bit 4 - Master Interface is Idle"]
76    #[inline(always)]
77    #[must_use]
78    pub fn idle(&mut self) -> IDLE_W<4> {
79        IDLE_W::new(self)
80    }
81    #[doc = "Bit 5 - Two-wire Bus is Free"]
82    #[inline(always)]
83    #[must_use]
84    pub fn busfree(&mut self) -> BUSFREE_W<5> {
85        BUSFREE_W::new(self)
86    }
87    #[doc = "Bit 8 - NAK in Address Phase Received"]
88    #[inline(always)]
89    #[must_use]
90    pub fn anak(&mut self) -> ANAK_W<8> {
91        ANAK_W::new(self)
92    }
93    #[doc = "Bit 9 - NAK in Data Phase Received"]
94    #[inline(always)]
95    #[must_use]
96    pub fn dnak(&mut self) -> DNAK_W<9> {
97        DNAK_W::new(self)
98    }
99    #[doc = "Bit 10 - Arbitration Lost"]
100    #[inline(always)]
101    #[must_use]
102    pub fn arblst(&mut self) -> ARBLST_W<10> {
103        ARBLST_W::new(self)
104    }
105    #[doc = "Bit 11 - SMBus Alert"]
106    #[inline(always)]
107    #[must_use]
108    pub fn smbalert(&mut self) -> SMBALERT_W<11> {
109        SMBALERT_W::new(self)
110    }
111    #[doc = "Bit 12 - Timeout"]
112    #[inline(always)]
113    #[must_use]
114    pub fn tout(&mut self) -> TOUT_W<12> {
115        TOUT_W::new(self)
116    }
117    #[doc = "Bit 13 - PEC Error"]
118    #[inline(always)]
119    #[must_use]
120    pub fn pecerr(&mut self) -> PECERR_W<13> {
121        PECERR_W::new(self)
122    }
123    #[doc = "Bit 14 - Stop Request Accepted"]
124    #[inline(always)]
125    #[must_use]
126    pub fn stop(&mut self) -> STOP_W<14> {
127        STOP_W::new(self)
128    }
129    #[doc = "Bit 17 - ACK in HS-mode Master Code Phase Received"]
130    #[inline(always)]
131    #[must_use]
132    pub fn hsmcack(&mut self) -> HSMCACK_W<17> {
133        HSMCACK_W::new(self)
134    }
135    #[doc = "Writes raw bits to the register."]
136    #[inline(always)]
137    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
138        self.0.bits(bits);
139        self
140    }
141}
142#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
143pub struct IER_SPEC;
144impl crate::RegisterSpec for IER_SPEC {
145    type Ux = u32;
146}
147#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
148impl crate::Writable for IER_SPEC {
149    type Writer = W;
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152}
153#[doc = "`reset()` method sets IER to value 0"]
154impl crate::Resettable for IER_SPEC {
155    const RESET_VALUE: Self::Ux = 0;
156}
atsam4ls2c_pac/twim0/ier.rs

atsam4ls2c_pac/twim0/
ier.rs
