atsam4ls2b_pac/abdacb/
scr.rs

1#[doc = "Register `SCR` writer"]
2pub struct W(crate::W<SCR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<SCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<SCR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<SCR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Transmit Ready Interrupt Clear\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum TXRDYSELECT_AW {
25    #[doc = "0: No effect"]
26    _0 = 0,
27    #[doc = "1: Clear the Audio DAC TX Ready interrupt"]
28    _1 = 1,
29}
30impl From<TXRDYSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: TXRDYSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Clear"]
37pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, TXRDYSELECT_AW, O>;
38impl<'a, const O: u8> TXRDY_W<'a, O> {
39    #[doc = "No effect"]
40    #[inline(always)]
41    pub fn _0(self) -> &'a mut W {
42        self.variant(TXRDYSELECT_AW::_0)
43    }
44    #[doc = "Clear the Audio DAC TX Ready interrupt"]
45    #[inline(always)]
46    pub fn _1(self) -> &'a mut W {
47        self.variant(TXRDYSELECT_AW::_1)
48    }
49}
50#[doc = "Transmit Underrun Interrupt Clear\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum TXURSELECT_AW {
53    #[doc = "0: No effect"]
54    _0 = 0,
55    #[doc = "1: Clear the Audio DAC Underrun interrupt"]
56    _1 = 1,
57}
58impl From<TXURSELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: TXURSELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `TXUR` writer - Transmit Underrun Interrupt Clear"]
65pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, TXURSELECT_AW, O>;
66impl<'a, const O: u8> TXUR_W<'a, O> {
67    #[doc = "No effect"]
68    #[inline(always)]
69    pub fn _0(self) -> &'a mut W {
70        self.variant(TXURSELECT_AW::_0)
71    }
72    #[doc = "Clear the Audio DAC Underrun interrupt"]
73    #[inline(always)]
74    pub fn _1(self) -> &'a mut W {
75        self.variant(TXURSELECT_AW::_1)
76    }
77}
78impl W {
79    #[doc = "Bit 1 - Transmit Ready Interrupt Clear"]
80    #[inline(always)]
81    #[must_use]
82    pub fn txrdy(&mut self) -> TXRDY_W<1> {
83        TXRDY_W::new(self)
84    }
85    #[doc = "Bit 2 - Transmit Underrun Interrupt Clear"]
86    #[inline(always)]
87    #[must_use]
88    pub fn txur(&mut self) -> TXUR_W<2> {
89        TXUR_W::new(self)
90    }
91    #[doc = "Writes raw bits to the register."]
92    #[inline(always)]
93    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94        self.0.bits(bits);
95        self
96    }
97}
98#[doc = "Status Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"]
99pub struct SCR_SPEC;
100impl crate::RegisterSpec for SCR_SPEC {
101    type Ux = u32;
102}
103#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"]
104impl crate::Writable for SCR_SPEC {
105    type Writer = W;
106    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108}
109#[doc = "`reset()` method sets SCR to value 0"]
110impl crate::Resettable for SCR_SPEC {
111    const RESET_VALUE: Self::Ux = 0;
112}
atsam4ls2b_pac/abdacb/scr.rs

atsam4ls2b_pac/abdacb/
scr.rs
