atsam4lc8b_pac/scif/
gcctrl.rs

1#[doc = "Register `GCCTRL%s` reader"]
2pub struct R(crate::R<GCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GCCTRL%s` writer"]
17pub struct W(crate::W<GCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CEN` reader - Clock Enable"]
38pub type CEN_R = crate::BitReader<bool>;
39#[doc = "Field `CEN` writer - Clock Enable"]
40pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCTRL_SPEC, bool, O>;
41#[doc = "Field `DIVEN` reader - Divide Enable"]
42pub type DIVEN_R = crate::BitReader<bool>;
43#[doc = "Field `DIVEN` writer - Divide Enable"]
44pub type DIVEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCCTRL_SPEC, bool, O>;
45#[doc = "Field `OSCSEL` reader - Clock Select"]
46pub type OSCSEL_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `OSCSEL` writer - Clock Select"]
48pub type OSCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GCCTRL_SPEC, u8, u8, 5, O>;
49#[doc = "Field `DIV` reader - Division Factor"]
50pub type DIV_R = crate::FieldReader<u16, u16>;
51#[doc = "Field `DIV` writer - Division Factor"]
52pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GCCTRL_SPEC, u16, u16, 16, O>;
53impl R {
54    #[doc = "Bit 0 - Clock Enable"]
55    #[inline(always)]
56    pub fn cen(&self) -> CEN_R {
57        CEN_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Divide Enable"]
60    #[inline(always)]
61    pub fn diven(&self) -> DIVEN_R {
62        DIVEN_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bits 8:12 - Clock Select"]
65    #[inline(always)]
66    pub fn oscsel(&self) -> OSCSEL_R {
67        OSCSEL_R::new(((self.bits >> 8) & 0x1f) as u8)
68    }
69    #[doc = "Bits 16:31 - Division Factor"]
70    #[inline(always)]
71    pub fn div(&self) -> DIV_R {
72        DIV_R::new(((self.bits >> 16) & 0xffff) as u16)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - Clock Enable"]
77    #[inline(always)]
78    #[must_use]
79    pub fn cen(&mut self) -> CEN_W<0> {
80        CEN_W::new(self)
81    }
82    #[doc = "Bit 1 - Divide Enable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn diven(&mut self) -> DIVEN_W<1> {
86        DIVEN_W::new(self)
87    }
88    #[doc = "Bits 8:12 - Clock Select"]
89    #[inline(always)]
90    #[must_use]
91    pub fn oscsel(&mut self) -> OSCSEL_W<8> {
92        OSCSEL_W::new(self)
93    }
94    #[doc = "Bits 16:31 - Division Factor"]
95    #[inline(always)]
96    #[must_use]
97    pub fn div(&mut self) -> DIV_W<16> {
98        DIV_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Generic Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcctrl](index.html) module"]
108pub struct GCCTRL_SPEC;
109impl crate::RegisterSpec for GCCTRL_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [gcctrl::R](R) reader structure"]
113impl crate::Readable for GCCTRL_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [gcctrl::W](W) writer structure"]
117impl crate::Writable for GCCTRL_SPEC {
118    type Writer = W;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets GCCTRL%s to value 0"]
123impl crate::Resettable for GCCTRL_SPEC {
124    const RESET_VALUE: Self::Ux = 0;
125}
atsam4lc8b_pac/scif/gcctrl.rs

atsam4lc8b_pac/scif/
gcctrl.rs
