atsam4lc8b_pac/pm/
sr.rs

1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CFD` reader - Clock Failure Detected"]
17pub type CFD_R = crate::BitReader<bool>;
18#[doc = "Field `OCP` reader - Over Clock Detected"]
19pub type OCP_R = crate::BitReader<bool>;
20#[doc = "Field `CKRDY` reader - Clock Ready"]
21pub type CKRDY_R = crate::BitReader<bool>;
22#[doc = "Field `WAKE` reader - Wake up"]
23pub type WAKE_R = crate::BitReader<WAKESELECT_A>;
24#[doc = "Wake up\n\nValue on reset: 0"]
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum WAKESELECT_A {
27    #[doc = "0: No effect"]
28    _0 = 0,
29    #[doc = "1: Disable Interrupt."]
30    _1 = 1,
31}
32impl From<WAKESELECT_A> for bool {
33    #[inline(always)]
34    fn from(variant: WAKESELECT_A) -> Self {
35        variant as u8 != 0
36    }
37}
38impl WAKE_R {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub fn variant(&self) -> WAKESELECT_A {
42        match self.bits {
43            false => WAKESELECT_A::_0,
44            true => WAKESELECT_A::_1,
45        }
46    }
47    #[doc = "Checks if the value of the field is `_0`"]
48    #[inline(always)]
49    pub fn is_0(&self) -> bool {
50        *self == WAKESELECT_A::_0
51    }
52    #[doc = "Checks if the value of the field is `_1`"]
53    #[inline(always)]
54    pub fn is_1(&self) -> bool {
55        *self == WAKESELECT_A::_1
56    }
57}
58#[doc = "Field `PERRDY` reader - Peripheral Ready"]
59pub type PERRDY_R = crate::BitReader<bool>;
60#[doc = "Field `AE` reader - Access Error"]
61pub type AE_R = crate::BitReader<bool>;
62impl R {
63    #[doc = "Bit 0 - Clock Failure Detected"]
64    #[inline(always)]
65    pub fn cfd(&self) -> CFD_R {
66        CFD_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bit 1 - Over Clock Detected"]
69    #[inline(always)]
70    pub fn ocp(&self) -> OCP_R {
71        OCP_R::new(((self.bits >> 1) & 1) != 0)
72    }
73    #[doc = "Bit 5 - Clock Ready"]
74    #[inline(always)]
75    pub fn ckrdy(&self) -> CKRDY_R {
76        CKRDY_R::new(((self.bits >> 5) & 1) != 0)
77    }
78    #[doc = "Bit 8 - Wake up"]
79    #[inline(always)]
80    pub fn wake(&self) -> WAKE_R {
81        WAKE_R::new(((self.bits >> 8) & 1) != 0)
82    }
83    #[doc = "Bit 28 - Peripheral Ready"]
84    #[inline(always)]
85    pub fn perrdy(&self) -> PERRDY_R {
86        PERRDY_R::new(((self.bits >> 28) & 1) != 0)
87    }
88    #[doc = "Bit 31 - Access Error"]
89    #[inline(always)]
90    pub fn ae(&self) -> AE_R {
91        AE_R::new(((self.bits >> 31) & 1) != 0)
92    }
93}
94#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
95pub struct SR_SPEC;
96impl crate::RegisterSpec for SR_SPEC {
97    type Ux = u32;
98}
99#[doc = "`read()` method returns [sr::R](R) reader structure"]
100impl crate::Readable for SR_SPEC {
101    type Reader = R;
102}
103#[doc = "`reset()` method sets SR to value 0"]
104impl crate::Resettable for SR_SPEC {
105    const RESET_VALUE: Self::Ux = 0;
106}
atsam4lc8b_pac/pm/sr.rs

atsam4lc8b_pac/pm/
sr.rs
