atsam4lc8b_pac/bscif/
icr.rs

1#[doc = "Register `ICR` writer"]
2pub struct W(crate::W<ICR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<ICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<ICR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<ICR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `OSC32RDY` writer - 32kHz Oscillator Ready"]
23pub type OSC32RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
24#[doc = "Field `RC32KRDY` writer - 32kHz RC Oscillator Ready"]
25pub type RC32KRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
26#[doc = "Field `RC32KLOCK` writer - 32kHz RC Oscillator Lock"]
27pub type RC32KLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
28#[doc = "Field `RC32KREFE` writer - 32kHz RC Oscillator Reference Error"]
29pub type RC32KREFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
30#[doc = "Field `RC32KSAT` writer - 32kHz RC Oscillator Saturation"]
31pub type RC32KSAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
32#[doc = "Field `BOD33DET` writer - BOD33 Detected"]
33pub type BOD33DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
34#[doc = "Field `BOD18DET` writer - BOD18 Detected"]
35pub type BOD18DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
36#[doc = "Field `BOD33SYNRDY` writer - BOD33 Synchronization Ready"]
37pub type BOD33SYNRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
38#[doc = "Field `BOD18SYNRDY` writer - BOD18 Synchronization Ready"]
39pub type BOD18SYNRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
40#[doc = "Field `SSWRDY` writer - VREG Stop Switching Ready"]
41pub type SSWRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
42#[doc = "Field `VREGOK` writer - Main VREG OK"]
43pub type VREGOK_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
44#[doc = "Field `LPBGRDY` writer - Low Power Bandgap Voltage Reference Ready"]
45pub type LPBGRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
46#[doc = "Field `AE` writer - Access Error"]
47pub type AE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
48impl W {
49    #[doc = "Bit 0 - 32kHz Oscillator Ready"]
50    #[inline(always)]
51    #[must_use]
52    pub fn osc32rdy(&mut self) -> OSC32RDY_W<0> {
53        OSC32RDY_W::new(self)
54    }
55    #[doc = "Bit 1 - 32kHz RC Oscillator Ready"]
56    #[inline(always)]
57    #[must_use]
58    pub fn rc32krdy(&mut self) -> RC32KRDY_W<1> {
59        RC32KRDY_W::new(self)
60    }
61    #[doc = "Bit 2 - 32kHz RC Oscillator Lock"]
62    #[inline(always)]
63    #[must_use]
64    pub fn rc32klock(&mut self) -> RC32KLOCK_W<2> {
65        RC32KLOCK_W::new(self)
66    }
67    #[doc = "Bit 3 - 32kHz RC Oscillator Reference Error"]
68    #[inline(always)]
69    #[must_use]
70    pub fn rc32krefe(&mut self) -> RC32KREFE_W<3> {
71        RC32KREFE_W::new(self)
72    }
73    #[doc = "Bit 4 - 32kHz RC Oscillator Saturation"]
74    #[inline(always)]
75    #[must_use]
76    pub fn rc32ksat(&mut self) -> RC32KSAT_W<4> {
77        RC32KSAT_W::new(self)
78    }
79    #[doc = "Bit 5 - BOD33 Detected"]
80    #[inline(always)]
81    #[must_use]
82    pub fn bod33det(&mut self) -> BOD33DET_W<5> {
83        BOD33DET_W::new(self)
84    }
85    #[doc = "Bit 6 - BOD18 Detected"]
86    #[inline(always)]
87    #[must_use]
88    pub fn bod18det(&mut self) -> BOD18DET_W<6> {
89        BOD18DET_W::new(self)
90    }
91    #[doc = "Bit 7 - BOD33 Synchronization Ready"]
92    #[inline(always)]
93    #[must_use]
94    pub fn bod33synrdy(&mut self) -> BOD33SYNRDY_W<7> {
95        BOD33SYNRDY_W::new(self)
96    }
97    #[doc = "Bit 8 - BOD18 Synchronization Ready"]
98    #[inline(always)]
99    #[must_use]
100    pub fn bod18synrdy(&mut self) -> BOD18SYNRDY_W<8> {
101        BOD18SYNRDY_W::new(self)
102    }
103    #[doc = "Bit 9 - VREG Stop Switching Ready"]
104    #[inline(always)]
105    #[must_use]
106    pub fn sswrdy(&mut self) -> SSWRDY_W<9> {
107        SSWRDY_W::new(self)
108    }
109    #[doc = "Bit 10 - Main VREG OK"]
110    #[inline(always)]
111    #[must_use]
112    pub fn vregok(&mut self) -> VREGOK_W<10> {
113        VREGOK_W::new(self)
114    }
115    #[doc = "Bit 12 - Low Power Bandgap Voltage Reference Ready"]
116    #[inline(always)]
117    #[must_use]
118    pub fn lpbgrdy(&mut self) -> LPBGRDY_W<12> {
119        LPBGRDY_W::new(self)
120    }
121    #[doc = "Bit 31 - Access Error"]
122    #[inline(always)]
123    #[must_use]
124    pub fn ae(&mut self) -> AE_W<31> {
125        AE_W::new(self)
126    }
127    #[doc = "Writes raw bits to the register."]
128    #[inline(always)]
129    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
130        self.0.bits(bits);
131        self
132    }
133}
134#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"]
135pub struct ICR_SPEC;
136impl crate::RegisterSpec for ICR_SPEC {
137    type Ux = u32;
138}
139#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"]
140impl crate::Writable for ICR_SPEC {
141    type Writer = W;
142    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
143    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
144}
145#[doc = "`reset()` method sets ICR to value 0"]
146impl crate::Resettable for ICR_SPEC {
147    const RESET_VALUE: Self::Ux = 0;
148}
atsam4lc8b_pac/bscif/icr.rs

atsam4lc8b_pac/bscif/
icr.rs
