atsam4lc8a_pac/usbc/
uecon3.rs

1#[doc = "Register `UECON3` reader"]
2pub struct R(crate::R<UECON3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UECON3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UECON3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UECON3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `TXINE` reader - TXIN Interrupt Enable"]
17pub type TXINE_R = crate::BitReader<bool>;
18#[doc = "Field `RXOUTE` reader - RXOUT Interrupt Enable"]
19pub type RXOUTE_R = crate::BitReader<bool>;
20#[doc = "Field `RXSTPE` reader - RXSTP Interrupt Enable"]
21pub type RXSTPE_R = crate::BitReader<bool>;
22#[doc = "Field `NAKOUTE` reader - NAKOUT Interrupt Enable"]
23pub type NAKOUTE_R = crate::BitReader<bool>;
24#[doc = "Field `NAKINE` reader - NAKIN Interrupt Enable"]
25pub type NAKINE_R = crate::BitReader<bool>;
26#[doc = "Field `STALLEDE` reader - STALLED Interrupt Enable"]
27pub type STALLEDE_R = crate::BitReader<bool>;
28#[doc = "Field `NREPLY` reader - No Reply"]
29pub type NREPLY_R = crate::BitReader<bool>;
30#[doc = "Field `RAMACERE` reader - RAMACER Interrupt Enable"]
31pub type RAMACERE_R = crate::BitReader<bool>;
32#[doc = "Field `NBUSYBKE` reader - Number of Busy Banks Interrupt Enable"]
33pub type NBUSYBKE_R = crate::BitReader<bool>;
34#[doc = "Field `KILLBK` reader - Kill IN Bank"]
35pub type KILLBK_R = crate::BitReader<bool>;
36#[doc = "Field `FIFOCON` reader - FIFO Control"]
37pub type FIFOCON_R = crate::BitReader<bool>;
38#[doc = "Field `NYETDIS` reader - NYET Token Enable"]
39pub type NYETDIS_R = crate::BitReader<bool>;
40#[doc = "Field `RSTDT` reader - Reset Data Toggle"]
41pub type RSTDT_R = crate::BitReader<bool>;
42#[doc = "Field `STALLRQ` reader - STALL Request"]
43pub type STALLRQ_R = crate::BitReader<bool>;
44#[doc = "Field `BUSY0` reader - Busy Bank1 Enable"]
45pub type BUSY0_R = crate::BitReader<bool>;
46#[doc = "Field `BUSY1` reader - Busy Bank0 Enable"]
47pub type BUSY1_R = crate::BitReader<bool>;
48impl R {
49    #[doc = "Bit 0 - TXIN Interrupt Enable"]
50    #[inline(always)]
51    pub fn txine(&self) -> TXINE_R {
52        TXINE_R::new((self.bits & 1) != 0)
53    }
54    #[doc = "Bit 1 - RXOUT Interrupt Enable"]
55    #[inline(always)]
56    pub fn rxoute(&self) -> RXOUTE_R {
57        RXOUTE_R::new(((self.bits >> 1) & 1) != 0)
58    }
59    #[doc = "Bit 2 - RXSTP Interrupt Enable"]
60    #[inline(always)]
61    pub fn rxstpe(&self) -> RXSTPE_R {
62        RXSTPE_R::new(((self.bits >> 2) & 1) != 0)
63    }
64    #[doc = "Bit 3 - NAKOUT Interrupt Enable"]
65    #[inline(always)]
66    pub fn nakoute(&self) -> NAKOUTE_R {
67        NAKOUTE_R::new(((self.bits >> 3) & 1) != 0)
68    }
69    #[doc = "Bit 4 - NAKIN Interrupt Enable"]
70    #[inline(always)]
71    pub fn nakine(&self) -> NAKINE_R {
72        NAKINE_R::new(((self.bits >> 4) & 1) != 0)
73    }
74    #[doc = "Bit 6 - STALLED Interrupt Enable"]
75    #[inline(always)]
76    pub fn stallede(&self) -> STALLEDE_R {
77        STALLEDE_R::new(((self.bits >> 6) & 1) != 0)
78    }
79    #[doc = "Bit 8 - No Reply"]
80    #[inline(always)]
81    pub fn nreply(&self) -> NREPLY_R {
82        NREPLY_R::new(((self.bits >> 8) & 1) != 0)
83    }
84    #[doc = "Bit 11 - RAMACER Interrupt Enable"]
85    #[inline(always)]
86    pub fn ramacere(&self) -> RAMACERE_R {
87        RAMACERE_R::new(((self.bits >> 11) & 1) != 0)
88    }
89    #[doc = "Bit 12 - Number of Busy Banks Interrupt Enable"]
90    #[inline(always)]
91    pub fn nbusybke(&self) -> NBUSYBKE_R {
92        NBUSYBKE_R::new(((self.bits >> 12) & 1) != 0)
93    }
94    #[doc = "Bit 13 - Kill IN Bank"]
95    #[inline(always)]
96    pub fn killbk(&self) -> KILLBK_R {
97        KILLBK_R::new(((self.bits >> 13) & 1) != 0)
98    }
99    #[doc = "Bit 14 - FIFO Control"]
100    #[inline(always)]
101    pub fn fifocon(&self) -> FIFOCON_R {
102        FIFOCON_R::new(((self.bits >> 14) & 1) != 0)
103    }
104    #[doc = "Bit 17 - NYET Token Enable"]
105    #[inline(always)]
106    pub fn nyetdis(&self) -> NYETDIS_R {
107        NYETDIS_R::new(((self.bits >> 17) & 1) != 0)
108    }
109    #[doc = "Bit 18 - Reset Data Toggle"]
110    #[inline(always)]
111    pub fn rstdt(&self) -> RSTDT_R {
112        RSTDT_R::new(((self.bits >> 18) & 1) != 0)
113    }
114    #[doc = "Bit 19 - STALL Request"]
115    #[inline(always)]
116    pub fn stallrq(&self) -> STALLRQ_R {
117        STALLRQ_R::new(((self.bits >> 19) & 1) != 0)
118    }
119    #[doc = "Bit 24 - Busy Bank1 Enable"]
120    #[inline(always)]
121    pub fn busy0(&self) -> BUSY0_R {
122        BUSY0_R::new(((self.bits >> 24) & 1) != 0)
123    }
124    #[doc = "Bit 25 - Busy Bank0 Enable"]
125    #[inline(always)]
126    pub fn busy1(&self) -> BUSY1_R {
127        BUSY1_R::new(((self.bits >> 25) & 1) != 0)
128    }
129}
130#[doc = "Endpoint Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uecon3](index.html) module"]
131pub struct UECON3_SPEC;
132impl crate::RegisterSpec for UECON3_SPEC {
133    type Ux = u32;
134}
135#[doc = "`read()` method returns [uecon3::R](R) reader structure"]
136impl crate::Readable for UECON3_SPEC {
137    type Reader = R;
138}
139#[doc = "`reset()` method sets UECON3 to value 0"]
140impl crate::Resettable for UECON3_SPEC {
141    const RESET_VALUE: Self::Ux = 0;
142}
atsam4lc8a_pac/usbc/uecon3.rs

atsam4lc8a_pac/usbc/
uecon3.rs
