atsam4lc4c_pac/wdt/
icr.rs

1#[doc = "Register `ICR` writer"]
2pub struct W(crate::W<ICR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<ICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<ICR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<ICR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `WINT` writer - Watchdog Interrupt"]
23pub type WINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
24impl W {
25    #[doc = "Bit 2 - Watchdog Interrupt"]
26    #[inline(always)]
27    #[must_use]
28    pub fn wint(&mut self) -> WINT_W<2> {
29        WINT_W::new(self)
30    }
31    #[doc = "Writes raw bits to the register."]
32    #[inline(always)]
33    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
34        self.0.bits(bits);
35        self
36    }
37}
38#[doc = "Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"]
39pub struct ICR_SPEC;
40impl crate::RegisterSpec for ICR_SPEC {
41    type Ux = u32;
42}
43#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"]
44impl crate::Writable for ICR_SPEC {
45    type Writer = W;
46    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
47    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
48}
49#[doc = "`reset()` method sets ICR to value 0"]
50impl crate::Resettable for ICR_SPEC {
51    const RESET_VALUE: Self::Ux = 0;
52}
atsam4lc4c_pac/wdt/icr.rs

atsam4lc4c_pac/wdt/
icr.rs
