Module atsam4lc4c_pac::twim0
source · Expand description
Two-wire Master Interface 0
Modules
- Command Register
- Control Register
- Clock Waveform Generator Register
- HS-mode Clock Waveform Generator
- HS-mode Slew Rate Register
- Interrupt Disable Register
- Interrupt Enable Register
- Interrupt Mask Register
- Next Command Register
- Parameter Register
- Receive Holding Register
- Status Clear Register
- SMBus Timing Register
- Status Register
- Slew Rate Register
- Transmit Holding Register
- Version Register
Structs
- Register block
Type Definitions
- CMDR (rw) register accessor: an alias for
Reg<CMDR_SPEC>
- CR (w) register accessor: an alias for
Reg<CR_SPEC>
- CWGR (rw) register accessor: an alias for
Reg<CWGR_SPEC>
- HSCWGR (rw) register accessor: an alias for
Reg<HSCWGR_SPEC>
- HSSRR (rw) register accessor: an alias for
Reg<HSSRR_SPEC>
- IDR (w) register accessor: an alias for
Reg<IDR_SPEC>
- IER (w) register accessor: an alias for
Reg<IER_SPEC>
- IMR (r) register accessor: an alias for
Reg<IMR_SPEC>
- NCMDR (rw) register accessor: an alias for
Reg<NCMDR_SPEC>
- PR (r) register accessor: an alias for
Reg<PR_SPEC>
- RHR (r) register accessor: an alias for
Reg<RHR_SPEC>
- SCR (w) register accessor: an alias for
Reg<SCR_SPEC>
- SMBTR (rw) register accessor: an alias for
Reg<SMBTR_SPEC>
- SR (r) register accessor: an alias for
Reg<SR_SPEC>
- SRR (rw) register accessor: an alias for
Reg<SRR_SPEC>
- THR (w) register accessor: an alias for
Reg<THR_SPEC>
- VR (r) register accessor: an alias for
Reg<VR_SPEC>