Module atsam4lc4c_pac::twis0
source · Expand description
Two-wire Slave Interface 0
Modules
- Control Register
- HS-mode Slew Rate Register
- HS-mode Timing Register
- Interrupt Disable Register
- Interrupt Enable Register
- Interrupt Mask Register
- NBYTES Register
- Packet Error Check Register
- Parameter Register
- Receive Holding Register
- Status Clear Register
- Status Register
- Slew Rate Register
- Transmit Holding Register
- Timing Register
- Version Register
Structs
- Register block
Type Definitions
- CR (rw) register accessor: an alias for
Reg<CR_SPEC>
- HSSRR (rw) register accessor: an alias for
Reg<HSSRR_SPEC>
- HSTR (rw) register accessor: an alias for
Reg<HSTR_SPEC>
- IDR (w) register accessor: an alias for
Reg<IDR_SPEC>
- IER (w) register accessor: an alias for
Reg<IER_SPEC>
- IMR (r) register accessor: an alias for
Reg<IMR_SPEC>
- NBYTES (rw) register accessor: an alias for
Reg<NBYTES_SPEC>
- PECR (r) register accessor: an alias for
Reg<PECR_SPEC>
- PR (r) register accessor: an alias for
Reg<PR_SPEC>
- RHR (r) register accessor: an alias for
Reg<RHR_SPEC>
- SCR (w) register accessor: an alias for
Reg<SCR_SPEC>
- SR (r) register accessor: an alias for
Reg<SR_SPEC>
- SRR (rw) register accessor: an alias for
Reg<SRR_SPEC>
- THR (w) register accessor: an alias for
Reg<THR_SPEC>
- TR (rw) register accessor: an alias for
Reg<TR_SPEC>
- VR (r) register accessor: an alias for
Reg<VR_SPEC>