atsam4lc4c_pac/iisc/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Receiver Ready Interrupt Enable\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum RXRDYSELECT_AW {
25    #[doc = "0: No effect"]
26    OFF = 0,
27    #[doc = "1: Enables the corresponding interrupt"]
28    ON = 1,
29}
30impl From<RXRDYSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: RXRDYSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `RXRDY` writer - Receiver Ready Interrupt Enable"]
37pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, RXRDYSELECT_AW, O>;
38impl<'a, const O: u8> RXRDY_W<'a, O> {
39    #[doc = "No effect"]
40    #[inline(always)]
41    pub fn off(self) -> &'a mut W {
42        self.variant(RXRDYSELECT_AW::OFF)
43    }
44    #[doc = "Enables the corresponding interrupt"]
45    #[inline(always)]
46    pub fn on(self) -> &'a mut W {
47        self.variant(RXRDYSELECT_AW::ON)
48    }
49}
50#[doc = "Receive Overrun Interrupt Enable\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum RXORSELECT_AW {
53    #[doc = "0: No effect"]
54    OFF = 0,
55    #[doc = "1: Enables the corresponding interrupt"]
56    ON = 1,
57}
58impl From<RXORSELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: RXORSELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `RXOR` writer - Receive Overrun Interrupt Enable"]
65pub type RXOR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, RXORSELECT_AW, O>;
66impl<'a, const O: u8> RXOR_W<'a, O> {
67    #[doc = "No effect"]
68    #[inline(always)]
69    pub fn off(self) -> &'a mut W {
70        self.variant(RXORSELECT_AW::OFF)
71    }
72    #[doc = "Enables the corresponding interrupt"]
73    #[inline(always)]
74    pub fn on(self) -> &'a mut W {
75        self.variant(RXORSELECT_AW::ON)
76    }
77}
78#[doc = "Transmit Ready Interrupt Enable\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum TXRDYSELECT_AW {
81    #[doc = "0: No effect"]
82    OFF = 0,
83    #[doc = "1: Enables the corresponding interrupt"]
84    ON = 1,
85}
86impl From<TXRDYSELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: TXRDYSELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Enable"]
93pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, TXRDYSELECT_AW, O>;
94impl<'a, const O: u8> TXRDY_W<'a, O> {
95    #[doc = "No effect"]
96    #[inline(always)]
97    pub fn off(self) -> &'a mut W {
98        self.variant(TXRDYSELECT_AW::OFF)
99    }
100    #[doc = "Enables the corresponding interrupt"]
101    #[inline(always)]
102    pub fn on(self) -> &'a mut W {
103        self.variant(TXRDYSELECT_AW::ON)
104    }
105}
106#[doc = "Transmit Underrun Interrupt Enable\n\nValue on reset: 0"]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum TXURSELECT_AW {
109    #[doc = "0: No effect"]
110    OFF = 0,
111    #[doc = "1: Enables the corresponding interrupt"]
112    ON = 1,
113}
114impl From<TXURSELECT_AW> for bool {
115    #[inline(always)]
116    fn from(variant: TXURSELECT_AW) -> Self {
117        variant as u8 != 0
118    }
119}
120#[doc = "Field `TXUR` writer - Transmit Underrun Interrupt Enable"]
121pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, TXURSELECT_AW, O>;
122impl<'a, const O: u8> TXUR_W<'a, O> {
123    #[doc = "No effect"]
124    #[inline(always)]
125    pub fn off(self) -> &'a mut W {
126        self.variant(TXURSELECT_AW::OFF)
127    }
128    #[doc = "Enables the corresponding interrupt"]
129    #[inline(always)]
130    pub fn on(self) -> &'a mut W {
131        self.variant(TXURSELECT_AW::ON)
132    }
133}
134impl W {
135    #[doc = "Bit 1 - Receiver Ready Interrupt Enable"]
136    #[inline(always)]
137    #[must_use]
138    pub fn rxrdy(&mut self) -> RXRDY_W<1> {
139        RXRDY_W::new(self)
140    }
141    #[doc = "Bit 2 - Receive Overrun Interrupt Enable"]
142    #[inline(always)]
143    #[must_use]
144    pub fn rxor(&mut self) -> RXOR_W<2> {
145        RXOR_W::new(self)
146    }
147    #[doc = "Bit 5 - Transmit Ready Interrupt Enable"]
148    #[inline(always)]
149    #[must_use]
150    pub fn txrdy(&mut self) -> TXRDY_W<5> {
151        TXRDY_W::new(self)
152    }
153    #[doc = "Bit 6 - Transmit Underrun Interrupt Enable"]
154    #[inline(always)]
155    #[must_use]
156    pub fn txur(&mut self) -> TXUR_W<6> {
157        TXUR_W::new(self)
158    }
159    #[doc = "Writes raw bits to the register."]
160    #[inline(always)]
161    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
162        self.0.bits(bits);
163        self
164    }
165}
166#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
167pub struct IER_SPEC;
168impl crate::RegisterSpec for IER_SPEC {
169    type Ux = u32;
170}
171#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
172impl crate::Writable for IER_SPEC {
173    type Writer = W;
174    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
175    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
176}
177#[doc = "`reset()` method sets IER to value 0"]
178impl crate::Resettable for IER_SPEC {
179    const RESET_VALUE: Self::Ux = 0;
180}
atsam4lc4c_pac/iisc/ier.rs

atsam4lc4c_pac/iisc/
ier.rs
