atsam4lc2b_pac/pdca/
pcontrol.rs

1#[doc = "Register `PCONTROL` reader"]
2pub struct R(crate::R<PCONTROL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PCONTROL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PCONTROL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PCONTROL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PCONTROL` writer"]
17pub struct W(crate::W<PCONTROL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PCONTROL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PCONTROL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PCONTROL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CH0EN` reader - Channel 0 Enabled"]
38pub type CH0EN_R = crate::BitReader<bool>;
39#[doc = "Field `CH0EN` writer - Channel 0 Enabled"]
40pub type CH0EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
41#[doc = "Field `CH1EN` reader - Channel 1 Enabled."]
42pub type CH1EN_R = crate::BitReader<bool>;
43#[doc = "Field `CH1EN` writer - Channel 1 Enabled."]
44pub type CH1EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
45#[doc = "Field `CH0OF` reader - Channel 0 Overflow Freeze"]
46pub type CH0OF_R = crate::BitReader<bool>;
47#[doc = "Field `CH0OF` writer - Channel 0 Overflow Freeze"]
48pub type CH0OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
49#[doc = "Field `CH1OF` reader - Channel 1 overflow freeze"]
50pub type CH1OF_R = crate::BitReader<bool>;
51#[doc = "Field `CH1OF` writer - Channel 1 overflow freeze"]
52pub type CH1OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
53#[doc = "Field `CH0RES` reader - Channel 0 counter reset"]
54pub type CH0RES_R = crate::BitReader<bool>;
55#[doc = "Field `CH0RES` writer - Channel 0 counter reset"]
56pub type CH0RES_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
57#[doc = "Field `CH1RES` reader - Channel 1 counter reset"]
58pub type CH1RES_R = crate::BitReader<bool>;
59#[doc = "Field `CH1RES` writer - Channel 1 counter reset"]
60pub type CH1RES_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCONTROL_SPEC, bool, O>;
61#[doc = "Field `MON0CH` reader - PDCA Channel to monitor with counter 0"]
62pub type MON0CH_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `MON0CH` writer - PDCA Channel to monitor with counter 0"]
64pub type MON0CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCONTROL_SPEC, u8, u8, 6, O>;
65#[doc = "Field `MON1CH` reader - PDCA Channel to monitor with counter 1"]
66pub type MON1CH_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `MON1CH` writer - PDCA Channel to monitor with counter 1"]
68pub type MON1CH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCONTROL_SPEC, u8, u8, 6, O>;
69impl R {
70    #[doc = "Bit 0 - Channel 0 Enabled"]
71    #[inline(always)]
72    pub fn ch0en(&self) -> CH0EN_R {
73        CH0EN_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Channel 1 Enabled."]
76    #[inline(always)]
77    pub fn ch1en(&self) -> CH1EN_R {
78        CH1EN_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 4 - Channel 0 Overflow Freeze"]
81    #[inline(always)]
82    pub fn ch0of(&self) -> CH0OF_R {
83        CH0OF_R::new(((self.bits >> 4) & 1) != 0)
84    }
85    #[doc = "Bit 5 - Channel 1 overflow freeze"]
86    #[inline(always)]
87    pub fn ch1of(&self) -> CH1OF_R {
88        CH1OF_R::new(((self.bits >> 5) & 1) != 0)
89    }
90    #[doc = "Bit 8 - Channel 0 counter reset"]
91    #[inline(always)]
92    pub fn ch0res(&self) -> CH0RES_R {
93        CH0RES_R::new(((self.bits >> 8) & 1) != 0)
94    }
95    #[doc = "Bit 9 - Channel 1 counter reset"]
96    #[inline(always)]
97    pub fn ch1res(&self) -> CH1RES_R {
98        CH1RES_R::new(((self.bits >> 9) & 1) != 0)
99    }
100    #[doc = "Bits 16:21 - PDCA Channel to monitor with counter 0"]
101    #[inline(always)]
102    pub fn mon0ch(&self) -> MON0CH_R {
103        MON0CH_R::new(((self.bits >> 16) & 0x3f) as u8)
104    }
105    #[doc = "Bits 24:29 - PDCA Channel to monitor with counter 1"]
106    #[inline(always)]
107    pub fn mon1ch(&self) -> MON1CH_R {
108        MON1CH_R::new(((self.bits >> 24) & 0x3f) as u8)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Channel 0 Enabled"]
113    #[inline(always)]
114    #[must_use]
115    pub fn ch0en(&mut self) -> CH0EN_W<0> {
116        CH0EN_W::new(self)
117    }
118    #[doc = "Bit 1 - Channel 1 Enabled."]
119    #[inline(always)]
120    #[must_use]
121    pub fn ch1en(&mut self) -> CH1EN_W<1> {
122        CH1EN_W::new(self)
123    }
124    #[doc = "Bit 4 - Channel 0 Overflow Freeze"]
125    #[inline(always)]
126    #[must_use]
127    pub fn ch0of(&mut self) -> CH0OF_W<4> {
128        CH0OF_W::new(self)
129    }
130    #[doc = "Bit 5 - Channel 1 overflow freeze"]
131    #[inline(always)]
132    #[must_use]
133    pub fn ch1of(&mut self) -> CH1OF_W<5> {
134        CH1OF_W::new(self)
135    }
136    #[doc = "Bit 8 - Channel 0 counter reset"]
137    #[inline(always)]
138    #[must_use]
139    pub fn ch0res(&mut self) -> CH0RES_W<8> {
140        CH0RES_W::new(self)
141    }
142    #[doc = "Bit 9 - Channel 1 counter reset"]
143    #[inline(always)]
144    #[must_use]
145    pub fn ch1res(&mut self) -> CH1RES_W<9> {
146        CH1RES_W::new(self)
147    }
148    #[doc = "Bits 16:21 - PDCA Channel to monitor with counter 0"]
149    #[inline(always)]
150    #[must_use]
151    pub fn mon0ch(&mut self) -> MON0CH_W<16> {
152        MON0CH_W::new(self)
153    }
154    #[doc = "Bits 24:29 - PDCA Channel to monitor with counter 1"]
155    #[inline(always)]
156    #[must_use]
157    pub fn mon1ch(&mut self) -> MON1CH_W<24> {
158        MON1CH_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Performance Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcontrol](index.html) module"]
168pub struct PCONTROL_SPEC;
169impl crate::RegisterSpec for PCONTROL_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [pcontrol::R](R) reader structure"]
173impl crate::Readable for PCONTROL_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [pcontrol::W](W) writer structure"]
177impl crate::Writable for PCONTROL_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets PCONTROL to value 0"]
183impl crate::Resettable for PCONTROL_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}
atsam4lc2b_pac/pdca/pcontrol.rs

atsam4lc2b_pac/pdca/
pcontrol.rs
