atsam4lc2a_pac/twim0/
scr.rs

1#[doc = "Register `SCR` writer"]
2pub struct W(crate::W<SCR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<SCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<SCR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<SCR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CCOMP` writer - Command Complete"]
23pub type CCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
24#[doc = "Field `ANAK` writer - NAK in Address Phase Received"]
25pub type ANAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
26#[doc = "Field `DNAK` writer - NAK in Data Phase Received"]
27pub type DNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
28#[doc = "Field `ARBLST` writer - Arbitration Lost"]
29pub type ARBLST_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
30#[doc = "Field `SMBALERT` writer - SMBus Alert"]
31pub type SMBALERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
32#[doc = "Field `TOUT` writer - Timeout"]
33pub type TOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
34#[doc = "Field `PECERR` writer - PEC Error"]
35pub type PECERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
36#[doc = "Field `STOP` writer - Stop Request Accepted"]
37pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
38#[doc = "Field `HSMCACK` writer - ACK in HS-mode Master Code Phase Received"]
39pub type HSMCACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
40impl W {
41    #[doc = "Bit 3 - Command Complete"]
42    #[inline(always)]
43    #[must_use]
44    pub fn ccomp(&mut self) -> CCOMP_W<3> {
45        CCOMP_W::new(self)
46    }
47    #[doc = "Bit 8 - NAK in Address Phase Received"]
48    #[inline(always)]
49    #[must_use]
50    pub fn anak(&mut self) -> ANAK_W<8> {
51        ANAK_W::new(self)
52    }
53    #[doc = "Bit 9 - NAK in Data Phase Received"]
54    #[inline(always)]
55    #[must_use]
56    pub fn dnak(&mut self) -> DNAK_W<9> {
57        DNAK_W::new(self)
58    }
59    #[doc = "Bit 10 - Arbitration Lost"]
60    #[inline(always)]
61    #[must_use]
62    pub fn arblst(&mut self) -> ARBLST_W<10> {
63        ARBLST_W::new(self)
64    }
65    #[doc = "Bit 11 - SMBus Alert"]
66    #[inline(always)]
67    #[must_use]
68    pub fn smbalert(&mut self) -> SMBALERT_W<11> {
69        SMBALERT_W::new(self)
70    }
71    #[doc = "Bit 12 - Timeout"]
72    #[inline(always)]
73    #[must_use]
74    pub fn tout(&mut self) -> TOUT_W<12> {
75        TOUT_W::new(self)
76    }
77    #[doc = "Bit 13 - PEC Error"]
78    #[inline(always)]
79    #[must_use]
80    pub fn pecerr(&mut self) -> PECERR_W<13> {
81        PECERR_W::new(self)
82    }
83    #[doc = "Bit 14 - Stop Request Accepted"]
84    #[inline(always)]
85    #[must_use]
86    pub fn stop(&mut self) -> STOP_W<14> {
87        STOP_W::new(self)
88    }
89    #[doc = "Bit 17 - ACK in HS-mode Master Code Phase Received"]
90    #[inline(always)]
91    #[must_use]
92    pub fn hsmcack(&mut self) -> HSMCACK_W<17> {
93        HSMCACK_W::new(self)
94    }
95    #[doc = "Writes raw bits to the register."]
96    #[inline(always)]
97    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
98        self.0.bits(bits);
99        self
100    }
101}
102#[doc = "Status Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"]
103pub struct SCR_SPEC;
104impl crate::RegisterSpec for SCR_SPEC {
105    type Ux = u32;
106}
107#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"]
108impl crate::Writable for SCR_SPEC {
109    type Writer = W;
110    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
111    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
112}
113#[doc = "`reset()` method sets SCR to value 0"]
114impl crate::Resettable for SCR_SPEC {
115    const RESET_VALUE: Self::Ux = 0;
116}
atsam4lc2a_pac/twim0/scr.rs

atsam4lc2a_pac/twim0/
scr.rs
