atsam4e8e_pac/tc0/
cmr0.rs

1#[doc = "Register `CMR0` reader"]
2pub struct R(crate::R<CMR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CMR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CMR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CMR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CMR0` writer"]
17pub struct W(crate::W<CMR0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CMR0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CMR0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CMR0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TCCLKS` reader - Clock Selection"]
38pub type TCCLKS_R = crate::FieldReader<u8, TCCLKS_A>;
39#[doc = "Clock Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum TCCLKS_A {
43    #[doc = "0: Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)"]
44    TIMER_CLOCK1 = 0,
45    #[doc = "1: Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)"]
46    TIMER_CLOCK2 = 1,
47    #[doc = "2: Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)"]
48    TIMER_CLOCK3 = 2,
49    #[doc = "3: Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)"]
50    TIMER_CLOCK4 = 3,
51    #[doc = "4: Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)"]
52    TIMER_CLOCK5 = 4,
53    #[doc = "5: Clock selected: XC0"]
54    XC0 = 5,
55    #[doc = "6: Clock selected: XC1"]
56    XC1 = 6,
57    #[doc = "7: Clock selected: XC2"]
58    XC2 = 7,
59}
60impl From<TCCLKS_A> for u8 {
61    #[inline(always)]
62    fn from(variant: TCCLKS_A) -> Self {
63        variant as _
64    }
65}
66impl TCCLKS_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> TCCLKS_A {
70        match self.bits {
71            0 => TCCLKS_A::TIMER_CLOCK1,
72            1 => TCCLKS_A::TIMER_CLOCK2,
73            2 => TCCLKS_A::TIMER_CLOCK3,
74            3 => TCCLKS_A::TIMER_CLOCK4,
75            4 => TCCLKS_A::TIMER_CLOCK5,
76            5 => TCCLKS_A::XC0,
77            6 => TCCLKS_A::XC1,
78            7 => TCCLKS_A::XC2,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `TIMER_CLOCK1`"]
83    #[inline(always)]
84    pub fn is_timer_clock1(&self) -> bool {
85        *self == TCCLKS_A::TIMER_CLOCK1
86    }
87    #[doc = "Checks if the value of the field is `TIMER_CLOCK2`"]
88    #[inline(always)]
89    pub fn is_timer_clock2(&self) -> bool {
90        *self == TCCLKS_A::TIMER_CLOCK2
91    }
92    #[doc = "Checks if the value of the field is `TIMER_CLOCK3`"]
93    #[inline(always)]
94    pub fn is_timer_clock3(&self) -> bool {
95        *self == TCCLKS_A::TIMER_CLOCK3
96    }
97    #[doc = "Checks if the value of the field is `TIMER_CLOCK4`"]
98    #[inline(always)]
99    pub fn is_timer_clock4(&self) -> bool {
100        *self == TCCLKS_A::TIMER_CLOCK4
101    }
102    #[doc = "Checks if the value of the field is `TIMER_CLOCK5`"]
103    #[inline(always)]
104    pub fn is_timer_clock5(&self) -> bool {
105        *self == TCCLKS_A::TIMER_CLOCK5
106    }
107    #[doc = "Checks if the value of the field is `XC0`"]
108    #[inline(always)]
109    pub fn is_xc0(&self) -> bool {
110        *self == TCCLKS_A::XC0
111    }
112    #[doc = "Checks if the value of the field is `XC1`"]
113    #[inline(always)]
114    pub fn is_xc1(&self) -> bool {
115        *self == TCCLKS_A::XC1
116    }
117    #[doc = "Checks if the value of the field is `XC2`"]
118    #[inline(always)]
119    pub fn is_xc2(&self) -> bool {
120        *self == TCCLKS_A::XC2
121    }
122}
123#[doc = "Field `TCCLKS` writer - Clock Selection"]
124pub type TCCLKS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CMR0_SPEC, u8, TCCLKS_A, 3, O>;
125impl<'a, const O: u8> TCCLKS_W<'a, O> {
126    #[doc = "Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)"]
127    #[inline(always)]
128    pub fn timer_clock1(self) -> &'a mut W {
129        self.variant(TCCLKS_A::TIMER_CLOCK1)
130    }
131    #[doc = "Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)"]
132    #[inline(always)]
133    pub fn timer_clock2(self) -> &'a mut W {
134        self.variant(TCCLKS_A::TIMER_CLOCK2)
135    }
136    #[doc = "Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)"]
137    #[inline(always)]
138    pub fn timer_clock3(self) -> &'a mut W {
139        self.variant(TCCLKS_A::TIMER_CLOCK3)
140    }
141    #[doc = "Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)"]
142    #[inline(always)]
143    pub fn timer_clock4(self) -> &'a mut W {
144        self.variant(TCCLKS_A::TIMER_CLOCK4)
145    }
146    #[doc = "Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)"]
147    #[inline(always)]
148    pub fn timer_clock5(self) -> &'a mut W {
149        self.variant(TCCLKS_A::TIMER_CLOCK5)
150    }
151    #[doc = "Clock selected: XC0"]
152    #[inline(always)]
153    pub fn xc0(self) -> &'a mut W {
154        self.variant(TCCLKS_A::XC0)
155    }
156    #[doc = "Clock selected: XC1"]
157    #[inline(always)]
158    pub fn xc1(self) -> &'a mut W {
159        self.variant(TCCLKS_A::XC1)
160    }
161    #[doc = "Clock selected: XC2"]
162    #[inline(always)]
163    pub fn xc2(self) -> &'a mut W {
164        self.variant(TCCLKS_A::XC2)
165    }
166}
167#[doc = "Field `CLKI` reader - Clock Invert"]
168pub type CLKI_R = crate::BitReader<bool>;
169#[doc = "Field `CLKI` writer - Clock Invert"]
170pub type CLKI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
171#[doc = "Field `BURST` reader - Burst Signal Selection"]
172pub type BURST_R = crate::FieldReader<u8, BURST_A>;
173#[doc = "Burst Signal Selection\n\nValue on reset: 0"]
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175#[repr(u8)]
176pub enum BURST_A {
177    #[doc = "0: The clock is not gated by an external signal."]
178    NONE = 0,
179    #[doc = "1: XC0 is ANDed with the selected clock."]
180    XC0 = 1,
181    #[doc = "2: XC1 is ANDed with the selected clock."]
182    XC1 = 2,
183    #[doc = "3: XC2 is ANDed with the selected clock."]
184    XC2 = 3,
185}
186impl From<BURST_A> for u8 {
187    #[inline(always)]
188    fn from(variant: BURST_A) -> Self {
189        variant as _
190    }
191}
192impl BURST_R {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub fn variant(&self) -> BURST_A {
196        match self.bits {
197            0 => BURST_A::NONE,
198            1 => BURST_A::XC0,
199            2 => BURST_A::XC1,
200            3 => BURST_A::XC2,
201            _ => unreachable!(),
202        }
203    }
204    #[doc = "Checks if the value of the field is `NONE`"]
205    #[inline(always)]
206    pub fn is_none(&self) -> bool {
207        *self == BURST_A::NONE
208    }
209    #[doc = "Checks if the value of the field is `XC0`"]
210    #[inline(always)]
211    pub fn is_xc0(&self) -> bool {
212        *self == BURST_A::XC0
213    }
214    #[doc = "Checks if the value of the field is `XC1`"]
215    #[inline(always)]
216    pub fn is_xc1(&self) -> bool {
217        *self == BURST_A::XC1
218    }
219    #[doc = "Checks if the value of the field is `XC2`"]
220    #[inline(always)]
221    pub fn is_xc2(&self) -> bool {
222        *self == BURST_A::XC2
223    }
224}
225#[doc = "Field `BURST` writer - Burst Signal Selection"]
226pub type BURST_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CMR0_SPEC, u8, BURST_A, 2, O>;
227impl<'a, const O: u8> BURST_W<'a, O> {
228    #[doc = "The clock is not gated by an external signal."]
229    #[inline(always)]
230    pub fn none(self) -> &'a mut W {
231        self.variant(BURST_A::NONE)
232    }
233    #[doc = "XC0 is ANDed with the selected clock."]
234    #[inline(always)]
235    pub fn xc0(self) -> &'a mut W {
236        self.variant(BURST_A::XC0)
237    }
238    #[doc = "XC1 is ANDed with the selected clock."]
239    #[inline(always)]
240    pub fn xc1(self) -> &'a mut W {
241        self.variant(BURST_A::XC1)
242    }
243    #[doc = "XC2 is ANDed with the selected clock."]
244    #[inline(always)]
245    pub fn xc2(self) -> &'a mut W {
246        self.variant(BURST_A::XC2)
247    }
248}
249#[doc = "Field `LDBSTOP` reader - Counter Clock Stopped with RB Loading"]
250pub type LDBSTOP_R = crate::BitReader<bool>;
251#[doc = "Field `LDBSTOP` writer - Counter Clock Stopped with RB Loading"]
252pub type LDBSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
253#[doc = "Field `LDBDIS` reader - Counter Clock Disable with RB Loading"]
254pub type LDBDIS_R = crate::BitReader<bool>;
255#[doc = "Field `LDBDIS` writer - Counter Clock Disable with RB Loading"]
256pub type LDBDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
257#[doc = "Field `ETRGEDG` reader - External Trigger Edge Selection"]
258pub type ETRGEDG_R = crate::FieldReader<u8, ETRGEDG_A>;
259#[doc = "External Trigger Edge Selection\n\nValue on reset: 0"]
260#[derive(Clone, Copy, Debug, PartialEq, Eq)]
261#[repr(u8)]
262pub enum ETRGEDG_A {
263    #[doc = "0: The clock is not gated by an external signal."]
264    NONE = 0,
265    #[doc = "1: Rising edge"]
266    RISING = 1,
267    #[doc = "2: Falling edge"]
268    FALLING = 2,
269    #[doc = "3: Each edge"]
270    EDGE = 3,
271}
272impl From<ETRGEDG_A> for u8 {
273    #[inline(always)]
274    fn from(variant: ETRGEDG_A) -> Self {
275        variant as _
276    }
277}
278impl ETRGEDG_R {
279    #[doc = "Get enumerated values variant"]
280    #[inline(always)]
281    pub fn variant(&self) -> ETRGEDG_A {
282        match self.bits {
283            0 => ETRGEDG_A::NONE,
284            1 => ETRGEDG_A::RISING,
285            2 => ETRGEDG_A::FALLING,
286            3 => ETRGEDG_A::EDGE,
287            _ => unreachable!(),
288        }
289    }
290    #[doc = "Checks if the value of the field is `NONE`"]
291    #[inline(always)]
292    pub fn is_none(&self) -> bool {
293        *self == ETRGEDG_A::NONE
294    }
295    #[doc = "Checks if the value of the field is `RISING`"]
296    #[inline(always)]
297    pub fn is_rising(&self) -> bool {
298        *self == ETRGEDG_A::RISING
299    }
300    #[doc = "Checks if the value of the field is `FALLING`"]
301    #[inline(always)]
302    pub fn is_falling(&self) -> bool {
303        *self == ETRGEDG_A::FALLING
304    }
305    #[doc = "Checks if the value of the field is `EDGE`"]
306    #[inline(always)]
307    pub fn is_edge(&self) -> bool {
308        *self == ETRGEDG_A::EDGE
309    }
310}
311#[doc = "Field `ETRGEDG` writer - External Trigger Edge Selection"]
312pub type ETRGEDG_W<'a, const O: u8> =
313    crate::FieldWriterSafe<'a, u32, CMR0_SPEC, u8, ETRGEDG_A, 2, O>;
314impl<'a, const O: u8> ETRGEDG_W<'a, O> {
315    #[doc = "The clock is not gated by an external signal."]
316    #[inline(always)]
317    pub fn none(self) -> &'a mut W {
318        self.variant(ETRGEDG_A::NONE)
319    }
320    #[doc = "Rising edge"]
321    #[inline(always)]
322    pub fn rising(self) -> &'a mut W {
323        self.variant(ETRGEDG_A::RISING)
324    }
325    #[doc = "Falling edge"]
326    #[inline(always)]
327    pub fn falling(self) -> &'a mut W {
328        self.variant(ETRGEDG_A::FALLING)
329    }
330    #[doc = "Each edge"]
331    #[inline(always)]
332    pub fn edge(self) -> &'a mut W {
333        self.variant(ETRGEDG_A::EDGE)
334    }
335}
336#[doc = "Field `ABETRG` reader - TIOA or TIOB External Trigger Selection"]
337pub type ABETRG_R = crate::BitReader<bool>;
338#[doc = "Field `ABETRG` writer - TIOA or TIOB External Trigger Selection"]
339pub type ABETRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
340#[doc = "Field `CPCTRG` reader - RC Compare Trigger Enable"]
341pub type CPCTRG_R = crate::BitReader<bool>;
342#[doc = "Field `CPCTRG` writer - RC Compare Trigger Enable"]
343pub type CPCTRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
344#[doc = "Field `WAVE` reader - Waveform Mode"]
345pub type WAVE_R = crate::BitReader<bool>;
346#[doc = "Field `WAVE` writer - Waveform Mode"]
347pub type WAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CMR0_SPEC, bool, O>;
348#[doc = "Field `LDRA` reader - RA Loading Edge Selection"]
349pub type LDRA_R = crate::FieldReader<u8, LDRA_A>;
350#[doc = "RA Loading Edge Selection\n\nValue on reset: 0"]
351#[derive(Clone, Copy, Debug, PartialEq, Eq)]
352#[repr(u8)]
353pub enum LDRA_A {
354    #[doc = "0: None"]
355    NONE = 0,
356    #[doc = "1: Rising edge of TIOA"]
357    RISING = 1,
358    #[doc = "2: Falling edge of TIOA"]
359    FALLING = 2,
360    #[doc = "3: Each edge of TIOA"]
361    EDGE = 3,
362}
363impl From<LDRA_A> for u8 {
364    #[inline(always)]
365    fn from(variant: LDRA_A) -> Self {
366        variant as _
367    }
368}
369impl LDRA_R {
370    #[doc = "Get enumerated values variant"]
371    #[inline(always)]
372    pub fn variant(&self) -> LDRA_A {
373        match self.bits {
374            0 => LDRA_A::NONE,
375            1 => LDRA_A::RISING,
376            2 => LDRA_A::FALLING,
377            3 => LDRA_A::EDGE,
378            _ => unreachable!(),
379        }
380    }
381    #[doc = "Checks if the value of the field is `NONE`"]
382    #[inline(always)]
383    pub fn is_none(&self) -> bool {
384        *self == LDRA_A::NONE
385    }
386    #[doc = "Checks if the value of the field is `RISING`"]
387    #[inline(always)]
388    pub fn is_rising(&self) -> bool {
389        *self == LDRA_A::RISING
390    }
391    #[doc = "Checks if the value of the field is `FALLING`"]
392    #[inline(always)]
393    pub fn is_falling(&self) -> bool {
394        *self == LDRA_A::FALLING
395    }
396    #[doc = "Checks if the value of the field is `EDGE`"]
397    #[inline(always)]
398    pub fn is_edge(&self) -> bool {
399        *self == LDRA_A::EDGE
400    }
401}
402#[doc = "Field `LDRA` writer - RA Loading Edge Selection"]
403pub type LDRA_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CMR0_SPEC, u8, LDRA_A, 2, O>;
404impl<'a, const O: u8> LDRA_W<'a, O> {
405    #[doc = "None"]
406    #[inline(always)]
407    pub fn none(self) -> &'a mut W {
408        self.variant(LDRA_A::NONE)
409    }
410    #[doc = "Rising edge of TIOA"]
411    #[inline(always)]
412    pub fn rising(self) -> &'a mut W {
413        self.variant(LDRA_A::RISING)
414    }
415    #[doc = "Falling edge of TIOA"]
416    #[inline(always)]
417    pub fn falling(self) -> &'a mut W {
418        self.variant(LDRA_A::FALLING)
419    }
420    #[doc = "Each edge of TIOA"]
421    #[inline(always)]
422    pub fn edge(self) -> &'a mut W {
423        self.variant(LDRA_A::EDGE)
424    }
425}
426#[doc = "Field `LDRB` reader - RB Loading Edge Selection"]
427pub type LDRB_R = crate::FieldReader<u8, LDRB_A>;
428#[doc = "RB Loading Edge Selection\n\nValue on reset: 0"]
429#[derive(Clone, Copy, Debug, PartialEq, Eq)]
430#[repr(u8)]
431pub enum LDRB_A {
432    #[doc = "0: None"]
433    NONE = 0,
434    #[doc = "1: Rising edge of TIOA"]
435    RISING = 1,
436    #[doc = "2: Falling edge of TIOA"]
437    FALLING = 2,
438    #[doc = "3: Each edge of TIOA"]
439    EDGE = 3,
440}
441impl From<LDRB_A> for u8 {
442    #[inline(always)]
443    fn from(variant: LDRB_A) -> Self {
444        variant as _
445    }
446}
447impl LDRB_R {
448    #[doc = "Get enumerated values variant"]
449    #[inline(always)]
450    pub fn variant(&self) -> LDRB_A {
451        match self.bits {
452            0 => LDRB_A::NONE,
453            1 => LDRB_A::RISING,
454            2 => LDRB_A::FALLING,
455            3 => LDRB_A::EDGE,
456            _ => unreachable!(),
457        }
458    }
459    #[doc = "Checks if the value of the field is `NONE`"]
460    #[inline(always)]
461    pub fn is_none(&self) -> bool {
462        *self == LDRB_A::NONE
463    }
464    #[doc = "Checks if the value of the field is `RISING`"]
465    #[inline(always)]
466    pub fn is_rising(&self) -> bool {
467        *self == LDRB_A::RISING
468    }
469    #[doc = "Checks if the value of the field is `FALLING`"]
470    #[inline(always)]
471    pub fn is_falling(&self) -> bool {
472        *self == LDRB_A::FALLING
473    }
474    #[doc = "Checks if the value of the field is `EDGE`"]
475    #[inline(always)]
476    pub fn is_edge(&self) -> bool {
477        *self == LDRB_A::EDGE
478    }
479}
480#[doc = "Field `LDRB` writer - RB Loading Edge Selection"]
481pub type LDRB_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CMR0_SPEC, u8, LDRB_A, 2, O>;
482impl<'a, const O: u8> LDRB_W<'a, O> {
483    #[doc = "None"]
484    #[inline(always)]
485    pub fn none(self) -> &'a mut W {
486        self.variant(LDRB_A::NONE)
487    }
488    #[doc = "Rising edge of TIOA"]
489    #[inline(always)]
490    pub fn rising(self) -> &'a mut W {
491        self.variant(LDRB_A::RISING)
492    }
493    #[doc = "Falling edge of TIOA"]
494    #[inline(always)]
495    pub fn falling(self) -> &'a mut W {
496        self.variant(LDRB_A::FALLING)
497    }
498    #[doc = "Each edge of TIOA"]
499    #[inline(always)]
500    pub fn edge(self) -> &'a mut W {
501        self.variant(LDRB_A::EDGE)
502    }
503}
504#[doc = "Field `SBSMPLR` reader - Loading Edge Subsampling Ratio"]
505pub type SBSMPLR_R = crate::FieldReader<u8, SBSMPLR_A>;
506#[doc = "Loading Edge Subsampling Ratio\n\nValue on reset: 0"]
507#[derive(Clone, Copy, Debug, PartialEq, Eq)]
508#[repr(u8)]
509pub enum SBSMPLR_A {
510    #[doc = "0: Load a Capture Register each selected edge"]
511    ONE = 0,
512    #[doc = "1: Load a Capture Register every 2 selected edges"]
513    HALF = 1,
514    #[doc = "2: Load a Capture Register every 4 selected edges"]
515    FOURTH = 2,
516    #[doc = "3: Load a Capture Register every 8 selected edges"]
517    EIGHTH = 3,
518    #[doc = "4: Load a Capture Register every 16 selected edges"]
519    SIXTEENTH = 4,
520}
521impl From<SBSMPLR_A> for u8 {
522    #[inline(always)]
523    fn from(variant: SBSMPLR_A) -> Self {
524        variant as _
525    }
526}
527impl SBSMPLR_R {
528    #[doc = "Get enumerated values variant"]
529    #[inline(always)]
530    pub fn variant(&self) -> Option<SBSMPLR_A> {
531        match self.bits {
532            0 => Some(SBSMPLR_A::ONE),
533            1 => Some(SBSMPLR_A::HALF),
534            2 => Some(SBSMPLR_A::FOURTH),
535            3 => Some(SBSMPLR_A::EIGHTH),
536            4 => Some(SBSMPLR_A::SIXTEENTH),
537            _ => None,
538        }
539    }
540    #[doc = "Checks if the value of the field is `ONE`"]
541    #[inline(always)]
542    pub fn is_one(&self) -> bool {
543        *self == SBSMPLR_A::ONE
544    }
545    #[doc = "Checks if the value of the field is `HALF`"]
546    #[inline(always)]
547    pub fn is_half(&self) -> bool {
548        *self == SBSMPLR_A::HALF
549    }
550    #[doc = "Checks if the value of the field is `FOURTH`"]
551    #[inline(always)]
552    pub fn is_fourth(&self) -> bool {
553        *self == SBSMPLR_A::FOURTH
554    }
555    #[doc = "Checks if the value of the field is `EIGHTH`"]
556    #[inline(always)]
557    pub fn is_eighth(&self) -> bool {
558        *self == SBSMPLR_A::EIGHTH
559    }
560    #[doc = "Checks if the value of the field is `SIXTEENTH`"]
561    #[inline(always)]
562    pub fn is_sixteenth(&self) -> bool {
563        *self == SBSMPLR_A::SIXTEENTH
564    }
565}
566#[doc = "Field `SBSMPLR` writer - Loading Edge Subsampling Ratio"]
567pub type SBSMPLR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMR0_SPEC, u8, SBSMPLR_A, 3, O>;
568impl<'a, const O: u8> SBSMPLR_W<'a, O> {
569    #[doc = "Load a Capture Register each selected edge"]
570    #[inline(always)]
571    pub fn one(self) -> &'a mut W {
572        self.variant(SBSMPLR_A::ONE)
573    }
574    #[doc = "Load a Capture Register every 2 selected edges"]
575    #[inline(always)]
576    pub fn half(self) -> &'a mut W {
577        self.variant(SBSMPLR_A::HALF)
578    }
579    #[doc = "Load a Capture Register every 4 selected edges"]
580    #[inline(always)]
581    pub fn fourth(self) -> &'a mut W {
582        self.variant(SBSMPLR_A::FOURTH)
583    }
584    #[doc = "Load a Capture Register every 8 selected edges"]
585    #[inline(always)]
586    pub fn eighth(self) -> &'a mut W {
587        self.variant(SBSMPLR_A::EIGHTH)
588    }
589    #[doc = "Load a Capture Register every 16 selected edges"]
590    #[inline(always)]
591    pub fn sixteenth(self) -> &'a mut W {
592        self.variant(SBSMPLR_A::SIXTEENTH)
593    }
594}
595impl R {
596    #[doc = "Bits 0:2 - Clock Selection"]
597    #[inline(always)]
598    pub fn tcclks(&self) -> TCCLKS_R {
599        TCCLKS_R::new((self.bits & 7) as u8)
600    }
601    #[doc = "Bit 3 - Clock Invert"]
602    #[inline(always)]
603    pub fn clki(&self) -> CLKI_R {
604        CLKI_R::new(((self.bits >> 3) & 1) != 0)
605    }
606    #[doc = "Bits 4:5 - Burst Signal Selection"]
607    #[inline(always)]
608    pub fn burst(&self) -> BURST_R {
609        BURST_R::new(((self.bits >> 4) & 3) as u8)
610    }
611    #[doc = "Bit 6 - Counter Clock Stopped with RB Loading"]
612    #[inline(always)]
613    pub fn ldbstop(&self) -> LDBSTOP_R {
614        LDBSTOP_R::new(((self.bits >> 6) & 1) != 0)
615    }
616    #[doc = "Bit 7 - Counter Clock Disable with RB Loading"]
617    #[inline(always)]
618    pub fn ldbdis(&self) -> LDBDIS_R {
619        LDBDIS_R::new(((self.bits >> 7) & 1) != 0)
620    }
621    #[doc = "Bits 8:9 - External Trigger Edge Selection"]
622    #[inline(always)]
623    pub fn etrgedg(&self) -> ETRGEDG_R {
624        ETRGEDG_R::new(((self.bits >> 8) & 3) as u8)
625    }
626    #[doc = "Bit 10 - TIOA or TIOB External Trigger Selection"]
627    #[inline(always)]
628    pub fn abetrg(&self) -> ABETRG_R {
629        ABETRG_R::new(((self.bits >> 10) & 1) != 0)
630    }
631    #[doc = "Bit 14 - RC Compare Trigger Enable"]
632    #[inline(always)]
633    pub fn cpctrg(&self) -> CPCTRG_R {
634        CPCTRG_R::new(((self.bits >> 14) & 1) != 0)
635    }
636    #[doc = "Bit 15 - Waveform Mode"]
637    #[inline(always)]
638    pub fn wave(&self) -> WAVE_R {
639        WAVE_R::new(((self.bits >> 15) & 1) != 0)
640    }
641    #[doc = "Bits 16:17 - RA Loading Edge Selection"]
642    #[inline(always)]
643    pub fn ldra(&self) -> LDRA_R {
644        LDRA_R::new(((self.bits >> 16) & 3) as u8)
645    }
646    #[doc = "Bits 18:19 - RB Loading Edge Selection"]
647    #[inline(always)]
648    pub fn ldrb(&self) -> LDRB_R {
649        LDRB_R::new(((self.bits >> 18) & 3) as u8)
650    }
651    #[doc = "Bits 20:22 - Loading Edge Subsampling Ratio"]
652    #[inline(always)]
653    pub fn sbsmplr(&self) -> SBSMPLR_R {
654        SBSMPLR_R::new(((self.bits >> 20) & 7) as u8)
655    }
656}
657impl W {
658    #[doc = "Bits 0:2 - Clock Selection"]
659    #[inline(always)]
660    #[must_use]
661    pub fn tcclks(&mut self) -> TCCLKS_W<0> {
662        TCCLKS_W::new(self)
663    }
664    #[doc = "Bit 3 - Clock Invert"]
665    #[inline(always)]
666    #[must_use]
667    pub fn clki(&mut self) -> CLKI_W<3> {
668        CLKI_W::new(self)
669    }
670    #[doc = "Bits 4:5 - Burst Signal Selection"]
671    #[inline(always)]
672    #[must_use]
673    pub fn burst(&mut self) -> BURST_W<4> {
674        BURST_W::new(self)
675    }
676    #[doc = "Bit 6 - Counter Clock Stopped with RB Loading"]
677    #[inline(always)]
678    #[must_use]
679    pub fn ldbstop(&mut self) -> LDBSTOP_W<6> {
680        LDBSTOP_W::new(self)
681    }
682    #[doc = "Bit 7 - Counter Clock Disable with RB Loading"]
683    #[inline(always)]
684    #[must_use]
685    pub fn ldbdis(&mut self) -> LDBDIS_W<7> {
686        LDBDIS_W::new(self)
687    }
688    #[doc = "Bits 8:9 - External Trigger Edge Selection"]
689    #[inline(always)]
690    #[must_use]
691    pub fn etrgedg(&mut self) -> ETRGEDG_W<8> {
692        ETRGEDG_W::new(self)
693    }
694    #[doc = "Bit 10 - TIOA or TIOB External Trigger Selection"]
695    #[inline(always)]
696    #[must_use]
697    pub fn abetrg(&mut self) -> ABETRG_W<10> {
698        ABETRG_W::new(self)
699    }
700    #[doc = "Bit 14 - RC Compare Trigger Enable"]
701    #[inline(always)]
702    #[must_use]
703    pub fn cpctrg(&mut self) -> CPCTRG_W<14> {
704        CPCTRG_W::new(self)
705    }
706    #[doc = "Bit 15 - Waveform Mode"]
707    #[inline(always)]
708    #[must_use]
709    pub fn wave(&mut self) -> WAVE_W<15> {
710        WAVE_W::new(self)
711    }
712    #[doc = "Bits 16:17 - RA Loading Edge Selection"]
713    #[inline(always)]
714    #[must_use]
715    pub fn ldra(&mut self) -> LDRA_W<16> {
716        LDRA_W::new(self)
717    }
718    #[doc = "Bits 18:19 - RB Loading Edge Selection"]
719    #[inline(always)]
720    #[must_use]
721    pub fn ldrb(&mut self) -> LDRB_W<18> {
722        LDRB_W::new(self)
723    }
724    #[doc = "Bits 20:22 - Loading Edge Subsampling Ratio"]
725    #[inline(always)]
726    #[must_use]
727    pub fn sbsmplr(&mut self) -> SBSMPLR_W<20> {
728        SBSMPLR_W::new(self)
729    }
730    #[doc = "Writes raw bits to the register."]
731    #[inline(always)]
732    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
733        self.0.bits(bits);
734        self
735    }
736}
737#[doc = "Channel Mode Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr0](index.html) module"]
738pub struct CMR0_SPEC;
739impl crate::RegisterSpec for CMR0_SPEC {
740    type Ux = u32;
741}
742#[doc = "`read()` method returns [cmr0::R](R) reader structure"]
743impl crate::Readable for CMR0_SPEC {
744    type Reader = R;
745}
746#[doc = "`write(|w| ..)` method takes [cmr0::W](W) writer structure"]
747impl crate::Writable for CMR0_SPEC {
748    type Writer = W;
749    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
750    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
751}
752#[doc = "`reset()` method sets CMR0 to value 0"]
753impl crate::Resettable for CMR0_SPEC {
754    const RESET_VALUE: Self::Ux = 0;
755}
atsam4e8e_pac/tc0/cmr0.rs

atsam4e8e_pac/tc0/
cmr0.rs
