atsam4e8c_pac/rtc/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ACKDIS` writer - Acknowledge Update Interrupt Disable"]
23pub type ACKDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
24#[doc = "Field `ALRDIS` writer - Alarm Interrupt Disable"]
25pub type ALRDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
26#[doc = "Field `SECDIS` writer - Second Event Interrupt Disable"]
27pub type SECDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
28#[doc = "Field `TIMDIS` writer - Time Event Interrupt Disable"]
29pub type TIMDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
30#[doc = "Field `CALDIS` writer - Calendar Event Interrupt Disable"]
31pub type CALDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
32#[doc = "Field `TDERRDIS` writer - Time and/or Date Error Interrupt Disable"]
33pub type TDERRDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
34impl W {
35    #[doc = "Bit 0 - Acknowledge Update Interrupt Disable"]
36    #[inline(always)]
37    #[must_use]
38    pub fn ackdis(&mut self) -> ACKDIS_W<0> {
39        ACKDIS_W::new(self)
40    }
41    #[doc = "Bit 1 - Alarm Interrupt Disable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn alrdis(&mut self) -> ALRDIS_W<1> {
45        ALRDIS_W::new(self)
46    }
47    #[doc = "Bit 2 - Second Event Interrupt Disable"]
48    #[inline(always)]
49    #[must_use]
50    pub fn secdis(&mut self) -> SECDIS_W<2> {
51        SECDIS_W::new(self)
52    }
53    #[doc = "Bit 3 - Time Event Interrupt Disable"]
54    #[inline(always)]
55    #[must_use]
56    pub fn timdis(&mut self) -> TIMDIS_W<3> {
57        TIMDIS_W::new(self)
58    }
59    #[doc = "Bit 4 - Calendar Event Interrupt Disable"]
60    #[inline(always)]
61    #[must_use]
62    pub fn caldis(&mut self) -> CALDIS_W<4> {
63        CALDIS_W::new(self)
64    }
65    #[doc = "Bit 5 - Time and/or Date Error Interrupt Disable"]
66    #[inline(always)]
67    #[must_use]
68    pub fn tderrdis(&mut self) -> TDERRDIS_W<5> {
69        TDERRDIS_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
79pub struct IDR_SPEC;
80impl crate::RegisterSpec for IDR_SPEC {
81    type Ux = u32;
82}
83#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
84impl crate::Writable for IDR_SPEC {
85    type Writer = W;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
88}
atsam4e8c_pac/rtc/idr.rs

atsam4e8c_pac/rtc/
idr.rs
