Enum atsam4e8c_pac::aes::isr::URAT_A
source · #[repr(u8)]
pub enum URAT_A {
IDR_WR_PROCESSING,
ODR_RD_PROCESSING,
MR_WR_PROCESSING,
ODR_RD_SUBKGEN,
MR_WR_SUBKGEN,
WOR_RD_ACCESS,
}
Expand description
Unspecified Register Access
Value on reset: 0
Variants§
IDR_WR_PROCESSING
0: Input Data Register written during the data processing when SMOD = 0x2 mode.
ODR_RD_PROCESSING
1: Output Data Register read during the data processing.
MR_WR_PROCESSING
2: Mode Register written during the data processing.
ODR_RD_SUBKGEN
3: Output Data Register read during the sub-keys generation.
MR_WR_SUBKGEN
4: Mode Register written during the sub-keys generation.
WOR_RD_ACCESS
5: Write-only register read access.