atsam4e16e_pac/dmac/
cfg3.rs

1#[doc = "Register `CFG3` reader"]
2pub struct R(crate::R<CFG3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG3` writer"]
17pub struct W(crate::W<CFG3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SRC_PER` reader - Source with Peripheral identifier"]
38pub type SRC_PER_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SRC_PER` writer - Source with Peripheral identifier"]
40pub type SRC_PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG3_SPEC, u8, u8, 4, O>;
41#[doc = "Field `DST_PER` reader - Destination with Peripheral identifier"]
42pub type DST_PER_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `DST_PER` writer - Destination with Peripheral identifier"]
44pub type DST_PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG3_SPEC, u8, u8, 4, O>;
45#[doc = "Field `SRC_H2SEL` reader - Software or Hardware Selection for the Source"]
46pub type SRC_H2SEL_R = crate::BitReader<SRC_H2SEL_A>;
47#[doc = "Software or Hardware Selection for the Source\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum SRC_H2SEL_A {
50    #[doc = "0: Software handshaking interface is used to trigger a transfer request."]
51    SW = 0,
52    #[doc = "1: Hardware handshaking interface is used to trigger a transfer request."]
53    HW = 1,
54}
55impl From<SRC_H2SEL_A> for bool {
56    #[inline(always)]
57    fn from(variant: SRC_H2SEL_A) -> Self {
58        variant as u8 != 0
59    }
60}
61impl SRC_H2SEL_R {
62    #[doc = "Get enumerated values variant"]
63    #[inline(always)]
64    pub fn variant(&self) -> SRC_H2SEL_A {
65        match self.bits {
66            false => SRC_H2SEL_A::SW,
67            true => SRC_H2SEL_A::HW,
68        }
69    }
70    #[doc = "Checks if the value of the field is `SW`"]
71    #[inline(always)]
72    pub fn is_sw(&self) -> bool {
73        *self == SRC_H2SEL_A::SW
74    }
75    #[doc = "Checks if the value of the field is `HW`"]
76    #[inline(always)]
77    pub fn is_hw(&self) -> bool {
78        *self == SRC_H2SEL_A::HW
79    }
80}
81#[doc = "Field `SRC_H2SEL` writer - Software or Hardware Selection for the Source"]
82pub type SRC_H2SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, SRC_H2SEL_A, O>;
83impl<'a, const O: u8> SRC_H2SEL_W<'a, O> {
84    #[doc = "Software handshaking interface is used to trigger a transfer request."]
85    #[inline(always)]
86    pub fn sw(self) -> &'a mut W {
87        self.variant(SRC_H2SEL_A::SW)
88    }
89    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
90    #[inline(always)]
91    pub fn hw(self) -> &'a mut W {
92        self.variant(SRC_H2SEL_A::HW)
93    }
94}
95#[doc = "Field `DST_H2SEL` reader - Software or Hardware Selection for the Destination"]
96pub type DST_H2SEL_R = crate::BitReader<DST_H2SEL_A>;
97#[doc = "Software or Hardware Selection for the Destination\n\nValue on reset: 0"]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum DST_H2SEL_A {
100    #[doc = "0: Software handshaking interface is used to trigger a transfer request."]
101    SW = 0,
102    #[doc = "1: Hardware handshaking interface is used to trigger a transfer request."]
103    HW = 1,
104}
105impl From<DST_H2SEL_A> for bool {
106    #[inline(always)]
107    fn from(variant: DST_H2SEL_A) -> Self {
108        variant as u8 != 0
109    }
110}
111impl DST_H2SEL_R {
112    #[doc = "Get enumerated values variant"]
113    #[inline(always)]
114    pub fn variant(&self) -> DST_H2SEL_A {
115        match self.bits {
116            false => DST_H2SEL_A::SW,
117            true => DST_H2SEL_A::HW,
118        }
119    }
120    #[doc = "Checks if the value of the field is `SW`"]
121    #[inline(always)]
122    pub fn is_sw(&self) -> bool {
123        *self == DST_H2SEL_A::SW
124    }
125    #[doc = "Checks if the value of the field is `HW`"]
126    #[inline(always)]
127    pub fn is_hw(&self) -> bool {
128        *self == DST_H2SEL_A::HW
129    }
130}
131#[doc = "Field `DST_H2SEL` writer - Software or Hardware Selection for the Destination"]
132pub type DST_H2SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, DST_H2SEL_A, O>;
133impl<'a, const O: u8> DST_H2SEL_W<'a, O> {
134    #[doc = "Software handshaking interface is used to trigger a transfer request."]
135    #[inline(always)]
136    pub fn sw(self) -> &'a mut W {
137        self.variant(DST_H2SEL_A::SW)
138    }
139    #[doc = "Hardware handshaking interface is used to trigger a transfer request."]
140    #[inline(always)]
141    pub fn hw(self) -> &'a mut W {
142        self.variant(DST_H2SEL_A::HW)
143    }
144}
145#[doc = "Field `SOD` reader - Stop On Done"]
146pub type SOD_R = crate::BitReader<SOD_A>;
147#[doc = "Stop On Done\n\nValue on reset: 0"]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149pub enum SOD_A {
150    #[doc = "0: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register."]
151    DISABLE = 0,
152    #[doc = "1: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1."]
153    ENABLE = 1,
154}
155impl From<SOD_A> for bool {
156    #[inline(always)]
157    fn from(variant: SOD_A) -> Self {
158        variant as u8 != 0
159    }
160}
161impl SOD_R {
162    #[doc = "Get enumerated values variant"]
163    #[inline(always)]
164    pub fn variant(&self) -> SOD_A {
165        match self.bits {
166            false => SOD_A::DISABLE,
167            true => SOD_A::ENABLE,
168        }
169    }
170    #[doc = "Checks if the value of the field is `DISABLE`"]
171    #[inline(always)]
172    pub fn is_disable(&self) -> bool {
173        *self == SOD_A::DISABLE
174    }
175    #[doc = "Checks if the value of the field is `ENABLE`"]
176    #[inline(always)]
177    pub fn is_enable(&self) -> bool {
178        *self == SOD_A::ENABLE
179    }
180}
181#[doc = "Field `SOD` writer - Stop On Done"]
182pub type SOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, SOD_A, O>;
183impl<'a, const O: u8> SOD_W<'a, O> {
184    #[doc = "STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register."]
185    #[inline(always)]
186    pub fn disable(self) -> &'a mut W {
187        self.variant(SOD_A::DISABLE)
188    }
189    #[doc = "STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1."]
190    #[inline(always)]
191    pub fn enable(self) -> &'a mut W {
192        self.variant(SOD_A::ENABLE)
193    }
194}
195#[doc = "Field `LOCK_IF` reader - Interface Lock"]
196pub type LOCK_IF_R = crate::BitReader<LOCK_IF_A>;
197#[doc = "Interface Lock\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum LOCK_IF_A {
200    #[doc = "0: Interface Lock capability is disabled"]
201    DISABLE = 0,
202    #[doc = "1: Interface Lock capability is enabled"]
203    ENABLE = 1,
204}
205impl From<LOCK_IF_A> for bool {
206    #[inline(always)]
207    fn from(variant: LOCK_IF_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl LOCK_IF_R {
212    #[doc = "Get enumerated values variant"]
213    #[inline(always)]
214    pub fn variant(&self) -> LOCK_IF_A {
215        match self.bits {
216            false => LOCK_IF_A::DISABLE,
217            true => LOCK_IF_A::ENABLE,
218        }
219    }
220    #[doc = "Checks if the value of the field is `DISABLE`"]
221    #[inline(always)]
222    pub fn is_disable(&self) -> bool {
223        *self == LOCK_IF_A::DISABLE
224    }
225    #[doc = "Checks if the value of the field is `ENABLE`"]
226    #[inline(always)]
227    pub fn is_enable(&self) -> bool {
228        *self == LOCK_IF_A::ENABLE
229    }
230}
231#[doc = "Field `LOCK_IF` writer - Interface Lock"]
232pub type LOCK_IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, LOCK_IF_A, O>;
233impl<'a, const O: u8> LOCK_IF_W<'a, O> {
234    #[doc = "Interface Lock capability is disabled"]
235    #[inline(always)]
236    pub fn disable(self) -> &'a mut W {
237        self.variant(LOCK_IF_A::DISABLE)
238    }
239    #[doc = "Interface Lock capability is enabled"]
240    #[inline(always)]
241    pub fn enable(self) -> &'a mut W {
242        self.variant(LOCK_IF_A::ENABLE)
243    }
244}
245#[doc = "Field `LOCK_B` reader - Bus Lock"]
246pub type LOCK_B_R = crate::BitReader<LOCK_B_A>;
247#[doc = "Bus Lock\n\nValue on reset: 0"]
248#[derive(Clone, Copy, Debug, PartialEq, Eq)]
249pub enum LOCK_B_A {
250    #[doc = "0: AHB Bus Locking capability is disabled."]
251    DISABLE = 0,
252}
253impl From<LOCK_B_A> for bool {
254    #[inline(always)]
255    fn from(variant: LOCK_B_A) -> Self {
256        variant as u8 != 0
257    }
258}
259impl LOCK_B_R {
260    #[doc = "Get enumerated values variant"]
261    #[inline(always)]
262    pub fn variant(&self) -> Option<LOCK_B_A> {
263        match self.bits {
264            false => Some(LOCK_B_A::DISABLE),
265            _ => None,
266        }
267    }
268    #[doc = "Checks if the value of the field is `DISABLE`"]
269    #[inline(always)]
270    pub fn is_disable(&self) -> bool {
271        *self == LOCK_B_A::DISABLE
272    }
273}
274#[doc = "Field `LOCK_B` writer - Bus Lock"]
275pub type LOCK_B_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, LOCK_B_A, O>;
276impl<'a, const O: u8> LOCK_B_W<'a, O> {
277    #[doc = "AHB Bus Locking capability is disabled."]
278    #[inline(always)]
279    pub fn disable(self) -> &'a mut W {
280        self.variant(LOCK_B_A::DISABLE)
281    }
282}
283#[doc = "Field `LOCK_IF_L` reader - Master Interface Arbiter Lock"]
284pub type LOCK_IF_L_R = crate::BitReader<LOCK_IF_L_A>;
285#[doc = "Master Interface Arbiter Lock\n\nValue on reset: 0"]
286#[derive(Clone, Copy, Debug, PartialEq, Eq)]
287pub enum LOCK_IF_L_A {
288    #[doc = "0: The Master Interface Arbiter is locked by the channel x for a chunk transfer."]
289    CHUNK = 0,
290    #[doc = "1: The Master Interface Arbiter is locked by the channel x for a buffer transfer."]
291    BUFFER = 1,
292}
293impl From<LOCK_IF_L_A> for bool {
294    #[inline(always)]
295    fn from(variant: LOCK_IF_L_A) -> Self {
296        variant as u8 != 0
297    }
298}
299impl LOCK_IF_L_R {
300    #[doc = "Get enumerated values variant"]
301    #[inline(always)]
302    pub fn variant(&self) -> LOCK_IF_L_A {
303        match self.bits {
304            false => LOCK_IF_L_A::CHUNK,
305            true => LOCK_IF_L_A::BUFFER,
306        }
307    }
308    #[doc = "Checks if the value of the field is `CHUNK`"]
309    #[inline(always)]
310    pub fn is_chunk(&self) -> bool {
311        *self == LOCK_IF_L_A::CHUNK
312    }
313    #[doc = "Checks if the value of the field is `BUFFER`"]
314    #[inline(always)]
315    pub fn is_buffer(&self) -> bool {
316        *self == LOCK_IF_L_A::BUFFER
317    }
318}
319#[doc = "Field `LOCK_IF_L` writer - Master Interface Arbiter Lock"]
320pub type LOCK_IF_L_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG3_SPEC, LOCK_IF_L_A, O>;
321impl<'a, const O: u8> LOCK_IF_L_W<'a, O> {
322    #[doc = "The Master Interface Arbiter is locked by the channel x for a chunk transfer."]
323    #[inline(always)]
324    pub fn chunk(self) -> &'a mut W {
325        self.variant(LOCK_IF_L_A::CHUNK)
326    }
327    #[doc = "The Master Interface Arbiter is locked by the channel x for a buffer transfer."]
328    #[inline(always)]
329    pub fn buffer(self) -> &'a mut W {
330        self.variant(LOCK_IF_L_A::BUFFER)
331    }
332}
333#[doc = "Field `AHB_PROT` reader - AHB Protection"]
334pub type AHB_PROT_R = crate::FieldReader<u8, u8>;
335#[doc = "Field `AHB_PROT` writer - AHB Protection"]
336pub type AHB_PROT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG3_SPEC, u8, u8, 3, O>;
337#[doc = "Field `FIFOCFG` reader - FIFO Configuration"]
338pub type FIFOCFG_R = crate::FieldReader<u8, FIFOCFG_A>;
339#[doc = "FIFO Configuration\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341#[repr(u8)]
342pub enum FIFOCFG_A {
343    #[doc = "0: The largest defined length AHB burst is performed on the destination AHB interface."]
344    ALAP_CFG = 0,
345    #[doc = "1: When half FIFO size is available/filled, a source/destination request is serviced."]
346    HALF_CFG = 1,
347    #[doc = "2: When there is enough space/data available to perform a single AHB access, then the request is serviced."]
348    ASAP_CFG = 2,
349}
350impl From<FIFOCFG_A> for u8 {
351    #[inline(always)]
352    fn from(variant: FIFOCFG_A) -> Self {
353        variant as _
354    }
355}
356impl FIFOCFG_R {
357    #[doc = "Get enumerated values variant"]
358    #[inline(always)]
359    pub fn variant(&self) -> Option<FIFOCFG_A> {
360        match self.bits {
361            0 => Some(FIFOCFG_A::ALAP_CFG),
362            1 => Some(FIFOCFG_A::HALF_CFG),
363            2 => Some(FIFOCFG_A::ASAP_CFG),
364            _ => None,
365        }
366    }
367    #[doc = "Checks if the value of the field is `ALAP_CFG`"]
368    #[inline(always)]
369    pub fn is_alap_cfg(&self) -> bool {
370        *self == FIFOCFG_A::ALAP_CFG
371    }
372    #[doc = "Checks if the value of the field is `HALF_CFG`"]
373    #[inline(always)]
374    pub fn is_half_cfg(&self) -> bool {
375        *self == FIFOCFG_A::HALF_CFG
376    }
377    #[doc = "Checks if the value of the field is `ASAP_CFG`"]
378    #[inline(always)]
379    pub fn is_asap_cfg(&self) -> bool {
380        *self == FIFOCFG_A::ASAP_CFG
381    }
382}
383#[doc = "Field `FIFOCFG` writer - FIFO Configuration"]
384pub type FIFOCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG3_SPEC, u8, FIFOCFG_A, 2, O>;
385impl<'a, const O: u8> FIFOCFG_W<'a, O> {
386    #[doc = "The largest defined length AHB burst is performed on the destination AHB interface."]
387    #[inline(always)]
388    pub fn alap_cfg(self) -> &'a mut W {
389        self.variant(FIFOCFG_A::ALAP_CFG)
390    }
391    #[doc = "When half FIFO size is available/filled, a source/destination request is serviced."]
392    #[inline(always)]
393    pub fn half_cfg(self) -> &'a mut W {
394        self.variant(FIFOCFG_A::HALF_CFG)
395    }
396    #[doc = "When there is enough space/data available to perform a single AHB access, then the request is serviced."]
397    #[inline(always)]
398    pub fn asap_cfg(self) -> &'a mut W {
399        self.variant(FIFOCFG_A::ASAP_CFG)
400    }
401}
402impl R {
403    #[doc = "Bits 0:3 - Source with Peripheral identifier"]
404    #[inline(always)]
405    pub fn src_per(&self) -> SRC_PER_R {
406        SRC_PER_R::new((self.bits & 0x0f) as u8)
407    }
408    #[doc = "Bits 4:7 - Destination with Peripheral identifier"]
409    #[inline(always)]
410    pub fn dst_per(&self) -> DST_PER_R {
411        DST_PER_R::new(((self.bits >> 4) & 0x0f) as u8)
412    }
413    #[doc = "Bit 9 - Software or Hardware Selection for the Source"]
414    #[inline(always)]
415    pub fn src_h2sel(&self) -> SRC_H2SEL_R {
416        SRC_H2SEL_R::new(((self.bits >> 9) & 1) != 0)
417    }
418    #[doc = "Bit 13 - Software or Hardware Selection for the Destination"]
419    #[inline(always)]
420    pub fn dst_h2sel(&self) -> DST_H2SEL_R {
421        DST_H2SEL_R::new(((self.bits >> 13) & 1) != 0)
422    }
423    #[doc = "Bit 16 - Stop On Done"]
424    #[inline(always)]
425    pub fn sod(&self) -> SOD_R {
426        SOD_R::new(((self.bits >> 16) & 1) != 0)
427    }
428    #[doc = "Bit 20 - Interface Lock"]
429    #[inline(always)]
430    pub fn lock_if(&self) -> LOCK_IF_R {
431        LOCK_IF_R::new(((self.bits >> 20) & 1) != 0)
432    }
433    #[doc = "Bit 21 - Bus Lock"]
434    #[inline(always)]
435    pub fn lock_b(&self) -> LOCK_B_R {
436        LOCK_B_R::new(((self.bits >> 21) & 1) != 0)
437    }
438    #[doc = "Bit 22 - Master Interface Arbiter Lock"]
439    #[inline(always)]
440    pub fn lock_if_l(&self) -> LOCK_IF_L_R {
441        LOCK_IF_L_R::new(((self.bits >> 22) & 1) != 0)
442    }
443    #[doc = "Bits 24:26 - AHB Protection"]
444    #[inline(always)]
445    pub fn ahb_prot(&self) -> AHB_PROT_R {
446        AHB_PROT_R::new(((self.bits >> 24) & 7) as u8)
447    }
448    #[doc = "Bits 28:29 - FIFO Configuration"]
449    #[inline(always)]
450    pub fn fifocfg(&self) -> FIFOCFG_R {
451        FIFOCFG_R::new(((self.bits >> 28) & 3) as u8)
452    }
453}
454impl W {
455    #[doc = "Bits 0:3 - Source with Peripheral identifier"]
456    #[inline(always)]
457    #[must_use]
458    pub fn src_per(&mut self) -> SRC_PER_W<0> {
459        SRC_PER_W::new(self)
460    }
461    #[doc = "Bits 4:7 - Destination with Peripheral identifier"]
462    #[inline(always)]
463    #[must_use]
464    pub fn dst_per(&mut self) -> DST_PER_W<4> {
465        DST_PER_W::new(self)
466    }
467    #[doc = "Bit 9 - Software or Hardware Selection for the Source"]
468    #[inline(always)]
469    #[must_use]
470    pub fn src_h2sel(&mut self) -> SRC_H2SEL_W<9> {
471        SRC_H2SEL_W::new(self)
472    }
473    #[doc = "Bit 13 - Software or Hardware Selection for the Destination"]
474    #[inline(always)]
475    #[must_use]
476    pub fn dst_h2sel(&mut self) -> DST_H2SEL_W<13> {
477        DST_H2SEL_W::new(self)
478    }
479    #[doc = "Bit 16 - Stop On Done"]
480    #[inline(always)]
481    #[must_use]
482    pub fn sod(&mut self) -> SOD_W<16> {
483        SOD_W::new(self)
484    }
485    #[doc = "Bit 20 - Interface Lock"]
486    #[inline(always)]
487    #[must_use]
488    pub fn lock_if(&mut self) -> LOCK_IF_W<20> {
489        LOCK_IF_W::new(self)
490    }
491    #[doc = "Bit 21 - Bus Lock"]
492    #[inline(always)]
493    #[must_use]
494    pub fn lock_b(&mut self) -> LOCK_B_W<21> {
495        LOCK_B_W::new(self)
496    }
497    #[doc = "Bit 22 - Master Interface Arbiter Lock"]
498    #[inline(always)]
499    #[must_use]
500    pub fn lock_if_l(&mut self) -> LOCK_IF_L_W<22> {
501        LOCK_IF_L_W::new(self)
502    }
503    #[doc = "Bits 24:26 - AHB Protection"]
504    #[inline(always)]
505    #[must_use]
506    pub fn ahb_prot(&mut self) -> AHB_PROT_W<24> {
507        AHB_PROT_W::new(self)
508    }
509    #[doc = "Bits 28:29 - FIFO Configuration"]
510    #[inline(always)]
511    #[must_use]
512    pub fn fifocfg(&mut self) -> FIFOCFG_W<28> {
513        FIFOCFG_W::new(self)
514    }
515    #[doc = "Writes raw bits to the register."]
516    #[inline(always)]
517    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
518        self.0.bits(bits);
519        self
520    }
521}
522#[doc = "DMAC Channel Configuration Register (ch_num = 3)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg3](index.html) module"]
523pub struct CFG3_SPEC;
524impl crate::RegisterSpec for CFG3_SPEC {
525    type Ux = u32;
526}
527#[doc = "`read()` method returns [cfg3::R](R) reader structure"]
528impl crate::Readable for CFG3_SPEC {
529    type Reader = R;
530}
531#[doc = "`write(|w| ..)` method takes [cfg3::W](W) writer structure"]
532impl crate::Writable for CFG3_SPEC {
533    type Writer = W;
534    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
535    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
536}
537#[doc = "`reset()` method sets CFG3 to value 0x0100_0000"]
538impl crate::Resettable for CFG3_SPEC {
539    const RESET_VALUE: Self::Ux = 0x0100_0000;
540}
atsam4e16e_pac/dmac/cfg3.rs

atsam4e16e_pac/dmac/
cfg3.rs
