atsam4e16e_pac/tc1/
imr0.rs

1#[doc = "Register `IMR0` reader"]
2pub struct R(crate::R<IMR0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `COVFS` reader - Counter Overflow"]
17pub type COVFS_R = crate::BitReader<bool>;
18#[doc = "Field `LOVRS` reader - Load Overrun"]
19pub type LOVRS_R = crate::BitReader<bool>;
20#[doc = "Field `CPAS` reader - RA Compare"]
21pub type CPAS_R = crate::BitReader<bool>;
22#[doc = "Field `CPBS` reader - RB Compare"]
23pub type CPBS_R = crate::BitReader<bool>;
24#[doc = "Field `CPCS` reader - RC Compare"]
25pub type CPCS_R = crate::BitReader<bool>;
26#[doc = "Field `LDRAS` reader - RA Loading"]
27pub type LDRAS_R = crate::BitReader<bool>;
28#[doc = "Field `LDRBS` reader - RB Loading"]
29pub type LDRBS_R = crate::BitReader<bool>;
30#[doc = "Field `ETRGS` reader - External Trigger"]
31pub type ETRGS_R = crate::BitReader<bool>;
32#[doc = "Field `ENDRX` reader - End of Receiver Transfer"]
33pub type ENDRX_R = crate::BitReader<bool>;
34#[doc = "Field `RXBUFF` reader - Reception Buffer Full"]
35pub type RXBUFF_R = crate::BitReader<bool>;
36impl R {
37    #[doc = "Bit 0 - Counter Overflow"]
38    #[inline(always)]
39    pub fn covfs(&self) -> COVFS_R {
40        COVFS_R::new((self.bits & 1) != 0)
41    }
42    #[doc = "Bit 1 - Load Overrun"]
43    #[inline(always)]
44    pub fn lovrs(&self) -> LOVRS_R {
45        LOVRS_R::new(((self.bits >> 1) & 1) != 0)
46    }
47    #[doc = "Bit 2 - RA Compare"]
48    #[inline(always)]
49    pub fn cpas(&self) -> CPAS_R {
50        CPAS_R::new(((self.bits >> 2) & 1) != 0)
51    }
52    #[doc = "Bit 3 - RB Compare"]
53    #[inline(always)]
54    pub fn cpbs(&self) -> CPBS_R {
55        CPBS_R::new(((self.bits >> 3) & 1) != 0)
56    }
57    #[doc = "Bit 4 - RC Compare"]
58    #[inline(always)]
59    pub fn cpcs(&self) -> CPCS_R {
60        CPCS_R::new(((self.bits >> 4) & 1) != 0)
61    }
62    #[doc = "Bit 5 - RA Loading"]
63    #[inline(always)]
64    pub fn ldras(&self) -> LDRAS_R {
65        LDRAS_R::new(((self.bits >> 5) & 1) != 0)
66    }
67    #[doc = "Bit 6 - RB Loading"]
68    #[inline(always)]
69    pub fn ldrbs(&self) -> LDRBS_R {
70        LDRBS_R::new(((self.bits >> 6) & 1) != 0)
71    }
72    #[doc = "Bit 7 - External Trigger"]
73    #[inline(always)]
74    pub fn etrgs(&self) -> ETRGS_R {
75        ETRGS_R::new(((self.bits >> 7) & 1) != 0)
76    }
77    #[doc = "Bit 8 - End of Receiver Transfer"]
78    #[inline(always)]
79    pub fn endrx(&self) -> ENDRX_R {
80        ENDRX_R::new(((self.bits >> 8) & 1) != 0)
81    }
82    #[doc = "Bit 9 - Reception Buffer Full"]
83    #[inline(always)]
84    pub fn rxbuff(&self) -> RXBUFF_R {
85        RXBUFF_R::new(((self.bits >> 9) & 1) != 0)
86    }
87}
88#[doc = "Interrupt Mask Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr0](index.html) module"]
89pub struct IMR0_SPEC;
90impl crate::RegisterSpec for IMR0_SPEC {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [imr0::R](R) reader structure"]
94impl crate::Readable for IMR0_SPEC {
95    type Reader = R;
96}
97#[doc = "`reset()` method sets IMR0 to value 0"]
98impl crate::Resettable for IMR0_SPEC {
99    const RESET_VALUE: Self::Ux = 0;
100}
atsam4e16e_pac/tc1/imr0.rs

atsam4e16e_pac/tc1/
imr0.rs
