atsam4e16e_pac/can1/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `MB0` reader - Mailbox 0 Interrupt Mask"]
17pub type MB0_R = crate::BitReader<bool>;
18#[doc = "Field `MB1` reader - Mailbox 1 Interrupt Mask"]
19pub type MB1_R = crate::BitReader<bool>;
20#[doc = "Field `MB2` reader - Mailbox 2 Interrupt Mask"]
21pub type MB2_R = crate::BitReader<bool>;
22#[doc = "Field `MB3` reader - Mailbox 3 Interrupt Mask"]
23pub type MB3_R = crate::BitReader<bool>;
24#[doc = "Field `MB4` reader - Mailbox 4 Interrupt Mask"]
25pub type MB4_R = crate::BitReader<bool>;
26#[doc = "Field `MB5` reader - Mailbox 5 Interrupt Mask"]
27pub type MB5_R = crate::BitReader<bool>;
28#[doc = "Field `MB6` reader - Mailbox 6 Interrupt Mask"]
29pub type MB6_R = crate::BitReader<bool>;
30#[doc = "Field `MB7` reader - Mailbox 7 Interrupt Mask"]
31pub type MB7_R = crate::BitReader<bool>;
32#[doc = "Field `ERRA` reader - Error Active Mode Interrupt Mask"]
33pub type ERRA_R = crate::BitReader<bool>;
34#[doc = "Field `WARN` reader - Warning Limit Interrupt Mask"]
35pub type WARN_R = crate::BitReader<bool>;
36#[doc = "Field `ERRP` reader - Error Passive Mode Interrupt Mask"]
37pub type ERRP_R = crate::BitReader<bool>;
38#[doc = "Field `BOFF` reader - Bus Off Mode Interrupt Mask"]
39pub type BOFF_R = crate::BitReader<bool>;
40#[doc = "Field `SLEEP` reader - Sleep Interrupt Mask"]
41pub type SLEEP_R = crate::BitReader<bool>;
42#[doc = "Field `WAKEUP` reader - Wakeup Interrupt Mask"]
43pub type WAKEUP_R = crate::BitReader<bool>;
44#[doc = "Field `TOVF` reader - Timer Overflow Interrupt Mask"]
45pub type TOVF_R = crate::BitReader<bool>;
46#[doc = "Field `TSTP` reader - Timestamp Interrupt Mask"]
47pub type TSTP_R = crate::BitReader<bool>;
48#[doc = "Field `CERR` reader - CRC Error Interrupt Mask"]
49pub type CERR_R = crate::BitReader<bool>;
50#[doc = "Field `SERR` reader - Stuffing Error Interrupt Mask"]
51pub type SERR_R = crate::BitReader<bool>;
52#[doc = "Field `AERR` reader - Acknowledgment Error Interrupt Mask"]
53pub type AERR_R = crate::BitReader<bool>;
54#[doc = "Field `FERR` reader - Form Error Interrupt Mask"]
55pub type FERR_R = crate::BitReader<bool>;
56#[doc = "Field `BERR` reader - Bit Error Interrupt Mask"]
57pub type BERR_R = crate::BitReader<bool>;
58impl R {
59    #[doc = "Bit 0 - Mailbox 0 Interrupt Mask"]
60    #[inline(always)]
61    pub fn mb0(&self) -> MB0_R {
62        MB0_R::new((self.bits & 1) != 0)
63    }
64    #[doc = "Bit 1 - Mailbox 1 Interrupt Mask"]
65    #[inline(always)]
66    pub fn mb1(&self) -> MB1_R {
67        MB1_R::new(((self.bits >> 1) & 1) != 0)
68    }
69    #[doc = "Bit 2 - Mailbox 2 Interrupt Mask"]
70    #[inline(always)]
71    pub fn mb2(&self) -> MB2_R {
72        MB2_R::new(((self.bits >> 2) & 1) != 0)
73    }
74    #[doc = "Bit 3 - Mailbox 3 Interrupt Mask"]
75    #[inline(always)]
76    pub fn mb3(&self) -> MB3_R {
77        MB3_R::new(((self.bits >> 3) & 1) != 0)
78    }
79    #[doc = "Bit 4 - Mailbox 4 Interrupt Mask"]
80    #[inline(always)]
81    pub fn mb4(&self) -> MB4_R {
82        MB4_R::new(((self.bits >> 4) & 1) != 0)
83    }
84    #[doc = "Bit 5 - Mailbox 5 Interrupt Mask"]
85    #[inline(always)]
86    pub fn mb5(&self) -> MB5_R {
87        MB5_R::new(((self.bits >> 5) & 1) != 0)
88    }
89    #[doc = "Bit 6 - Mailbox 6 Interrupt Mask"]
90    #[inline(always)]
91    pub fn mb6(&self) -> MB6_R {
92        MB6_R::new(((self.bits >> 6) & 1) != 0)
93    }
94    #[doc = "Bit 7 - Mailbox 7 Interrupt Mask"]
95    #[inline(always)]
96    pub fn mb7(&self) -> MB7_R {
97        MB7_R::new(((self.bits >> 7) & 1) != 0)
98    }
99    #[doc = "Bit 16 - Error Active Mode Interrupt Mask"]
100    #[inline(always)]
101    pub fn erra(&self) -> ERRA_R {
102        ERRA_R::new(((self.bits >> 16) & 1) != 0)
103    }
104    #[doc = "Bit 17 - Warning Limit Interrupt Mask"]
105    #[inline(always)]
106    pub fn warn(&self) -> WARN_R {
107        WARN_R::new(((self.bits >> 17) & 1) != 0)
108    }
109    #[doc = "Bit 18 - Error Passive Mode Interrupt Mask"]
110    #[inline(always)]
111    pub fn errp(&self) -> ERRP_R {
112        ERRP_R::new(((self.bits >> 18) & 1) != 0)
113    }
114    #[doc = "Bit 19 - Bus Off Mode Interrupt Mask"]
115    #[inline(always)]
116    pub fn boff(&self) -> BOFF_R {
117        BOFF_R::new(((self.bits >> 19) & 1) != 0)
118    }
119    #[doc = "Bit 20 - Sleep Interrupt Mask"]
120    #[inline(always)]
121    pub fn sleep(&self) -> SLEEP_R {
122        SLEEP_R::new(((self.bits >> 20) & 1) != 0)
123    }
124    #[doc = "Bit 21 - Wakeup Interrupt Mask"]
125    #[inline(always)]
126    pub fn wakeup(&self) -> WAKEUP_R {
127        WAKEUP_R::new(((self.bits >> 21) & 1) != 0)
128    }
129    #[doc = "Bit 22 - Timer Overflow Interrupt Mask"]
130    #[inline(always)]
131    pub fn tovf(&self) -> TOVF_R {
132        TOVF_R::new(((self.bits >> 22) & 1) != 0)
133    }
134    #[doc = "Bit 23 - Timestamp Interrupt Mask"]
135    #[inline(always)]
136    pub fn tstp(&self) -> TSTP_R {
137        TSTP_R::new(((self.bits >> 23) & 1) != 0)
138    }
139    #[doc = "Bit 24 - CRC Error Interrupt Mask"]
140    #[inline(always)]
141    pub fn cerr(&self) -> CERR_R {
142        CERR_R::new(((self.bits >> 24) & 1) != 0)
143    }
144    #[doc = "Bit 25 - Stuffing Error Interrupt Mask"]
145    #[inline(always)]
146    pub fn serr(&self) -> SERR_R {
147        SERR_R::new(((self.bits >> 25) & 1) != 0)
148    }
149    #[doc = "Bit 26 - Acknowledgment Error Interrupt Mask"]
150    #[inline(always)]
151    pub fn aerr(&self) -> AERR_R {
152        AERR_R::new(((self.bits >> 26) & 1) != 0)
153    }
154    #[doc = "Bit 27 - Form Error Interrupt Mask"]
155    #[inline(always)]
156    pub fn ferr(&self) -> FERR_R {
157        FERR_R::new(((self.bits >> 27) & 1) != 0)
158    }
159    #[doc = "Bit 28 - Bit Error Interrupt Mask"]
160    #[inline(always)]
161    pub fn berr(&self) -> BERR_R {
162        BERR_R::new(((self.bits >> 28) & 1) != 0)
163    }
164}
165#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
166pub struct IMR_SPEC;
167impl crate::RegisterSpec for IMR_SPEC {
168    type Ux = u32;
169}
170#[doc = "`read()` method returns [imr::R](R) reader structure"]
171impl crate::Readable for IMR_SPEC {
172    type Reader = R;
173}
174#[doc = "`reset()` method sets IMR to value 0"]
175impl crate::Resettable for IMR_SPEC {
176    const RESET_VALUE: Self::Ux = 0;
177}
atsam4e16e_pac/can1/imr.rs

atsam4e16e_pac/can1/
imr.rs
