1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<IDR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<IDR_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"]
23pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
24#[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"]
25pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
26#[doc = "Field `RXBRK` writer - Receiver Break Interrupt Disable"]
27pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
28#[doc = "Field `ENDRX` writer - End of Receive Transfer Interrupt Disable (available in all USART modes of operation)"]
29pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
30#[doc = "Field `ENDTX` writer - End of Transmit Interrupt Disable (available in all USART modes of operation)"]
31pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
32#[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"]
33pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
34#[doc = "Field `FRAME` writer - Framing Error Interrupt Disable"]
35pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
36#[doc = "Field `PARE` writer - Parity Error Interrupt Disable"]
37pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
38#[doc = "Field `TIMEOUT` writer - Time-out Interrupt Disable"]
39pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
40#[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"]
41pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
42#[doc = "Field `ITER` writer - Max Number of Repetitions Reached Interrupt Disable"]
43pub type ITER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
44#[doc = "Field `TXBUFE` writer - Buffer Empty Interrupt Disable (available in all USART modes of operation)"]
45pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
46#[doc = "Field `RXBUFF` writer - Buffer Full Interrupt Disable (available in all USART modes of operation)"]
47pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
48#[doc = "Field `NACK` writer - Non Acknowledge Interrupt Disable"]
49pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
50#[doc = "Field `RIIC` writer - Ring Indicator Input Change Disable"]
51pub type RIIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
52#[doc = "Field `DSRIC` writer - Data Set Ready Input Change Disable"]
53pub type DSRIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
54#[doc = "Field `DCDIC` writer - Data Carrier Detect Input Change Interrupt Disable"]
55pub type DCDIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
56#[doc = "Field `CTSIC` writer - Clear to Send Input Change Interrupt Disable"]
57pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
58#[doc = "Field `MANE` writer - Manchester Error Interrupt Disable"]
59pub type MANE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
60impl W {
61 #[doc = "Bit 0 - RXRDY Interrupt Disable"]
62 #[inline(always)]
63 #[must_use]
64 pub fn rxrdy(&mut self) -> RXRDY_W<0> {
65 RXRDY_W::new(self)
66 }
67 #[doc = "Bit 1 - TXRDY Interrupt Disable"]
68 #[inline(always)]
69 #[must_use]
70 pub fn txrdy(&mut self) -> TXRDY_W<1> {
71 TXRDY_W::new(self)
72 }
73 #[doc = "Bit 2 - Receiver Break Interrupt Disable"]
74 #[inline(always)]
75 #[must_use]
76 pub fn rxbrk(&mut self) -> RXBRK_W<2> {
77 RXBRK_W::new(self)
78 }
79 #[doc = "Bit 3 - End of Receive Transfer Interrupt Disable (available in all USART modes of operation)"]
80 #[inline(always)]
81 #[must_use]
82 pub fn endrx(&mut self) -> ENDRX_W<3> {
83 ENDRX_W::new(self)
84 }
85 #[doc = "Bit 4 - End of Transmit Interrupt Disable (available in all USART modes of operation)"]
86 #[inline(always)]
87 #[must_use]
88 pub fn endtx(&mut self) -> ENDTX_W<4> {
89 ENDTX_W::new(self)
90 }
91 #[doc = "Bit 5 - Overrun Error Interrupt Enable"]
92 #[inline(always)]
93 #[must_use]
94 pub fn ovre(&mut self) -> OVRE_W<5> {
95 OVRE_W::new(self)
96 }
97 #[doc = "Bit 6 - Framing Error Interrupt Disable"]
98 #[inline(always)]
99 #[must_use]
100 pub fn frame(&mut self) -> FRAME_W<6> {
101 FRAME_W::new(self)
102 }
103 #[doc = "Bit 7 - Parity Error Interrupt Disable"]
104 #[inline(always)]
105 #[must_use]
106 pub fn pare(&mut self) -> PARE_W<7> {
107 PARE_W::new(self)
108 }
109 #[doc = "Bit 8 - Time-out Interrupt Disable"]
110 #[inline(always)]
111 #[must_use]
112 pub fn timeout(&mut self) -> TIMEOUT_W<8> {
113 TIMEOUT_W::new(self)
114 }
115 #[doc = "Bit 9 - TXEMPTY Interrupt Disable"]
116 #[inline(always)]
117 #[must_use]
118 pub fn txempty(&mut self) -> TXEMPTY_W<9> {
119 TXEMPTY_W::new(self)
120 }
121 #[doc = "Bit 10 - Max Number of Repetitions Reached Interrupt Disable"]
122 #[inline(always)]
123 #[must_use]
124 pub fn iter(&mut self) -> ITER_W<10> {
125 ITER_W::new(self)
126 }
127 #[doc = "Bit 11 - Buffer Empty Interrupt Disable (available in all USART modes of operation)"]
128 #[inline(always)]
129 #[must_use]
130 pub fn txbufe(&mut self) -> TXBUFE_W<11> {
131 TXBUFE_W::new(self)
132 }
133 #[doc = "Bit 12 - Buffer Full Interrupt Disable (available in all USART modes of operation)"]
134 #[inline(always)]
135 #[must_use]
136 pub fn rxbuff(&mut self) -> RXBUFF_W<12> {
137 RXBUFF_W::new(self)
138 }
139 #[doc = "Bit 13 - Non Acknowledge Interrupt Disable"]
140 #[inline(always)]
141 #[must_use]
142 pub fn nack(&mut self) -> NACK_W<13> {
143 NACK_W::new(self)
144 }
145 #[doc = "Bit 16 - Ring Indicator Input Change Disable"]
146 #[inline(always)]
147 #[must_use]
148 pub fn riic(&mut self) -> RIIC_W<16> {
149 RIIC_W::new(self)
150 }
151 #[doc = "Bit 17 - Data Set Ready Input Change Disable"]
152 #[inline(always)]
153 #[must_use]
154 pub fn dsric(&mut self) -> DSRIC_W<17> {
155 DSRIC_W::new(self)
156 }
157 #[doc = "Bit 18 - Data Carrier Detect Input Change Interrupt Disable"]
158 #[inline(always)]
159 #[must_use]
160 pub fn dcdic(&mut self) -> DCDIC_W<18> {
161 DCDIC_W::new(self)
162 }
163 #[doc = "Bit 19 - Clear to Send Input Change Interrupt Disable"]
164 #[inline(always)]
165 #[must_use]
166 pub fn ctsic(&mut self) -> CTSIC_W<19> {
167 CTSIC_W::new(self)
168 }
169 #[doc = "Bit 24 - Manchester Error Interrupt Disable"]
170 #[inline(always)]
171 #[must_use]
172 pub fn mane(&mut self) -> MANE_W<24> {
173 MANE_W::new(self)
174 }
175 #[doc = "Writes raw bits to the register."]
176 #[inline(always)]
177 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178 self.0.bits(bits);
179 self
180 }
181}
182#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
183pub struct IDR_SPEC;
184impl crate::RegisterSpec for IDR_SPEC {
185 type Ux = u32;
186}
187#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
188impl crate::Writable for IDR_SPEC {
189 type Writer = W;
190 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
191 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
192}