atsam4e16c_pac/usart0/
csr.rs

1#[doc = "Register `CSR` reader"]
2pub struct R(crate::R<CSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXRDY` reader - Receiver Ready"]
17pub type RXRDY_R = crate::BitReader<bool>;
18#[doc = "Field `TXRDY` reader - Transmitter Ready"]
19pub type TXRDY_R = crate::BitReader<bool>;
20#[doc = "Field `RXBRK` reader - Break Received/End of Break"]
21pub type RXBRK_R = crate::BitReader<bool>;
22#[doc = "Field `ENDRX` reader - End of Receiver Transfer"]
23pub type ENDRX_R = crate::BitReader<bool>;
24#[doc = "Field `ENDTX` reader - End of Transmitter Transfer"]
25pub type ENDTX_R = crate::BitReader<bool>;
26#[doc = "Field `OVRE` reader - Overrun Error"]
27pub type OVRE_R = crate::BitReader<bool>;
28#[doc = "Field `FRAME` reader - Framing Error"]
29pub type FRAME_R = crate::BitReader<bool>;
30#[doc = "Field `PARE` reader - Parity Error"]
31pub type PARE_R = crate::BitReader<bool>;
32#[doc = "Field `TIMEOUT` reader - Receiver Time-out"]
33pub type TIMEOUT_R = crate::BitReader<bool>;
34#[doc = "Field `TXEMPTY` reader - Transmitter Empty"]
35pub type TXEMPTY_R = crate::BitReader<bool>;
36#[doc = "Field `ITER` reader - Max Number of Repetitions Reached"]
37pub type ITER_R = crate::BitReader<bool>;
38#[doc = "Field `TXBUFE` reader - Transmission Buffer Empty"]
39pub type TXBUFE_R = crate::BitReader<bool>;
40#[doc = "Field `RXBUFF` reader - Reception Buffer Full"]
41pub type RXBUFF_R = crate::BitReader<bool>;
42#[doc = "Field `NACK` reader - Non Acknowledge Interrupt"]
43pub type NACK_R = crate::BitReader<bool>;
44#[doc = "Field `RIIC` reader - Ring Indicator Input Change Flag"]
45pub type RIIC_R = crate::BitReader<bool>;
46#[doc = "Field `DSRIC` reader - Data Set Ready Input Change Flag"]
47pub type DSRIC_R = crate::BitReader<bool>;
48#[doc = "Field `DCDIC` reader - Data Carrier Detect Input Change Flag"]
49pub type DCDIC_R = crate::BitReader<bool>;
50#[doc = "Field `CTSIC` reader - Clear to Send Input Change Flag"]
51pub type CTSIC_R = crate::BitReader<bool>;
52#[doc = "Field `RI` reader - Image of RI Input"]
53pub type RI_R = crate::BitReader<bool>;
54#[doc = "Field `DSR` reader - Image of DSR Input"]
55pub type DSR_R = crate::BitReader<bool>;
56#[doc = "Field `DCD` reader - Image of DCD Input"]
57pub type DCD_R = crate::BitReader<bool>;
58#[doc = "Field `CTS` reader - Image of CTS Input"]
59pub type CTS_R = crate::BitReader<bool>;
60#[doc = "Field `MANERR` reader - Manchester Error"]
61pub type MANERR_R = crate::BitReader<bool>;
62impl R {
63    #[doc = "Bit 0 - Receiver Ready"]
64    #[inline(always)]
65    pub fn rxrdy(&self) -> RXRDY_R {
66        RXRDY_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bit 1 - Transmitter Ready"]
69    #[inline(always)]
70    pub fn txrdy(&self) -> TXRDY_R {
71        TXRDY_R::new(((self.bits >> 1) & 1) != 0)
72    }
73    #[doc = "Bit 2 - Break Received/End of Break"]
74    #[inline(always)]
75    pub fn rxbrk(&self) -> RXBRK_R {
76        RXBRK_R::new(((self.bits >> 2) & 1) != 0)
77    }
78    #[doc = "Bit 3 - End of Receiver Transfer"]
79    #[inline(always)]
80    pub fn endrx(&self) -> ENDRX_R {
81        ENDRX_R::new(((self.bits >> 3) & 1) != 0)
82    }
83    #[doc = "Bit 4 - End of Transmitter Transfer"]
84    #[inline(always)]
85    pub fn endtx(&self) -> ENDTX_R {
86        ENDTX_R::new(((self.bits >> 4) & 1) != 0)
87    }
88    #[doc = "Bit 5 - Overrun Error"]
89    #[inline(always)]
90    pub fn ovre(&self) -> OVRE_R {
91        OVRE_R::new(((self.bits >> 5) & 1) != 0)
92    }
93    #[doc = "Bit 6 - Framing Error"]
94    #[inline(always)]
95    pub fn frame(&self) -> FRAME_R {
96        FRAME_R::new(((self.bits >> 6) & 1) != 0)
97    }
98    #[doc = "Bit 7 - Parity Error"]
99    #[inline(always)]
100    pub fn pare(&self) -> PARE_R {
101        PARE_R::new(((self.bits >> 7) & 1) != 0)
102    }
103    #[doc = "Bit 8 - Receiver Time-out"]
104    #[inline(always)]
105    pub fn timeout(&self) -> TIMEOUT_R {
106        TIMEOUT_R::new(((self.bits >> 8) & 1) != 0)
107    }
108    #[doc = "Bit 9 - Transmitter Empty"]
109    #[inline(always)]
110    pub fn txempty(&self) -> TXEMPTY_R {
111        TXEMPTY_R::new(((self.bits >> 9) & 1) != 0)
112    }
113    #[doc = "Bit 10 - Max Number of Repetitions Reached"]
114    #[inline(always)]
115    pub fn iter(&self) -> ITER_R {
116        ITER_R::new(((self.bits >> 10) & 1) != 0)
117    }
118    #[doc = "Bit 11 - Transmission Buffer Empty"]
119    #[inline(always)]
120    pub fn txbufe(&self) -> TXBUFE_R {
121        TXBUFE_R::new(((self.bits >> 11) & 1) != 0)
122    }
123    #[doc = "Bit 12 - Reception Buffer Full"]
124    #[inline(always)]
125    pub fn rxbuff(&self) -> RXBUFF_R {
126        RXBUFF_R::new(((self.bits >> 12) & 1) != 0)
127    }
128    #[doc = "Bit 13 - Non Acknowledge Interrupt"]
129    #[inline(always)]
130    pub fn nack(&self) -> NACK_R {
131        NACK_R::new(((self.bits >> 13) & 1) != 0)
132    }
133    #[doc = "Bit 16 - Ring Indicator Input Change Flag"]
134    #[inline(always)]
135    pub fn riic(&self) -> RIIC_R {
136        RIIC_R::new(((self.bits >> 16) & 1) != 0)
137    }
138    #[doc = "Bit 17 - Data Set Ready Input Change Flag"]
139    #[inline(always)]
140    pub fn dsric(&self) -> DSRIC_R {
141        DSRIC_R::new(((self.bits >> 17) & 1) != 0)
142    }
143    #[doc = "Bit 18 - Data Carrier Detect Input Change Flag"]
144    #[inline(always)]
145    pub fn dcdic(&self) -> DCDIC_R {
146        DCDIC_R::new(((self.bits >> 18) & 1) != 0)
147    }
148    #[doc = "Bit 19 - Clear to Send Input Change Flag"]
149    #[inline(always)]
150    pub fn ctsic(&self) -> CTSIC_R {
151        CTSIC_R::new(((self.bits >> 19) & 1) != 0)
152    }
153    #[doc = "Bit 20 - Image of RI Input"]
154    #[inline(always)]
155    pub fn ri(&self) -> RI_R {
156        RI_R::new(((self.bits >> 20) & 1) != 0)
157    }
158    #[doc = "Bit 21 - Image of DSR Input"]
159    #[inline(always)]
160    pub fn dsr(&self) -> DSR_R {
161        DSR_R::new(((self.bits >> 21) & 1) != 0)
162    }
163    #[doc = "Bit 22 - Image of DCD Input"]
164    #[inline(always)]
165    pub fn dcd(&self) -> DCD_R {
166        DCD_R::new(((self.bits >> 22) & 1) != 0)
167    }
168    #[doc = "Bit 23 - Image of CTS Input"]
169    #[inline(always)]
170    pub fn cts(&self) -> CTS_R {
171        CTS_R::new(((self.bits >> 23) & 1) != 0)
172    }
173    #[doc = "Bit 24 - Manchester Error"]
174    #[inline(always)]
175    pub fn manerr(&self) -> MANERR_R {
176        MANERR_R::new(((self.bits >> 24) & 1) != 0)
177    }
178}
179#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
180pub struct CSR_SPEC;
181impl crate::RegisterSpec for CSR_SPEC {
182    type Ux = u32;
183}
184#[doc = "`read()` method returns [csr::R](R) reader structure"]
185impl crate::Readable for CSR_SPEC {
186    type Reader = R;
187}
atsam4e16c_pac/usart0/csr.rs

atsam4e16c_pac/usart0/
csr.rs
