atsam4e16c_pac/twi0/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `TXCOMP` writer - Transmission Completed Interrupt Disable"]
23pub type TXCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
24#[doc = "Field `RXRDY` writer - Receive Holding Register Ready Interrupt Disable"]
25pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
26#[doc = "Field `TXRDY` writer - Transmit Holding Register Ready Interrupt Disable"]
27pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
28#[doc = "Field `SVACC` writer - Slave Access Interrupt Disable"]
29pub type SVACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
30#[doc = "Field `GACC` writer - General Call Access Interrupt Disable"]
31pub type GACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
32#[doc = "Field `OVRE` writer - Overrun Error Interrupt Disable"]
33pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
34#[doc = "Field `NACK` writer - Not Acknowledge Interrupt Disable"]
35pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
36#[doc = "Field `ARBLST` writer - Arbitration Lost Interrupt Disable"]
37pub type ARBLST_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
38#[doc = "Field `SCL_WS` writer - Clock Wait State Interrupt Disable"]
39pub type SCL_WS_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
40#[doc = "Field `EOSACC` writer - End Of Slave Access Interrupt Disable"]
41pub type EOSACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
42#[doc = "Field `ENDRX` writer - End of Receive Buffer Interrupt Disable"]
43pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
44#[doc = "Field `ENDTX` writer - End of Transmit Buffer Interrupt Disable"]
45pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
46#[doc = "Field `RXBUFF` writer - Receive Buffer Full Interrupt Disable"]
47pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
48#[doc = "Field `TXBUFE` writer - Transmit Buffer Empty Interrupt Disable"]
49pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, bool, O>;
50impl W {
51    #[doc = "Bit 0 - Transmission Completed Interrupt Disable"]
52    #[inline(always)]
53    #[must_use]
54    pub fn txcomp(&mut self) -> TXCOMP_W<0> {
55        TXCOMP_W::new(self)
56    }
57    #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Disable"]
58    #[inline(always)]
59    #[must_use]
60    pub fn rxrdy(&mut self) -> RXRDY_W<1> {
61        RXRDY_W::new(self)
62    }
63    #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Disable"]
64    #[inline(always)]
65    #[must_use]
66    pub fn txrdy(&mut self) -> TXRDY_W<2> {
67        TXRDY_W::new(self)
68    }
69    #[doc = "Bit 4 - Slave Access Interrupt Disable"]
70    #[inline(always)]
71    #[must_use]
72    pub fn svacc(&mut self) -> SVACC_W<4> {
73        SVACC_W::new(self)
74    }
75    #[doc = "Bit 5 - General Call Access Interrupt Disable"]
76    #[inline(always)]
77    #[must_use]
78    pub fn gacc(&mut self) -> GACC_W<5> {
79        GACC_W::new(self)
80    }
81    #[doc = "Bit 6 - Overrun Error Interrupt Disable"]
82    #[inline(always)]
83    #[must_use]
84    pub fn ovre(&mut self) -> OVRE_W<6> {
85        OVRE_W::new(self)
86    }
87    #[doc = "Bit 8 - Not Acknowledge Interrupt Disable"]
88    #[inline(always)]
89    #[must_use]
90    pub fn nack(&mut self) -> NACK_W<8> {
91        NACK_W::new(self)
92    }
93    #[doc = "Bit 9 - Arbitration Lost Interrupt Disable"]
94    #[inline(always)]
95    #[must_use]
96    pub fn arblst(&mut self) -> ARBLST_W<9> {
97        ARBLST_W::new(self)
98    }
99    #[doc = "Bit 10 - Clock Wait State Interrupt Disable"]
100    #[inline(always)]
101    #[must_use]
102    pub fn scl_ws(&mut self) -> SCL_WS_W<10> {
103        SCL_WS_W::new(self)
104    }
105    #[doc = "Bit 11 - End Of Slave Access Interrupt Disable"]
106    #[inline(always)]
107    #[must_use]
108    pub fn eosacc(&mut self) -> EOSACC_W<11> {
109        EOSACC_W::new(self)
110    }
111    #[doc = "Bit 12 - End of Receive Buffer Interrupt Disable"]
112    #[inline(always)]
113    #[must_use]
114    pub fn endrx(&mut self) -> ENDRX_W<12> {
115        ENDRX_W::new(self)
116    }
117    #[doc = "Bit 13 - End of Transmit Buffer Interrupt Disable"]
118    #[inline(always)]
119    #[must_use]
120    pub fn endtx(&mut self) -> ENDTX_W<13> {
121        ENDTX_W::new(self)
122    }
123    #[doc = "Bit 14 - Receive Buffer Full Interrupt Disable"]
124    #[inline(always)]
125    #[must_use]
126    pub fn rxbuff(&mut self) -> RXBUFF_W<14> {
127        RXBUFF_W::new(self)
128    }
129    #[doc = "Bit 15 - Transmit Buffer Empty Interrupt Disable"]
130    #[inline(always)]
131    #[must_use]
132    pub fn txbufe(&mut self) -> TXBUFE_W<15> {
133        TXBUFE_W::new(self)
134    }
135    #[doc = "Writes raw bits to the register."]
136    #[inline(always)]
137    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
138        self.0.bits(bits);
139        self
140    }
141}
142#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
143pub struct IDR_SPEC;
144impl crate::RegisterSpec for IDR_SPEC {
145    type Ux = u32;
146}
147#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
148impl crate::Writable for IDR_SPEC {
149    type Writer = W;
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152}
atsam4e16c_pac/twi0/idr.rs

atsam4e16c_pac/twi0/
idr.rs
