atsam3x4c/usart2/
mr.rs

1#[doc = "Register `MR` reader"]
2pub type R = crate::R<MrSpec>;
3#[doc = "Register `MR` writer"]
4pub type W = crate::W<MrSpec>;
5#[doc = "USART Mode of Operation"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum UsartMode {
9    #[doc = "0: Normal mode"]
10    Normal = 0,
11    #[doc = "1: RS485"]
12    Rs485 = 1,
13    #[doc = "2: Hardware Handshaking"]
14    HwHandshaking = 2,
15    #[doc = "4: IS07816 Protocol: T = 0"]
16    Is07816T0 = 4,
17    #[doc = "6: IS07816 Protocol: T = 1"]
18    Is07816T1 = 6,
19    #[doc = "8: IrDA"]
20    Irda = 8,
21    #[doc = "10: LIN master"]
22    LinMaster = 10,
23    #[doc = "11: LIN Slave"]
24    LinSlave = 11,
25    #[doc = "14: SPI master"]
26    SpiMaster = 14,
27    #[doc = "15: SPI Slave"]
28    SpiSlave = 15,
29}
30impl From<UsartMode> for u8 {
31    #[inline(always)]
32    fn from(variant: UsartMode) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for UsartMode {
37    type Ux = u8;
38}
39impl crate::IsEnum for UsartMode {}
40#[doc = "Field `USART_MODE` reader - USART Mode of Operation"]
41pub type UsartModeR = crate::FieldReader<UsartMode>;
42impl UsartModeR {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub const fn variant(&self) -> Option<UsartMode> {
46        match self.bits {
47            0 => Some(UsartMode::Normal),
48            1 => Some(UsartMode::Rs485),
49            2 => Some(UsartMode::HwHandshaking),
50            4 => Some(UsartMode::Is07816T0),
51            6 => Some(UsartMode::Is07816T1),
52            8 => Some(UsartMode::Irda),
53            10 => Some(UsartMode::LinMaster),
54            11 => Some(UsartMode::LinSlave),
55            14 => Some(UsartMode::SpiMaster),
56            15 => Some(UsartMode::SpiSlave),
57            _ => None,
58        }
59    }
60    #[doc = "Normal mode"]
61    #[inline(always)]
62    pub fn is_normal(&self) -> bool {
63        *self == UsartMode::Normal
64    }
65    #[doc = "RS485"]
66    #[inline(always)]
67    pub fn is_rs485(&self) -> bool {
68        *self == UsartMode::Rs485
69    }
70    #[doc = "Hardware Handshaking"]
71    #[inline(always)]
72    pub fn is_hw_handshaking(&self) -> bool {
73        *self == UsartMode::HwHandshaking
74    }
75    #[doc = "IS07816 Protocol: T = 0"]
76    #[inline(always)]
77    pub fn is_is07816_t_0(&self) -> bool {
78        *self == UsartMode::Is07816T0
79    }
80    #[doc = "IS07816 Protocol: T = 1"]
81    #[inline(always)]
82    pub fn is_is07816_t_1(&self) -> bool {
83        *self == UsartMode::Is07816T1
84    }
85    #[doc = "IrDA"]
86    #[inline(always)]
87    pub fn is_irda(&self) -> bool {
88        *self == UsartMode::Irda
89    }
90    #[doc = "LIN master"]
91    #[inline(always)]
92    pub fn is_lin_master(&self) -> bool {
93        *self == UsartMode::LinMaster
94    }
95    #[doc = "LIN Slave"]
96    #[inline(always)]
97    pub fn is_lin_slave(&self) -> bool {
98        *self == UsartMode::LinSlave
99    }
100    #[doc = "SPI master"]
101    #[inline(always)]
102    pub fn is_spi_master(&self) -> bool {
103        *self == UsartMode::SpiMaster
104    }
105    #[doc = "SPI Slave"]
106    #[inline(always)]
107    pub fn is_spi_slave(&self) -> bool {
108        *self == UsartMode::SpiSlave
109    }
110}
111#[doc = "Field `USART_MODE` writer - USART Mode of Operation"]
112pub type UsartModeW<'a, REG> = crate::FieldWriter<'a, REG, 4, UsartMode>;
113impl<'a, REG> UsartModeW<'a, REG>
114where
115    REG: crate::Writable + crate::RegisterSpec,
116    REG::Ux: From<u8>,
117{
118    #[doc = "Normal mode"]
119    #[inline(always)]
120    pub fn normal(self) -> &'a mut crate::W<REG> {
121        self.variant(UsartMode::Normal)
122    }
123    #[doc = "RS485"]
124    #[inline(always)]
125    pub fn rs485(self) -> &'a mut crate::W<REG> {
126        self.variant(UsartMode::Rs485)
127    }
128    #[doc = "Hardware Handshaking"]
129    #[inline(always)]
130    pub fn hw_handshaking(self) -> &'a mut crate::W<REG> {
131        self.variant(UsartMode::HwHandshaking)
132    }
133    #[doc = "IS07816 Protocol: T = 0"]
134    #[inline(always)]
135    pub fn is07816_t_0(self) -> &'a mut crate::W<REG> {
136        self.variant(UsartMode::Is07816T0)
137    }
138    #[doc = "IS07816 Protocol: T = 1"]
139    #[inline(always)]
140    pub fn is07816_t_1(self) -> &'a mut crate::W<REG> {
141        self.variant(UsartMode::Is07816T1)
142    }
143    #[doc = "IrDA"]
144    #[inline(always)]
145    pub fn irda(self) -> &'a mut crate::W<REG> {
146        self.variant(UsartMode::Irda)
147    }
148    #[doc = "LIN master"]
149    #[inline(always)]
150    pub fn lin_master(self) -> &'a mut crate::W<REG> {
151        self.variant(UsartMode::LinMaster)
152    }
153    #[doc = "LIN Slave"]
154    #[inline(always)]
155    pub fn lin_slave(self) -> &'a mut crate::W<REG> {
156        self.variant(UsartMode::LinSlave)
157    }
158    #[doc = "SPI master"]
159    #[inline(always)]
160    pub fn spi_master(self) -> &'a mut crate::W<REG> {
161        self.variant(UsartMode::SpiMaster)
162    }
163    #[doc = "SPI Slave"]
164    #[inline(always)]
165    pub fn spi_slave(self) -> &'a mut crate::W<REG> {
166        self.variant(UsartMode::SpiSlave)
167    }
168}
169#[doc = "Clock Selection"]
170#[derive(Clone, Copy, Debug, PartialEq, Eq)]
171#[repr(u8)]
172pub enum Usclks {
173    #[doc = "0: master Clock MCK is selected"]
174    Mck = 0,
175    #[doc = "1: Internal Clock Divided MCK/DIV (DIV=8) is selected"]
176    Div = 1,
177    #[doc = "3: Serial Clock SLK is selected"]
178    Sck = 3,
179}
180impl From<Usclks> for u8 {
181    #[inline(always)]
182    fn from(variant: Usclks) -> Self {
183        variant as _
184    }
185}
186impl crate::FieldSpec for Usclks {
187    type Ux = u8;
188}
189impl crate::IsEnum for Usclks {}
190#[doc = "Field `USCLKS` reader - Clock Selection"]
191pub type UsclksR = crate::FieldReader<Usclks>;
192impl UsclksR {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> Option<Usclks> {
196        match self.bits {
197            0 => Some(Usclks::Mck),
198            1 => Some(Usclks::Div),
199            3 => Some(Usclks::Sck),
200            _ => None,
201        }
202    }
203    #[doc = "master Clock MCK is selected"]
204    #[inline(always)]
205    pub fn is_mck(&self) -> bool {
206        *self == Usclks::Mck
207    }
208    #[doc = "Internal Clock Divided MCK/DIV (DIV=8) is selected"]
209    #[inline(always)]
210    pub fn is_div(&self) -> bool {
211        *self == Usclks::Div
212    }
213    #[doc = "Serial Clock SLK is selected"]
214    #[inline(always)]
215    pub fn is_sck(&self) -> bool {
216        *self == Usclks::Sck
217    }
218}
219#[doc = "Field `USCLKS` writer - Clock Selection"]
220pub type UsclksW<'a, REG> = crate::FieldWriter<'a, REG, 2, Usclks>;
221impl<'a, REG> UsclksW<'a, REG>
222where
223    REG: crate::Writable + crate::RegisterSpec,
224    REG::Ux: From<u8>,
225{
226    #[doc = "master Clock MCK is selected"]
227    #[inline(always)]
228    pub fn mck(self) -> &'a mut crate::W<REG> {
229        self.variant(Usclks::Mck)
230    }
231    #[doc = "Internal Clock Divided MCK/DIV (DIV=8) is selected"]
232    #[inline(always)]
233    pub fn div(self) -> &'a mut crate::W<REG> {
234        self.variant(Usclks::Div)
235    }
236    #[doc = "Serial Clock SLK is selected"]
237    #[inline(always)]
238    pub fn sck(self) -> &'a mut crate::W<REG> {
239        self.variant(Usclks::Sck)
240    }
241}
242#[doc = "Character Length"]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244#[repr(u8)]
245pub enum Chrl {
246    #[doc = "0: Character length is 5 bits"]
247    _5Bit = 0,
248    #[doc = "1: Character length is 6 bits"]
249    _6Bit = 1,
250    #[doc = "2: Character length is 7 bits"]
251    _7Bit = 2,
252    #[doc = "3: Character length is 8 bits"]
253    _8Bit = 3,
254}
255impl From<Chrl> for u8 {
256    #[inline(always)]
257    fn from(variant: Chrl) -> Self {
258        variant as _
259    }
260}
261impl crate::FieldSpec for Chrl {
262    type Ux = u8;
263}
264impl crate::IsEnum for Chrl {}
265#[doc = "Field `CHRL` reader - Character Length"]
266pub type ChrlR = crate::FieldReader<Chrl>;
267impl ChrlR {
268    #[doc = "Get enumerated values variant"]
269    #[inline(always)]
270    pub const fn variant(&self) -> Chrl {
271        match self.bits {
272            0 => Chrl::_5Bit,
273            1 => Chrl::_6Bit,
274            2 => Chrl::_7Bit,
275            3 => Chrl::_8Bit,
276            _ => unreachable!(),
277        }
278    }
279    #[doc = "Character length is 5 bits"]
280    #[inline(always)]
281    pub fn is_5_bit(&self) -> bool {
282        *self == Chrl::_5Bit
283    }
284    #[doc = "Character length is 6 bits"]
285    #[inline(always)]
286    pub fn is_6_bit(&self) -> bool {
287        *self == Chrl::_6Bit
288    }
289    #[doc = "Character length is 7 bits"]
290    #[inline(always)]
291    pub fn is_7_bit(&self) -> bool {
292        *self == Chrl::_7Bit
293    }
294    #[doc = "Character length is 8 bits"]
295    #[inline(always)]
296    pub fn is_8_bit(&self) -> bool {
297        *self == Chrl::_8Bit
298    }
299}
300#[doc = "Field `CHRL` writer - Character Length"]
301pub type ChrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Chrl, crate::Safe>;
302impl<'a, REG> ChrlW<'a, REG>
303where
304    REG: crate::Writable + crate::RegisterSpec,
305    REG::Ux: From<u8>,
306{
307    #[doc = "Character length is 5 bits"]
308    #[inline(always)]
309    pub fn _5_bit(self) -> &'a mut crate::W<REG> {
310        self.variant(Chrl::_5Bit)
311    }
312    #[doc = "Character length is 6 bits"]
313    #[inline(always)]
314    pub fn _6_bit(self) -> &'a mut crate::W<REG> {
315        self.variant(Chrl::_6Bit)
316    }
317    #[doc = "Character length is 7 bits"]
318    #[inline(always)]
319    pub fn _7_bit(self) -> &'a mut crate::W<REG> {
320        self.variant(Chrl::_7Bit)
321    }
322    #[doc = "Character length is 8 bits"]
323    #[inline(always)]
324    pub fn _8_bit(self) -> &'a mut crate::W<REG> {
325        self.variant(Chrl::_8Bit)
326    }
327}
328#[doc = "Field `SYNC` reader - Synchronous Mode Select"]
329pub type SyncR = crate::BitReader;
330#[doc = "Field `SYNC` writer - Synchronous Mode Select"]
331pub type SyncW<'a, REG> = crate::BitWriter<'a, REG>;
332#[doc = "Parity Type"]
333#[derive(Clone, Copy, Debug, PartialEq, Eq)]
334#[repr(u8)]
335pub enum Par {
336    #[doc = "0: Even parity"]
337    Even = 0,
338    #[doc = "1: Odd parity"]
339    Odd = 1,
340    #[doc = "2: Parity forced to 0 (Space)"]
341    Space = 2,
342    #[doc = "3: Parity forced to 1 (Mark)"]
343    Mark = 3,
344    #[doc = "4: No parity"]
345    No = 4,
346    #[doc = "6: Multidrop mode"]
347    Multidrop = 6,
348}
349impl From<Par> for u8 {
350    #[inline(always)]
351    fn from(variant: Par) -> Self {
352        variant as _
353    }
354}
355impl crate::FieldSpec for Par {
356    type Ux = u8;
357}
358impl crate::IsEnum for Par {}
359#[doc = "Field `PAR` reader - Parity Type"]
360pub type ParR = crate::FieldReader<Par>;
361impl ParR {
362    #[doc = "Get enumerated values variant"]
363    #[inline(always)]
364    pub const fn variant(&self) -> Option<Par> {
365        match self.bits {
366            0 => Some(Par::Even),
367            1 => Some(Par::Odd),
368            2 => Some(Par::Space),
369            3 => Some(Par::Mark),
370            4 => Some(Par::No),
371            6 => Some(Par::Multidrop),
372            _ => None,
373        }
374    }
375    #[doc = "Even parity"]
376    #[inline(always)]
377    pub fn is_even(&self) -> bool {
378        *self == Par::Even
379    }
380    #[doc = "Odd parity"]
381    #[inline(always)]
382    pub fn is_odd(&self) -> bool {
383        *self == Par::Odd
384    }
385    #[doc = "Parity forced to 0 (Space)"]
386    #[inline(always)]
387    pub fn is_space(&self) -> bool {
388        *self == Par::Space
389    }
390    #[doc = "Parity forced to 1 (Mark)"]
391    #[inline(always)]
392    pub fn is_mark(&self) -> bool {
393        *self == Par::Mark
394    }
395    #[doc = "No parity"]
396    #[inline(always)]
397    pub fn is_no(&self) -> bool {
398        *self == Par::No
399    }
400    #[doc = "Multidrop mode"]
401    #[inline(always)]
402    pub fn is_multidrop(&self) -> bool {
403        *self == Par::Multidrop
404    }
405}
406#[doc = "Field `PAR` writer - Parity Type"]
407pub type ParW<'a, REG> = crate::FieldWriter<'a, REG, 3, Par>;
408impl<'a, REG> ParW<'a, REG>
409where
410    REG: crate::Writable + crate::RegisterSpec,
411    REG::Ux: From<u8>,
412{
413    #[doc = "Even parity"]
414    #[inline(always)]
415    pub fn even(self) -> &'a mut crate::W<REG> {
416        self.variant(Par::Even)
417    }
418    #[doc = "Odd parity"]
419    #[inline(always)]
420    pub fn odd(self) -> &'a mut crate::W<REG> {
421        self.variant(Par::Odd)
422    }
423    #[doc = "Parity forced to 0 (Space)"]
424    #[inline(always)]
425    pub fn space(self) -> &'a mut crate::W<REG> {
426        self.variant(Par::Space)
427    }
428    #[doc = "Parity forced to 1 (Mark)"]
429    #[inline(always)]
430    pub fn mark(self) -> &'a mut crate::W<REG> {
431        self.variant(Par::Mark)
432    }
433    #[doc = "No parity"]
434    #[inline(always)]
435    pub fn no(self) -> &'a mut crate::W<REG> {
436        self.variant(Par::No)
437    }
438    #[doc = "Multidrop mode"]
439    #[inline(always)]
440    pub fn multidrop(self) -> &'a mut crate::W<REG> {
441        self.variant(Par::Multidrop)
442    }
443}
444#[doc = "Number of Stop Bits"]
445#[derive(Clone, Copy, Debug, PartialEq, Eq)]
446#[repr(u8)]
447pub enum Nbstop {
448    #[doc = "0: 1 stop bit"]
449    _1Bit = 0,
450    #[doc = "1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)"]
451    _1_5Bit = 1,
452    #[doc = "2: 2 stop bits"]
453    _2Bit = 2,
454}
455impl From<Nbstop> for u8 {
456    #[inline(always)]
457    fn from(variant: Nbstop) -> Self {
458        variant as _
459    }
460}
461impl crate::FieldSpec for Nbstop {
462    type Ux = u8;
463}
464impl crate::IsEnum for Nbstop {}
465#[doc = "Field `NBSTOP` reader - Number of Stop Bits"]
466pub type NbstopR = crate::FieldReader<Nbstop>;
467impl NbstopR {
468    #[doc = "Get enumerated values variant"]
469    #[inline(always)]
470    pub const fn variant(&self) -> Option<Nbstop> {
471        match self.bits {
472            0 => Some(Nbstop::_1Bit),
473            1 => Some(Nbstop::_1_5Bit),
474            2 => Some(Nbstop::_2Bit),
475            _ => None,
476        }
477    }
478    #[doc = "1 stop bit"]
479    #[inline(always)]
480    pub fn is_1_bit(&self) -> bool {
481        *self == Nbstop::_1Bit
482    }
483    #[doc = "1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)"]
484    #[inline(always)]
485    pub fn is_1_5_bit(&self) -> bool {
486        *self == Nbstop::_1_5Bit
487    }
488    #[doc = "2 stop bits"]
489    #[inline(always)]
490    pub fn is_2_bit(&self) -> bool {
491        *self == Nbstop::_2Bit
492    }
493}
494#[doc = "Field `NBSTOP` writer - Number of Stop Bits"]
495pub type NbstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Nbstop>;
496impl<'a, REG> NbstopW<'a, REG>
497where
498    REG: crate::Writable + crate::RegisterSpec,
499    REG::Ux: From<u8>,
500{
501    #[doc = "1 stop bit"]
502    #[inline(always)]
503    pub fn _1_bit(self) -> &'a mut crate::W<REG> {
504        self.variant(Nbstop::_1Bit)
505    }
506    #[doc = "1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)"]
507    #[inline(always)]
508    pub fn _1_5_bit(self) -> &'a mut crate::W<REG> {
509        self.variant(Nbstop::_1_5Bit)
510    }
511    #[doc = "2 stop bits"]
512    #[inline(always)]
513    pub fn _2_bit(self) -> &'a mut crate::W<REG> {
514        self.variant(Nbstop::_2Bit)
515    }
516}
517#[doc = "Channel Mode"]
518#[derive(Clone, Copy, Debug, PartialEq, Eq)]
519#[repr(u8)]
520pub enum Chmode {
521    #[doc = "0: Normal mode"]
522    Normal = 0,
523    #[doc = "1: Automatic Echo. Receiver input is connected to the TXD pin."]
524    Automatic = 1,
525    #[doc = "2: Local Loopback. Transmitter output is connected to the Receiver Input."]
526    LocalLoopback = 2,
527    #[doc = "3: Remote Loopback. RXD pin is internally connected to the TXD pin."]
528    RemoteLoopback = 3,
529}
530impl From<Chmode> for u8 {
531    #[inline(always)]
532    fn from(variant: Chmode) -> Self {
533        variant as _
534    }
535}
536impl crate::FieldSpec for Chmode {
537    type Ux = u8;
538}
539impl crate::IsEnum for Chmode {}
540#[doc = "Field `CHMODE` reader - Channel Mode"]
541pub type ChmodeR = crate::FieldReader<Chmode>;
542impl ChmodeR {
543    #[doc = "Get enumerated values variant"]
544    #[inline(always)]
545    pub const fn variant(&self) -> Chmode {
546        match self.bits {
547            0 => Chmode::Normal,
548            1 => Chmode::Automatic,
549            2 => Chmode::LocalLoopback,
550            3 => Chmode::RemoteLoopback,
551            _ => unreachable!(),
552        }
553    }
554    #[doc = "Normal mode"]
555    #[inline(always)]
556    pub fn is_normal(&self) -> bool {
557        *self == Chmode::Normal
558    }
559    #[doc = "Automatic Echo. Receiver input is connected to the TXD pin."]
560    #[inline(always)]
561    pub fn is_automatic(&self) -> bool {
562        *self == Chmode::Automatic
563    }
564    #[doc = "Local Loopback. Transmitter output is connected to the Receiver Input."]
565    #[inline(always)]
566    pub fn is_local_loopback(&self) -> bool {
567        *self == Chmode::LocalLoopback
568    }
569    #[doc = "Remote Loopback. RXD pin is internally connected to the TXD pin."]
570    #[inline(always)]
571    pub fn is_remote_loopback(&self) -> bool {
572        *self == Chmode::RemoteLoopback
573    }
574}
575#[doc = "Field `CHMODE` writer - Channel Mode"]
576pub type ChmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Chmode, crate::Safe>;
577impl<'a, REG> ChmodeW<'a, REG>
578where
579    REG: crate::Writable + crate::RegisterSpec,
580    REG::Ux: From<u8>,
581{
582    #[doc = "Normal mode"]
583    #[inline(always)]
584    pub fn normal(self) -> &'a mut crate::W<REG> {
585        self.variant(Chmode::Normal)
586    }
587    #[doc = "Automatic Echo. Receiver input is connected to the TXD pin."]
588    #[inline(always)]
589    pub fn automatic(self) -> &'a mut crate::W<REG> {
590        self.variant(Chmode::Automatic)
591    }
592    #[doc = "Local Loopback. Transmitter output is connected to the Receiver Input."]
593    #[inline(always)]
594    pub fn local_loopback(self) -> &'a mut crate::W<REG> {
595        self.variant(Chmode::LocalLoopback)
596    }
597    #[doc = "Remote Loopback. RXD pin is internally connected to the TXD pin."]
598    #[inline(always)]
599    pub fn remote_loopback(self) -> &'a mut crate::W<REG> {
600        self.variant(Chmode::RemoteLoopback)
601    }
602}
603#[doc = "Field `MSBF` reader - Bit Order"]
604pub type MsbfR = crate::BitReader;
605#[doc = "Field `MSBF` writer - Bit Order"]
606pub type MsbfW<'a, REG> = crate::BitWriter<'a, REG>;
607#[doc = "Field `MODE9` reader - 9-bit Character Length"]
608pub type Mode9R = crate::BitReader;
609#[doc = "Field `MODE9` writer - 9-bit Character Length"]
610pub type Mode9W<'a, REG> = crate::BitWriter<'a, REG>;
611#[doc = "Field `CLKO` reader - Clock Output Select"]
612pub type ClkoR = crate::BitReader;
613#[doc = "Field `CLKO` writer - Clock Output Select"]
614pub type ClkoW<'a, REG> = crate::BitWriter<'a, REG>;
615#[doc = "Field `OVER` reader - Oversampling Mode"]
616pub type OverR = crate::BitReader;
617#[doc = "Field `OVER` writer - Oversampling Mode"]
618pub type OverW<'a, REG> = crate::BitWriter<'a, REG>;
619#[doc = "Field `INACK` reader - Inhibit Non Acknowledge"]
620pub type InackR = crate::BitReader;
621#[doc = "Field `INACK` writer - Inhibit Non Acknowledge"]
622pub type InackW<'a, REG> = crate::BitWriter<'a, REG>;
623#[doc = "Field `DSNACK` reader - Disable Successive NACK"]
624pub type DsnackR = crate::BitReader;
625#[doc = "Field `DSNACK` writer - Disable Successive NACK"]
626pub type DsnackW<'a, REG> = crate::BitWriter<'a, REG>;
627#[doc = "Field `VAR_SYNC` reader - Variable Synchronization of Command/Data Sync Start Frame Delimiter"]
628pub type VarSyncR = crate::BitReader;
629#[doc = "Field `VAR_SYNC` writer - Variable Synchronization of Command/Data Sync Start Frame Delimiter"]
630pub type VarSyncW<'a, REG> = crate::BitWriter<'a, REG>;
631#[doc = "Field `INVDATA` reader - Inverted Data"]
632pub type InvdataR = crate::BitReader;
633#[doc = "Field `INVDATA` writer - Inverted Data"]
634pub type InvdataW<'a, REG> = crate::BitWriter<'a, REG>;
635#[doc = "Field `MAX_ITERATION` reader - Maximum Number of Automatic Iteration"]
636pub type MaxIterationR = crate::FieldReader;
637#[doc = "Field `MAX_ITERATION` writer - Maximum Number of Automatic Iteration"]
638pub type MaxIterationW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
639#[doc = "Field `FILTER` reader - Infrared Receive Line Filter"]
640pub type FilterR = crate::BitReader;
641#[doc = "Field `FILTER` writer - Infrared Receive Line Filter"]
642pub type FilterW<'a, REG> = crate::BitWriter<'a, REG>;
643#[doc = "Field `MAN` reader - Manchester Encoder/Decoder Enable"]
644pub type ManR = crate::BitReader;
645#[doc = "Field `MAN` writer - Manchester Encoder/Decoder Enable"]
646pub type ManW<'a, REG> = crate::BitWriter<'a, REG>;
647#[doc = "Field `MODSYNC` reader - Manchester Synchronization Mode"]
648pub type ModsyncR = crate::BitReader;
649#[doc = "Field `MODSYNC` writer - Manchester Synchronization Mode"]
650pub type ModsyncW<'a, REG> = crate::BitWriter<'a, REG>;
651#[doc = "Field `ONEBIT` reader - Start Frame Delimiter Selector"]
652pub type OnebitR = crate::BitReader;
653#[doc = "Field `ONEBIT` writer - Start Frame Delimiter Selector"]
654pub type OnebitW<'a, REG> = crate::BitWriter<'a, REG>;
655impl R {
656    #[doc = "Bits 0:3 - USART Mode of Operation"]
657    #[inline(always)]
658    pub fn usart_mode(&self) -> UsartModeR {
659        UsartModeR::new((self.bits & 0x0f) as u8)
660    }
661    #[doc = "Bits 4:5 - Clock Selection"]
662    #[inline(always)]
663    pub fn usclks(&self) -> UsclksR {
664        UsclksR::new(((self.bits >> 4) & 3) as u8)
665    }
666    #[doc = "Bits 6:7 - Character Length"]
667    #[inline(always)]
668    pub fn chrl(&self) -> ChrlR {
669        ChrlR::new(((self.bits >> 6) & 3) as u8)
670    }
671    #[doc = "Bit 8 - Synchronous Mode Select"]
672    #[inline(always)]
673    pub fn sync(&self) -> SyncR {
674        SyncR::new(((self.bits >> 8) & 1) != 0)
675    }
676    #[doc = "Bits 9:11 - Parity Type"]
677    #[inline(always)]
678    pub fn par(&self) -> ParR {
679        ParR::new(((self.bits >> 9) & 7) as u8)
680    }
681    #[doc = "Bits 12:13 - Number of Stop Bits"]
682    #[inline(always)]
683    pub fn nbstop(&self) -> NbstopR {
684        NbstopR::new(((self.bits >> 12) & 3) as u8)
685    }
686    #[doc = "Bits 14:15 - Channel Mode"]
687    #[inline(always)]
688    pub fn chmode(&self) -> ChmodeR {
689        ChmodeR::new(((self.bits >> 14) & 3) as u8)
690    }
691    #[doc = "Bit 16 - Bit Order"]
692    #[inline(always)]
693    pub fn msbf(&self) -> MsbfR {
694        MsbfR::new(((self.bits >> 16) & 1) != 0)
695    }
696    #[doc = "Bit 17 - 9-bit Character Length"]
697    #[inline(always)]
698    pub fn mode9(&self) -> Mode9R {
699        Mode9R::new(((self.bits >> 17) & 1) != 0)
700    }
701    #[doc = "Bit 18 - Clock Output Select"]
702    #[inline(always)]
703    pub fn clko(&self) -> ClkoR {
704        ClkoR::new(((self.bits >> 18) & 1) != 0)
705    }
706    #[doc = "Bit 19 - Oversampling Mode"]
707    #[inline(always)]
708    pub fn over(&self) -> OverR {
709        OverR::new(((self.bits >> 19) & 1) != 0)
710    }
711    #[doc = "Bit 20 - Inhibit Non Acknowledge"]
712    #[inline(always)]
713    pub fn inack(&self) -> InackR {
714        InackR::new(((self.bits >> 20) & 1) != 0)
715    }
716    #[doc = "Bit 21 - Disable Successive NACK"]
717    #[inline(always)]
718    pub fn dsnack(&self) -> DsnackR {
719        DsnackR::new(((self.bits >> 21) & 1) != 0)
720    }
721    #[doc = "Bit 22 - Variable Synchronization of Command/Data Sync Start Frame Delimiter"]
722    #[inline(always)]
723    pub fn var_sync(&self) -> VarSyncR {
724        VarSyncR::new(((self.bits >> 22) & 1) != 0)
725    }
726    #[doc = "Bit 23 - Inverted Data"]
727    #[inline(always)]
728    pub fn invdata(&self) -> InvdataR {
729        InvdataR::new(((self.bits >> 23) & 1) != 0)
730    }
731    #[doc = "Bits 24:26 - Maximum Number of Automatic Iteration"]
732    #[inline(always)]
733    pub fn max_iteration(&self) -> MaxIterationR {
734        MaxIterationR::new(((self.bits >> 24) & 7) as u8)
735    }
736    #[doc = "Bit 28 - Infrared Receive Line Filter"]
737    #[inline(always)]
738    pub fn filter(&self) -> FilterR {
739        FilterR::new(((self.bits >> 28) & 1) != 0)
740    }
741    #[doc = "Bit 29 - Manchester Encoder/Decoder Enable"]
742    #[inline(always)]
743    pub fn man(&self) -> ManR {
744        ManR::new(((self.bits >> 29) & 1) != 0)
745    }
746    #[doc = "Bit 30 - Manchester Synchronization Mode"]
747    #[inline(always)]
748    pub fn modsync(&self) -> ModsyncR {
749        ModsyncR::new(((self.bits >> 30) & 1) != 0)
750    }
751    #[doc = "Bit 31 - Start Frame Delimiter Selector"]
752    #[inline(always)]
753    pub fn onebit(&self) -> OnebitR {
754        OnebitR::new(((self.bits >> 31) & 1) != 0)
755    }
756}
757impl W {
758    #[doc = "Bits 0:3 - USART Mode of Operation"]
759    #[inline(always)]
760    #[must_use]
761    pub fn usart_mode(&mut self) -> UsartModeW<MrSpec> {
762        UsartModeW::new(self, 0)
763    }
764    #[doc = "Bits 4:5 - Clock Selection"]
765    #[inline(always)]
766    #[must_use]
767    pub fn usclks(&mut self) -> UsclksW<MrSpec> {
768        UsclksW::new(self, 4)
769    }
770    #[doc = "Bits 6:7 - Character Length"]
771    #[inline(always)]
772    #[must_use]
773    pub fn chrl(&mut self) -> ChrlW<MrSpec> {
774        ChrlW::new(self, 6)
775    }
776    #[doc = "Bit 8 - Synchronous Mode Select"]
777    #[inline(always)]
778    #[must_use]
779    pub fn sync(&mut self) -> SyncW<MrSpec> {
780        SyncW::new(self, 8)
781    }
782    #[doc = "Bits 9:11 - Parity Type"]
783    #[inline(always)]
784    #[must_use]
785    pub fn par(&mut self) -> ParW<MrSpec> {
786        ParW::new(self, 9)
787    }
788    #[doc = "Bits 12:13 - Number of Stop Bits"]
789    #[inline(always)]
790    #[must_use]
791    pub fn nbstop(&mut self) -> NbstopW<MrSpec> {
792        NbstopW::new(self, 12)
793    }
794    #[doc = "Bits 14:15 - Channel Mode"]
795    #[inline(always)]
796    #[must_use]
797    pub fn chmode(&mut self) -> ChmodeW<MrSpec> {
798        ChmodeW::new(self, 14)
799    }
800    #[doc = "Bit 16 - Bit Order"]
801    #[inline(always)]
802    #[must_use]
803    pub fn msbf(&mut self) -> MsbfW<MrSpec> {
804        MsbfW::new(self, 16)
805    }
806    #[doc = "Bit 17 - 9-bit Character Length"]
807    #[inline(always)]
808    #[must_use]
809    pub fn mode9(&mut self) -> Mode9W<MrSpec> {
810        Mode9W::new(self, 17)
811    }
812    #[doc = "Bit 18 - Clock Output Select"]
813    #[inline(always)]
814    #[must_use]
815    pub fn clko(&mut self) -> ClkoW<MrSpec> {
816        ClkoW::new(self, 18)
817    }
818    #[doc = "Bit 19 - Oversampling Mode"]
819    #[inline(always)]
820    #[must_use]
821    pub fn over(&mut self) -> OverW<MrSpec> {
822        OverW::new(self, 19)
823    }
824    #[doc = "Bit 20 - Inhibit Non Acknowledge"]
825    #[inline(always)]
826    #[must_use]
827    pub fn inack(&mut self) -> InackW<MrSpec> {
828        InackW::new(self, 20)
829    }
830    #[doc = "Bit 21 - Disable Successive NACK"]
831    #[inline(always)]
832    #[must_use]
833    pub fn dsnack(&mut self) -> DsnackW<MrSpec> {
834        DsnackW::new(self, 21)
835    }
836    #[doc = "Bit 22 - Variable Synchronization of Command/Data Sync Start Frame Delimiter"]
837    #[inline(always)]
838    #[must_use]
839    pub fn var_sync(&mut self) -> VarSyncW<MrSpec> {
840        VarSyncW::new(self, 22)
841    }
842    #[doc = "Bit 23 - Inverted Data"]
843    #[inline(always)]
844    #[must_use]
845    pub fn invdata(&mut self) -> InvdataW<MrSpec> {
846        InvdataW::new(self, 23)
847    }
848    #[doc = "Bits 24:26 - Maximum Number of Automatic Iteration"]
849    #[inline(always)]
850    #[must_use]
851    pub fn max_iteration(&mut self) -> MaxIterationW<MrSpec> {
852        MaxIterationW::new(self, 24)
853    }
854    #[doc = "Bit 28 - Infrared Receive Line Filter"]
855    #[inline(always)]
856    #[must_use]
857    pub fn filter(&mut self) -> FilterW<MrSpec> {
858        FilterW::new(self, 28)
859    }
860    #[doc = "Bit 29 - Manchester Encoder/Decoder Enable"]
861    #[inline(always)]
862    #[must_use]
863    pub fn man(&mut self) -> ManW<MrSpec> {
864        ManW::new(self, 29)
865    }
866    #[doc = "Bit 30 - Manchester Synchronization Mode"]
867    #[inline(always)]
868    #[must_use]
869    pub fn modsync(&mut self) -> ModsyncW<MrSpec> {
870        ModsyncW::new(self, 30)
871    }
872    #[doc = "Bit 31 - Start Frame Delimiter Selector"]
873    #[inline(always)]
874    #[must_use]
875    pub fn onebit(&mut self) -> OnebitW<MrSpec> {
876        OnebitW::new(self, 31)
877    }
878}
879#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R).  You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
880pub struct MrSpec;
881impl crate::RegisterSpec for MrSpec {
882    type Ux = u32;
883}
884#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
885impl crate::Readable for MrSpec {}
886#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
887impl crate::Writable for MrSpec {
888    type Safety = crate::Unsafe;
889    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
890    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
891}
atsam3x4c/usart2/mr.rs

atsam3x4c/usart2/
mr.rs
