1#[doc = "Register `CTRLA1` reader"]
2pub type R = crate::R<Ctrla1Spec>;
3#[doc = "Register `CTRLA1` writer"]
4pub type W = crate::W<Ctrla1Spec>;
5#[doc = "Field `BTSIZE` reader - Buffer Transfer Size"]
6pub type BtsizeR = crate::FieldReader<u16>;
7#[doc = "Field `BTSIZE` writer - Buffer Transfer Size"]
8pub type BtsizeW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Transfer Width for the Source\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u8)]
12pub enum SrcWidth {
13 #[doc = "0: the transfer size is set to 8-bit width"]
14 Byte = 0,
15 #[doc = "1: the transfer size is set to 16-bit width"]
16 HalfWord = 1,
17 #[doc = "2: the transfer size is set to 32-bit width"]
18 Word = 2,
19}
20impl From<SrcWidth> for u8 {
21 #[inline(always)]
22 fn from(variant: SrcWidth) -> Self {
23 variant as _
24 }
25}
26impl crate::FieldSpec for SrcWidth {
27 type Ux = u8;
28}
29impl crate::IsEnum for SrcWidth {}
30#[doc = "Field `SRC_WIDTH` reader - Transfer Width for the Source"]
31pub type SrcWidthR = crate::FieldReader<SrcWidth>;
32impl SrcWidthR {
33 #[doc = "Get enumerated values variant"]
34 #[inline(always)]
35 pub const fn variant(&self) -> Option<SrcWidth> {
36 match self.bits {
37 0 => Some(SrcWidth::Byte),
38 1 => Some(SrcWidth::HalfWord),
39 2 => Some(SrcWidth::Word),
40 _ => None,
41 }
42 }
43 #[doc = "the transfer size is set to 8-bit width"]
44 #[inline(always)]
45 pub fn is_byte(&self) -> bool {
46 *self == SrcWidth::Byte
47 }
48 #[doc = "the transfer size is set to 16-bit width"]
49 #[inline(always)]
50 pub fn is_half_word(&self) -> bool {
51 *self == SrcWidth::HalfWord
52 }
53 #[doc = "the transfer size is set to 32-bit width"]
54 #[inline(always)]
55 pub fn is_word(&self) -> bool {
56 *self == SrcWidth::Word
57 }
58}
59#[doc = "Field `SRC_WIDTH` writer - Transfer Width for the Source"]
60pub type SrcWidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, SrcWidth>;
61impl<'a, REG> SrcWidthW<'a, REG>
62where
63 REG: crate::Writable + crate::RegisterSpec,
64 REG::Ux: From<u8>,
65{
66 #[doc = "the transfer size is set to 8-bit width"]
67 #[inline(always)]
68 pub fn byte(self) -> &'a mut crate::W<REG> {
69 self.variant(SrcWidth::Byte)
70 }
71 #[doc = "the transfer size is set to 16-bit width"]
72 #[inline(always)]
73 pub fn half_word(self) -> &'a mut crate::W<REG> {
74 self.variant(SrcWidth::HalfWord)
75 }
76 #[doc = "the transfer size is set to 32-bit width"]
77 #[inline(always)]
78 pub fn word(self) -> &'a mut crate::W<REG> {
79 self.variant(SrcWidth::Word)
80 }
81}
82#[doc = "Transfer Width for the Destination\n\nValue on reset: 0"]
83#[derive(Clone, Copy, Debug, PartialEq, Eq)]
84#[repr(u8)]
85pub enum DstWidth {
86 #[doc = "0: the transfer size is set to 8-bit width"]
87 Byte = 0,
88 #[doc = "1: the transfer size is set to 16-bit width"]
89 HalfWord = 1,
90 #[doc = "2: the transfer size is set to 32-bit width"]
91 Word = 2,
92}
93impl From<DstWidth> for u8 {
94 #[inline(always)]
95 fn from(variant: DstWidth) -> Self {
96 variant as _
97 }
98}
99impl crate::FieldSpec for DstWidth {
100 type Ux = u8;
101}
102impl crate::IsEnum for DstWidth {}
103#[doc = "Field `DST_WIDTH` reader - Transfer Width for the Destination"]
104pub type DstWidthR = crate::FieldReader<DstWidth>;
105impl DstWidthR {
106 #[doc = "Get enumerated values variant"]
107 #[inline(always)]
108 pub const fn variant(&self) -> Option<DstWidth> {
109 match self.bits {
110 0 => Some(DstWidth::Byte),
111 1 => Some(DstWidth::HalfWord),
112 2 => Some(DstWidth::Word),
113 _ => None,
114 }
115 }
116 #[doc = "the transfer size is set to 8-bit width"]
117 #[inline(always)]
118 pub fn is_byte(&self) -> bool {
119 *self == DstWidth::Byte
120 }
121 #[doc = "the transfer size is set to 16-bit width"]
122 #[inline(always)]
123 pub fn is_half_word(&self) -> bool {
124 *self == DstWidth::HalfWord
125 }
126 #[doc = "the transfer size is set to 32-bit width"]
127 #[inline(always)]
128 pub fn is_word(&self) -> bool {
129 *self == DstWidth::Word
130 }
131}
132#[doc = "Field `DST_WIDTH` writer - Transfer Width for the Destination"]
133pub type DstWidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, DstWidth>;
134impl<'a, REG> DstWidthW<'a, REG>
135where
136 REG: crate::Writable + crate::RegisterSpec,
137 REG::Ux: From<u8>,
138{
139 #[doc = "the transfer size is set to 8-bit width"]
140 #[inline(always)]
141 pub fn byte(self) -> &'a mut crate::W<REG> {
142 self.variant(DstWidth::Byte)
143 }
144 #[doc = "the transfer size is set to 16-bit width"]
145 #[inline(always)]
146 pub fn half_word(self) -> &'a mut crate::W<REG> {
147 self.variant(DstWidth::HalfWord)
148 }
149 #[doc = "the transfer size is set to 32-bit width"]
150 #[inline(always)]
151 pub fn word(self) -> &'a mut crate::W<REG> {
152 self.variant(DstWidth::Word)
153 }
154}
155#[doc = "Field `DONE` reader - Current Descriptor Stop Command and Transfer Completed Memory Indicator"]
156pub type DoneR = crate::BitReader;
157#[doc = "Field `DONE` writer - Current Descriptor Stop Command and Transfer Completed Memory Indicator"]
158pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
159impl R {
160 #[doc = "Bits 0:15 - Buffer Transfer Size"]
161 #[inline(always)]
162 pub fn btsize(&self) -> BtsizeR {
163 BtsizeR::new((self.bits & 0xffff) as u16)
164 }
165 #[doc = "Bits 24:25 - Transfer Width for the Source"]
166 #[inline(always)]
167 pub fn src_width(&self) -> SrcWidthR {
168 SrcWidthR::new(((self.bits >> 24) & 3) as u8)
169 }
170 #[doc = "Bits 28:29 - Transfer Width for the Destination"]
171 #[inline(always)]
172 pub fn dst_width(&self) -> DstWidthR {
173 DstWidthR::new(((self.bits >> 28) & 3) as u8)
174 }
175 #[doc = "Bit 31 - Current Descriptor Stop Command and Transfer Completed Memory Indicator"]
176 #[inline(always)]
177 pub fn done(&self) -> DoneR {
178 DoneR::new(((self.bits >> 31) & 1) != 0)
179 }
180}
181impl W {
182 #[doc = "Bits 0:15 - Buffer Transfer Size"]
183 #[inline(always)]
184 #[must_use]
185 pub fn btsize(&mut self) -> BtsizeW<Ctrla1Spec> {
186 BtsizeW::new(self, 0)
187 }
188 #[doc = "Bits 24:25 - Transfer Width for the Source"]
189 #[inline(always)]
190 #[must_use]
191 pub fn src_width(&mut self) -> SrcWidthW<Ctrla1Spec> {
192 SrcWidthW::new(self, 24)
193 }
194 #[doc = "Bits 28:29 - Transfer Width for the Destination"]
195 #[inline(always)]
196 #[must_use]
197 pub fn dst_width(&mut self) -> DstWidthW<Ctrla1Spec> {
198 DstWidthW::new(self, 28)
199 }
200 #[doc = "Bit 31 - Current Descriptor Stop Command and Transfer Completed Memory Indicator"]
201 #[inline(always)]
202 #[must_use]
203 pub fn done(&mut self) -> DoneW<Ctrla1Spec> {
204 DoneW::new(self, 31)
205 }
206}
207#[doc = "DMAC Channel Control A Register (ch_num = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrla1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrla1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
208pub struct Ctrla1Spec;
209impl crate::RegisterSpec for Ctrla1Spec {
210 type Ux = u32;
211}
212#[doc = "`read()` method returns [`ctrla1::R`](R) reader structure"]
213impl crate::Readable for Ctrla1Spec {}
214#[doc = "`write(|w| ..)` method takes [`ctrla1::W`](W) writer structure"]
215impl crate::Writable for Ctrla1Spec {
216 type Safety = crate::Unsafe;
217 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
218 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
219}
220#[doc = "`reset()` method sets CTRLA1 to value 0"]
221impl crate::Resettable for Ctrla1Spec {
222 const RESET_VALUE: u32 = 0;
223}