atsam3s8c/udp/
csr7.rs

1#[doc = "Register `CSR7` reader"]
2pub type R = crate::R<Csr7Spec>;
3#[doc = "Register `CSR7` writer"]
4pub type W = crate::W<Csr7Spec>;
5#[doc = "Field `TXCOMP` reader - Generates an IN Packet with Data Previously Written in the DPR"]
6pub type TxcompR = crate::BitReader;
7#[doc = "Field `TXCOMP` writer - Generates an IN Packet with Data Previously Written in the DPR"]
8pub type TxcompW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_DATA_BK0` reader - Receive Data Bank 0"]
10pub type RxDataBk0R = crate::BitReader;
11#[doc = "Field `RX_DATA_BK0` writer - Receive Data Bank 0"]
12pub type RxDataBk0W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXSETUP` reader - Received Setup"]
14pub type RxsetupR = crate::BitReader;
15#[doc = "Field `RXSETUP` writer - Received Setup"]
16pub type RxsetupW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `STALLSENT` reader - Stall Sent"]
18pub type StallsentR = crate::BitReader;
19#[doc = "Field `STALLSENT` writer - Stall Sent"]
20pub type StallsentW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TXPKTRDY` reader - Transmit Packet Ready"]
22pub type TxpktrdyR = crate::BitReader;
23#[doc = "Field `TXPKTRDY` writer - Transmit Packet Ready"]
24pub type TxpktrdyW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FORCESTALL` reader - Force Stall (used by Control, Bulk and Isochronous Endpoints)"]
26pub type ForcestallR = crate::BitReader;
27#[doc = "Field `FORCESTALL` writer - Force Stall (used by Control, Bulk and Isochronous Endpoints)"]
28pub type ForcestallW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_DATA_BK1` reader - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)"]
30pub type RxDataBk1R = crate::BitReader;
31#[doc = "Field `RX_DATA_BK1` writer - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)"]
32pub type RxDataBk1W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DIR` reader - Transfer Direction (only available for control endpoints)"]
34pub type DirR = crate::BitReader;
35#[doc = "Field `DIR` writer - Transfer Direction (only available for control endpoints)"]
36pub type DirW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Endpoint Type"]
38#[derive(Clone, Copy, Debug, PartialEq, Eq)]
39#[repr(u8)]
40pub enum Eptype {
41    #[doc = "0: Control"]
42    Ctrl = 0,
43    #[doc = "1: Isochronous OUT"]
44    IsoOut = 1,
45    #[doc = "2: Bulk OUT"]
46    BulkOut = 2,
47    #[doc = "3: Interrupt OUT"]
48    IntOut = 3,
49    #[doc = "5: Isochronous IN"]
50    IsoIn = 5,
51    #[doc = "6: Bulk IN"]
52    BulkIn = 6,
53    #[doc = "7: Interrupt IN"]
54    IntIn = 7,
55}
56impl From<Eptype> for u8 {
57    #[inline(always)]
58    fn from(variant: Eptype) -> Self {
59        variant as _
60    }
61}
62impl crate::FieldSpec for Eptype {
63    type Ux = u8;
64}
65impl crate::IsEnum for Eptype {}
66#[doc = "Field `EPTYPE` reader - Endpoint Type"]
67pub type EptypeR = crate::FieldReader<Eptype>;
68impl EptypeR {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub const fn variant(&self) -> Option<Eptype> {
72        match self.bits {
73            0 => Some(Eptype::Ctrl),
74            1 => Some(Eptype::IsoOut),
75            2 => Some(Eptype::BulkOut),
76            3 => Some(Eptype::IntOut),
77            5 => Some(Eptype::IsoIn),
78            6 => Some(Eptype::BulkIn),
79            7 => Some(Eptype::IntIn),
80            _ => None,
81        }
82    }
83    #[doc = "Control"]
84    #[inline(always)]
85    pub fn is_ctrl(&self) -> bool {
86        *self == Eptype::Ctrl
87    }
88    #[doc = "Isochronous OUT"]
89    #[inline(always)]
90    pub fn is_iso_out(&self) -> bool {
91        *self == Eptype::IsoOut
92    }
93    #[doc = "Bulk OUT"]
94    #[inline(always)]
95    pub fn is_bulk_out(&self) -> bool {
96        *self == Eptype::BulkOut
97    }
98    #[doc = "Interrupt OUT"]
99    #[inline(always)]
100    pub fn is_int_out(&self) -> bool {
101        *self == Eptype::IntOut
102    }
103    #[doc = "Isochronous IN"]
104    #[inline(always)]
105    pub fn is_iso_in(&self) -> bool {
106        *self == Eptype::IsoIn
107    }
108    #[doc = "Bulk IN"]
109    #[inline(always)]
110    pub fn is_bulk_in(&self) -> bool {
111        *self == Eptype::BulkIn
112    }
113    #[doc = "Interrupt IN"]
114    #[inline(always)]
115    pub fn is_int_in(&self) -> bool {
116        *self == Eptype::IntIn
117    }
118}
119#[doc = "Field `EPTYPE` writer - Endpoint Type"]
120pub type EptypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Eptype>;
121impl<'a, REG> EptypeW<'a, REG>
122where
123    REG: crate::Writable + crate::RegisterSpec,
124    REG::Ux: From<u8>,
125{
126    #[doc = "Control"]
127    #[inline(always)]
128    pub fn ctrl(self) -> &'a mut crate::W<REG> {
129        self.variant(Eptype::Ctrl)
130    }
131    #[doc = "Isochronous OUT"]
132    #[inline(always)]
133    pub fn iso_out(self) -> &'a mut crate::W<REG> {
134        self.variant(Eptype::IsoOut)
135    }
136    #[doc = "Bulk OUT"]
137    #[inline(always)]
138    pub fn bulk_out(self) -> &'a mut crate::W<REG> {
139        self.variant(Eptype::BulkOut)
140    }
141    #[doc = "Interrupt OUT"]
142    #[inline(always)]
143    pub fn int_out(self) -> &'a mut crate::W<REG> {
144        self.variant(Eptype::IntOut)
145    }
146    #[doc = "Isochronous IN"]
147    #[inline(always)]
148    pub fn iso_in(self) -> &'a mut crate::W<REG> {
149        self.variant(Eptype::IsoIn)
150    }
151    #[doc = "Bulk IN"]
152    #[inline(always)]
153    pub fn bulk_in(self) -> &'a mut crate::W<REG> {
154        self.variant(Eptype::BulkIn)
155    }
156    #[doc = "Interrupt IN"]
157    #[inline(always)]
158    pub fn int_in(self) -> &'a mut crate::W<REG> {
159        self.variant(Eptype::IntIn)
160    }
161}
162#[doc = "Field `DTGLE` reader - Data Toggle"]
163pub type DtgleR = crate::BitReader;
164#[doc = "Field `DTGLE` writer - Data Toggle"]
165pub type DtgleW<'a, REG> = crate::BitWriter<'a, REG>;
166#[doc = "Field `EPEDS` reader - Endpoint Enable Disable"]
167pub type EpedsR = crate::BitReader;
168#[doc = "Field `EPEDS` writer - Endpoint Enable Disable"]
169pub type EpedsW<'a, REG> = crate::BitWriter<'a, REG>;
170#[doc = "Field `RXBYTECNT` reader - Number of Bytes Available in the FIFO"]
171pub type RxbytecntR = crate::FieldReader<u16>;
172#[doc = "Field `RXBYTECNT` writer - Number of Bytes Available in the FIFO"]
173pub type RxbytecntW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
174impl R {
175    #[doc = "Bit 0 - Generates an IN Packet with Data Previously Written in the DPR"]
176    #[inline(always)]
177    pub fn txcomp(&self) -> TxcompR {
178        TxcompR::new((self.bits & 1) != 0)
179    }
180    #[doc = "Bit 1 - Receive Data Bank 0"]
181    #[inline(always)]
182    pub fn rx_data_bk0(&self) -> RxDataBk0R {
183        RxDataBk0R::new(((self.bits >> 1) & 1) != 0)
184    }
185    #[doc = "Bit 2 - Received Setup"]
186    #[inline(always)]
187    pub fn rxsetup(&self) -> RxsetupR {
188        RxsetupR::new(((self.bits >> 2) & 1) != 0)
189    }
190    #[doc = "Bit 3 - Stall Sent"]
191    #[inline(always)]
192    pub fn stallsent(&self) -> StallsentR {
193        StallsentR::new(((self.bits >> 3) & 1) != 0)
194    }
195    #[doc = "Bit 4 - Transmit Packet Ready"]
196    #[inline(always)]
197    pub fn txpktrdy(&self) -> TxpktrdyR {
198        TxpktrdyR::new(((self.bits >> 4) & 1) != 0)
199    }
200    #[doc = "Bit 5 - Force Stall (used by Control, Bulk and Isochronous Endpoints)"]
201    #[inline(always)]
202    pub fn forcestall(&self) -> ForcestallR {
203        ForcestallR::new(((self.bits >> 5) & 1) != 0)
204    }
205    #[doc = "Bit 6 - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)"]
206    #[inline(always)]
207    pub fn rx_data_bk1(&self) -> RxDataBk1R {
208        RxDataBk1R::new(((self.bits >> 6) & 1) != 0)
209    }
210    #[doc = "Bit 7 - Transfer Direction (only available for control endpoints)"]
211    #[inline(always)]
212    pub fn dir(&self) -> DirR {
213        DirR::new(((self.bits >> 7) & 1) != 0)
214    }
215    #[doc = "Bits 8:10 - Endpoint Type"]
216    #[inline(always)]
217    pub fn eptype(&self) -> EptypeR {
218        EptypeR::new(((self.bits >> 8) & 7) as u8)
219    }
220    #[doc = "Bit 11 - Data Toggle"]
221    #[inline(always)]
222    pub fn dtgle(&self) -> DtgleR {
223        DtgleR::new(((self.bits >> 11) & 1) != 0)
224    }
225    #[doc = "Bit 15 - Endpoint Enable Disable"]
226    #[inline(always)]
227    pub fn epeds(&self) -> EpedsR {
228        EpedsR::new(((self.bits >> 15) & 1) != 0)
229    }
230    #[doc = "Bits 16:26 - Number of Bytes Available in the FIFO"]
231    #[inline(always)]
232    pub fn rxbytecnt(&self) -> RxbytecntR {
233        RxbytecntR::new(((self.bits >> 16) & 0x07ff) as u16)
234    }
235}
236impl W {
237    #[doc = "Bit 0 - Generates an IN Packet with Data Previously Written in the DPR"]
238    #[inline(always)]
239    #[must_use]
240    pub fn txcomp(&mut self) -> TxcompW<Csr7Spec> {
241        TxcompW::new(self, 0)
242    }
243    #[doc = "Bit 1 - Receive Data Bank 0"]
244    #[inline(always)]
245    #[must_use]
246    pub fn rx_data_bk0(&mut self) -> RxDataBk0W<Csr7Spec> {
247        RxDataBk0W::new(self, 1)
248    }
249    #[doc = "Bit 2 - Received Setup"]
250    #[inline(always)]
251    #[must_use]
252    pub fn rxsetup(&mut self) -> RxsetupW<Csr7Spec> {
253        RxsetupW::new(self, 2)
254    }
255    #[doc = "Bit 3 - Stall Sent"]
256    #[inline(always)]
257    #[must_use]
258    pub fn stallsent(&mut self) -> StallsentW<Csr7Spec> {
259        StallsentW::new(self, 3)
260    }
261    #[doc = "Bit 4 - Transmit Packet Ready"]
262    #[inline(always)]
263    #[must_use]
264    pub fn txpktrdy(&mut self) -> TxpktrdyW<Csr7Spec> {
265        TxpktrdyW::new(self, 4)
266    }
267    #[doc = "Bit 5 - Force Stall (used by Control, Bulk and Isochronous Endpoints)"]
268    #[inline(always)]
269    #[must_use]
270    pub fn forcestall(&mut self) -> ForcestallW<Csr7Spec> {
271        ForcestallW::new(self, 5)
272    }
273    #[doc = "Bit 6 - Receive Data Bank 1 (only used by endpoints with ping-pong attributes)"]
274    #[inline(always)]
275    #[must_use]
276    pub fn rx_data_bk1(&mut self) -> RxDataBk1W<Csr7Spec> {
277        RxDataBk1W::new(self, 6)
278    }
279    #[doc = "Bit 7 - Transfer Direction (only available for control endpoints)"]
280    #[inline(always)]
281    #[must_use]
282    pub fn dir(&mut self) -> DirW<Csr7Spec> {
283        DirW::new(self, 7)
284    }
285    #[doc = "Bits 8:10 - Endpoint Type"]
286    #[inline(always)]
287    #[must_use]
288    pub fn eptype(&mut self) -> EptypeW<Csr7Spec> {
289        EptypeW::new(self, 8)
290    }
291    #[doc = "Bit 11 - Data Toggle"]
292    #[inline(always)]
293    #[must_use]
294    pub fn dtgle(&mut self) -> DtgleW<Csr7Spec> {
295        DtgleW::new(self, 11)
296    }
297    #[doc = "Bit 15 - Endpoint Enable Disable"]
298    #[inline(always)]
299    #[must_use]
300    pub fn epeds(&mut self) -> EpedsW<Csr7Spec> {
301        EpedsW::new(self, 15)
302    }
303    #[doc = "Bits 16:26 - Number of Bytes Available in the FIFO"]
304    #[inline(always)]
305    #[must_use]
306    pub fn rxbytecnt(&mut self) -> RxbytecntW<Csr7Spec> {
307        RxbytecntW::new(self, 16)
308    }
309}
310#[doc = "Endpoint Control and Status Register 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr7::R`](R).  You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
311pub struct Csr7Spec;
312impl crate::RegisterSpec for Csr7Spec {
313    type Ux = u32;
314}
315#[doc = "`read()` method returns [`csr7::R`](R) reader structure"]
316impl crate::Readable for Csr7Spec {}
317#[doc = "`write(|w| ..)` method takes [`csr7::W`](W) writer structure"]
318impl crate::Writable for Csr7Spec {
319    type Safety = crate::Unsafe;
320    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
321    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
322}
atsam3s8c/udp/csr7.rs

atsam3s8c/udp/
csr7.rs
