atsam3s2c/ssc/
tfmr.rs

1#[doc = "Register `TFMR` reader"]
2pub type R = crate::R<TfmrSpec>;
3#[doc = "Register `TFMR` writer"]
4pub type W = crate::W<TfmrSpec>;
5#[doc = "Field `DATLEN` reader - Data Length"]
6pub type DatlenR = crate::FieldReader;
7#[doc = "Field `DATLEN` writer - Data Length"]
8pub type DatlenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `DATDEF` reader - Data Default Value"]
10pub type DatdefR = crate::BitReader;
11#[doc = "Field `DATDEF` writer - Data Default Value"]
12pub type DatdefW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MSBF` reader - Most Significant Bit First"]
14pub type MsbfR = crate::BitReader;
15#[doc = "Field `MSBF` writer - Most Significant Bit First"]
16pub type MsbfW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DATNB` reader - Data Number per frame"]
18pub type DatnbR = crate::FieldReader;
19#[doc = "Field `DATNB` writer - Data Number per frame"]
20pub type DatnbW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `FSLEN` reader - Transmit Frame Sync Length"]
22pub type FslenR = crate::FieldReader;
23#[doc = "Field `FSLEN` writer - Transmit Frame Sync Length"]
24pub type FslenW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Transmit Frame Sync Output Selection\n\nValue on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq, Eq)]
27#[repr(u8)]
28pub enum Fsos {
29    #[doc = "0: None, RF pin is an input"]
30    None = 0,
31    #[doc = "1: Negative Pulse, RF pin is an output"]
32    Negative = 1,
33    #[doc = "2: Positive Pulse, RF pin is an output"]
34    Positive = 2,
35    #[doc = "3: Driven Low during data transfer"]
36    Low = 3,
37    #[doc = "4: Driven High during data transfer"]
38    High = 4,
39    #[doc = "5: Toggling at each start of data transfer"]
40    Toggling = 5,
41}
42impl From<Fsos> for u8 {
43    #[inline(always)]
44    fn from(variant: Fsos) -> Self {
45        variant as _
46    }
47}
48impl crate::FieldSpec for Fsos {
49    type Ux = u8;
50}
51impl crate::IsEnum for Fsos {}
52#[doc = "Field `FSOS` reader - Transmit Frame Sync Output Selection"]
53pub type FsosR = crate::FieldReader<Fsos>;
54impl FsosR {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub const fn variant(&self) -> Option<Fsos> {
58        match self.bits {
59            0 => Some(Fsos::None),
60            1 => Some(Fsos::Negative),
61            2 => Some(Fsos::Positive),
62            3 => Some(Fsos::Low),
63            4 => Some(Fsos::High),
64            5 => Some(Fsos::Toggling),
65            _ => None,
66        }
67    }
68    #[doc = "None, RF pin is an input"]
69    #[inline(always)]
70    pub fn is_none(&self) -> bool {
71        *self == Fsos::None
72    }
73    #[doc = "Negative Pulse, RF pin is an output"]
74    #[inline(always)]
75    pub fn is_negative(&self) -> bool {
76        *self == Fsos::Negative
77    }
78    #[doc = "Positive Pulse, RF pin is an output"]
79    #[inline(always)]
80    pub fn is_positive(&self) -> bool {
81        *self == Fsos::Positive
82    }
83    #[doc = "Driven Low during data transfer"]
84    #[inline(always)]
85    pub fn is_low(&self) -> bool {
86        *self == Fsos::Low
87    }
88    #[doc = "Driven High during data transfer"]
89    #[inline(always)]
90    pub fn is_high(&self) -> bool {
91        *self == Fsos::High
92    }
93    #[doc = "Toggling at each start of data transfer"]
94    #[inline(always)]
95    pub fn is_toggling(&self) -> bool {
96        *self == Fsos::Toggling
97    }
98}
99#[doc = "Field `FSOS` writer - Transmit Frame Sync Output Selection"]
100pub type FsosW<'a, REG> = crate::FieldWriter<'a, REG, 3, Fsos>;
101impl<'a, REG> FsosW<'a, REG>
102where
103    REG: crate::Writable + crate::RegisterSpec,
104    REG::Ux: From<u8>,
105{
106    #[doc = "None, RF pin is an input"]
107    #[inline(always)]
108    pub fn none(self) -> &'a mut crate::W<REG> {
109        self.variant(Fsos::None)
110    }
111    #[doc = "Negative Pulse, RF pin is an output"]
112    #[inline(always)]
113    pub fn negative(self) -> &'a mut crate::W<REG> {
114        self.variant(Fsos::Negative)
115    }
116    #[doc = "Positive Pulse, RF pin is an output"]
117    #[inline(always)]
118    pub fn positive(self) -> &'a mut crate::W<REG> {
119        self.variant(Fsos::Positive)
120    }
121    #[doc = "Driven Low during data transfer"]
122    #[inline(always)]
123    pub fn low(self) -> &'a mut crate::W<REG> {
124        self.variant(Fsos::Low)
125    }
126    #[doc = "Driven High during data transfer"]
127    #[inline(always)]
128    pub fn high(self) -> &'a mut crate::W<REG> {
129        self.variant(Fsos::High)
130    }
131    #[doc = "Toggling at each start of data transfer"]
132    #[inline(always)]
133    pub fn toggling(self) -> &'a mut crate::W<REG> {
134        self.variant(Fsos::Toggling)
135    }
136}
137#[doc = "Field `FSDEN` reader - Frame Sync Data Enable"]
138pub type FsdenR = crate::BitReader;
139#[doc = "Field `FSDEN` writer - Frame Sync Data Enable"]
140pub type FsdenW<'a, REG> = crate::BitWriter<'a, REG>;
141#[doc = "Frame Sync Edge Detection\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143pub enum Fsedge {
144    #[doc = "0: Positive Edge Detection"]
145    Positive = 0,
146    #[doc = "1: Negative Edge Detection"]
147    Negative = 1,
148}
149impl From<Fsedge> for bool {
150    #[inline(always)]
151    fn from(variant: Fsedge) -> Self {
152        variant as u8 != 0
153    }
154}
155#[doc = "Field `FSEDGE` reader - Frame Sync Edge Detection"]
156pub type FsedgeR = crate::BitReader<Fsedge>;
157impl FsedgeR {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Fsedge {
161        match self.bits {
162            false => Fsedge::Positive,
163            true => Fsedge::Negative,
164        }
165    }
166    #[doc = "Positive Edge Detection"]
167    #[inline(always)]
168    pub fn is_positive(&self) -> bool {
169        *self == Fsedge::Positive
170    }
171    #[doc = "Negative Edge Detection"]
172    #[inline(always)]
173    pub fn is_negative(&self) -> bool {
174        *self == Fsedge::Negative
175    }
176}
177#[doc = "Field `FSEDGE` writer - Frame Sync Edge Detection"]
178pub type FsedgeW<'a, REG> = crate::BitWriter<'a, REG, Fsedge>;
179impl<'a, REG> FsedgeW<'a, REG>
180where
181    REG: crate::Writable + crate::RegisterSpec,
182{
183    #[doc = "Positive Edge Detection"]
184    #[inline(always)]
185    pub fn positive(self) -> &'a mut crate::W<REG> {
186        self.variant(Fsedge::Positive)
187    }
188    #[doc = "Negative Edge Detection"]
189    #[inline(always)]
190    pub fn negative(self) -> &'a mut crate::W<REG> {
191        self.variant(Fsedge::Negative)
192    }
193}
194#[doc = "Field `FSLEN_EXT` reader - FSLEN Field Extension"]
195pub type FslenExtR = crate::FieldReader;
196#[doc = "Field `FSLEN_EXT` writer - FSLEN Field Extension"]
197pub type FslenExtW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
198impl R {
199    #[doc = "Bits 0:4 - Data Length"]
200    #[inline(always)]
201    pub fn datlen(&self) -> DatlenR {
202        DatlenR::new((self.bits & 0x1f) as u8)
203    }
204    #[doc = "Bit 5 - Data Default Value"]
205    #[inline(always)]
206    pub fn datdef(&self) -> DatdefR {
207        DatdefR::new(((self.bits >> 5) & 1) != 0)
208    }
209    #[doc = "Bit 7 - Most Significant Bit First"]
210    #[inline(always)]
211    pub fn msbf(&self) -> MsbfR {
212        MsbfR::new(((self.bits >> 7) & 1) != 0)
213    }
214    #[doc = "Bits 8:11 - Data Number per frame"]
215    #[inline(always)]
216    pub fn datnb(&self) -> DatnbR {
217        DatnbR::new(((self.bits >> 8) & 0x0f) as u8)
218    }
219    #[doc = "Bits 16:19 - Transmit Frame Sync Length"]
220    #[inline(always)]
221    pub fn fslen(&self) -> FslenR {
222        FslenR::new(((self.bits >> 16) & 0x0f) as u8)
223    }
224    #[doc = "Bits 20:22 - Transmit Frame Sync Output Selection"]
225    #[inline(always)]
226    pub fn fsos(&self) -> FsosR {
227        FsosR::new(((self.bits >> 20) & 7) as u8)
228    }
229    #[doc = "Bit 23 - Frame Sync Data Enable"]
230    #[inline(always)]
231    pub fn fsden(&self) -> FsdenR {
232        FsdenR::new(((self.bits >> 23) & 1) != 0)
233    }
234    #[doc = "Bit 24 - Frame Sync Edge Detection"]
235    #[inline(always)]
236    pub fn fsedge(&self) -> FsedgeR {
237        FsedgeR::new(((self.bits >> 24) & 1) != 0)
238    }
239    #[doc = "Bits 28:31 - FSLEN Field Extension"]
240    #[inline(always)]
241    pub fn fslen_ext(&self) -> FslenExtR {
242        FslenExtR::new(((self.bits >> 28) & 0x0f) as u8)
243    }
244}
245impl W {
246    #[doc = "Bits 0:4 - Data Length"]
247    #[inline(always)]
248    #[must_use]
249    pub fn datlen(&mut self) -> DatlenW<TfmrSpec> {
250        DatlenW::new(self, 0)
251    }
252    #[doc = "Bit 5 - Data Default Value"]
253    #[inline(always)]
254    #[must_use]
255    pub fn datdef(&mut self) -> DatdefW<TfmrSpec> {
256        DatdefW::new(self, 5)
257    }
258    #[doc = "Bit 7 - Most Significant Bit First"]
259    #[inline(always)]
260    #[must_use]
261    pub fn msbf(&mut self) -> MsbfW<TfmrSpec> {
262        MsbfW::new(self, 7)
263    }
264    #[doc = "Bits 8:11 - Data Number per frame"]
265    #[inline(always)]
266    #[must_use]
267    pub fn datnb(&mut self) -> DatnbW<TfmrSpec> {
268        DatnbW::new(self, 8)
269    }
270    #[doc = "Bits 16:19 - Transmit Frame Sync Length"]
271    #[inline(always)]
272    #[must_use]
273    pub fn fslen(&mut self) -> FslenW<TfmrSpec> {
274        FslenW::new(self, 16)
275    }
276    #[doc = "Bits 20:22 - Transmit Frame Sync Output Selection"]
277    #[inline(always)]
278    #[must_use]
279    pub fn fsos(&mut self) -> FsosW<TfmrSpec> {
280        FsosW::new(self, 20)
281    }
282    #[doc = "Bit 23 - Frame Sync Data Enable"]
283    #[inline(always)]
284    #[must_use]
285    pub fn fsden(&mut self) -> FsdenW<TfmrSpec> {
286        FsdenW::new(self, 23)
287    }
288    #[doc = "Bit 24 - Frame Sync Edge Detection"]
289    #[inline(always)]
290    #[must_use]
291    pub fn fsedge(&mut self) -> FsedgeW<TfmrSpec> {
292        FsedgeW::new(self, 24)
293    }
294    #[doc = "Bits 28:31 - FSLEN Field Extension"]
295    #[inline(always)]
296    #[must_use]
297    pub fn fslen_ext(&mut self) -> FslenExtW<TfmrSpec> {
298        FslenExtW::new(self, 28)
299    }
300}
301#[doc = "Transmit Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfmr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
302pub struct TfmrSpec;
303impl crate::RegisterSpec for TfmrSpec {
304    type Ux = u32;
305}
306#[doc = "`read()` method returns [`tfmr::R`](R) reader structure"]
307impl crate::Readable for TfmrSpec {}
308#[doc = "`write(|w| ..)` method takes [`tfmr::W`](W) writer structure"]
309impl crate::Writable for TfmrSpec {
310    type Safety = crate::Unsafe;
311    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
312    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
313}
314#[doc = "`reset()` method sets TFMR to value 0"]
315impl crate::Resettable for TfmrSpec {
316    const RESET_VALUE: u32 = 0;
317}
atsam3s2c/ssc/tfmr.rs

atsam3s2c/ssc/
tfmr.rs
