1#[doc = "Register `CSR1` reader"]
2pub type R = crate::R<Csr1Spec>;
3#[doc = "Register `CSR1` writer"]
4pub type W = crate::W<Csr1Spec>;
5#[doc = "Field `CPOL` reader - Clock Polarity"]
6pub type CpolR = crate::BitReader;
7#[doc = "Field `CPOL` writer - Clock Polarity"]
8pub type CpolW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `NCPHA` reader - Clock Phase"]
10pub type NcphaR = crate::BitReader;
11#[doc = "Field `NCPHA` writer - Clock Phase"]
12pub type NcphaW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CSNAAT` reader - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
14pub type CsnaatR = crate::BitReader;
15#[doc = "Field `CSNAAT` writer - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
16pub type CsnaatW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CSAAT` reader - Chip Select Active After Transfer"]
18pub type CsaatR = crate::BitReader;
19#[doc = "Field `CSAAT` writer - Chip Select Active After Transfer"]
20pub type CsaatW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Bits Per Transfer"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23#[repr(u8)]
24pub enum Bits {
25 #[doc = "0: 8 bits for transfer"]
26 _8Bit = 0,
27 #[doc = "1: 9 bits for transfer"]
28 _9Bit = 1,
29 #[doc = "2: 10 bits for transfer"]
30 _10Bit = 2,
31 #[doc = "3: 11 bits for transfer"]
32 _11Bit = 3,
33 #[doc = "4: 12 bits for transfer"]
34 _12Bit = 4,
35 #[doc = "5: 13 bits for transfer"]
36 _13Bit = 5,
37 #[doc = "6: 14 bits for transfer"]
38 _14Bit = 6,
39 #[doc = "7: 15 bits for transfer"]
40 _15Bit = 7,
41 #[doc = "8: 16 bits for transfer"]
42 _16Bit = 8,
43}
44impl From<Bits> for u8 {
45 #[inline(always)]
46 fn from(variant: Bits) -> Self {
47 variant as _
48 }
49}
50impl crate::FieldSpec for Bits {
51 type Ux = u8;
52}
53impl crate::IsEnum for Bits {}
54#[doc = "Field `BITS` reader - Bits Per Transfer"]
55pub type BitsR = crate::FieldReader<Bits>;
56impl BitsR {
57 #[doc = "Get enumerated values variant"]
58 #[inline(always)]
59 pub const fn variant(&self) -> Option<Bits> {
60 match self.bits {
61 0 => Some(Bits::_8Bit),
62 1 => Some(Bits::_9Bit),
63 2 => Some(Bits::_10Bit),
64 3 => Some(Bits::_11Bit),
65 4 => Some(Bits::_12Bit),
66 5 => Some(Bits::_13Bit),
67 6 => Some(Bits::_14Bit),
68 7 => Some(Bits::_15Bit),
69 8 => Some(Bits::_16Bit),
70 _ => None,
71 }
72 }
73 #[doc = "8 bits for transfer"]
74 #[inline(always)]
75 pub fn is_8_bit(&self) -> bool {
76 *self == Bits::_8Bit
77 }
78 #[doc = "9 bits for transfer"]
79 #[inline(always)]
80 pub fn is_9_bit(&self) -> bool {
81 *self == Bits::_9Bit
82 }
83 #[doc = "10 bits for transfer"]
84 #[inline(always)]
85 pub fn is_10_bit(&self) -> bool {
86 *self == Bits::_10Bit
87 }
88 #[doc = "11 bits for transfer"]
89 #[inline(always)]
90 pub fn is_11_bit(&self) -> bool {
91 *self == Bits::_11Bit
92 }
93 #[doc = "12 bits for transfer"]
94 #[inline(always)]
95 pub fn is_12_bit(&self) -> bool {
96 *self == Bits::_12Bit
97 }
98 #[doc = "13 bits for transfer"]
99 #[inline(always)]
100 pub fn is_13_bit(&self) -> bool {
101 *self == Bits::_13Bit
102 }
103 #[doc = "14 bits for transfer"]
104 #[inline(always)]
105 pub fn is_14_bit(&self) -> bool {
106 *self == Bits::_14Bit
107 }
108 #[doc = "15 bits for transfer"]
109 #[inline(always)]
110 pub fn is_15_bit(&self) -> bool {
111 *self == Bits::_15Bit
112 }
113 #[doc = "16 bits for transfer"]
114 #[inline(always)]
115 pub fn is_16_bit(&self) -> bool {
116 *self == Bits::_16Bit
117 }
118}
119#[doc = "Field `BITS` writer - Bits Per Transfer"]
120pub type BitsW<'a, REG> = crate::FieldWriter<'a, REG, 4, Bits>;
121impl<'a, REG> BitsW<'a, REG>
122where
123 REG: crate::Writable + crate::RegisterSpec,
124 REG::Ux: From<u8>,
125{
126 #[doc = "8 bits for transfer"]
127 #[inline(always)]
128 pub fn _8_bit(self) -> &'a mut crate::W<REG> {
129 self.variant(Bits::_8Bit)
130 }
131 #[doc = "9 bits for transfer"]
132 #[inline(always)]
133 pub fn _9_bit(self) -> &'a mut crate::W<REG> {
134 self.variant(Bits::_9Bit)
135 }
136 #[doc = "10 bits for transfer"]
137 #[inline(always)]
138 pub fn _10_bit(self) -> &'a mut crate::W<REG> {
139 self.variant(Bits::_10Bit)
140 }
141 #[doc = "11 bits for transfer"]
142 #[inline(always)]
143 pub fn _11_bit(self) -> &'a mut crate::W<REG> {
144 self.variant(Bits::_11Bit)
145 }
146 #[doc = "12 bits for transfer"]
147 #[inline(always)]
148 pub fn _12_bit(self) -> &'a mut crate::W<REG> {
149 self.variant(Bits::_12Bit)
150 }
151 #[doc = "13 bits for transfer"]
152 #[inline(always)]
153 pub fn _13_bit(self) -> &'a mut crate::W<REG> {
154 self.variant(Bits::_13Bit)
155 }
156 #[doc = "14 bits for transfer"]
157 #[inline(always)]
158 pub fn _14_bit(self) -> &'a mut crate::W<REG> {
159 self.variant(Bits::_14Bit)
160 }
161 #[doc = "15 bits for transfer"]
162 #[inline(always)]
163 pub fn _15_bit(self) -> &'a mut crate::W<REG> {
164 self.variant(Bits::_15Bit)
165 }
166 #[doc = "16 bits for transfer"]
167 #[inline(always)]
168 pub fn _16_bit(self) -> &'a mut crate::W<REG> {
169 self.variant(Bits::_16Bit)
170 }
171}
172#[doc = "Field `SCBR` reader - Serial Clock Baud Rate"]
173pub type ScbrR = crate::FieldReader;
174#[doc = "Field `SCBR` writer - Serial Clock Baud Rate"]
175pub type ScbrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
176#[doc = "Field `DLYBS` reader - Delay Before SPCK"]
177pub type DlybsR = crate::FieldReader;
178#[doc = "Field `DLYBS` writer - Delay Before SPCK"]
179pub type DlybsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
180#[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"]
181pub type DlybctR = crate::FieldReader;
182#[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"]
183pub type DlybctW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
184impl R {
185 #[doc = "Bit 0 - Clock Polarity"]
186 #[inline(always)]
187 pub fn cpol(&self) -> CpolR {
188 CpolR::new((self.bits & 1) != 0)
189 }
190 #[doc = "Bit 1 - Clock Phase"]
191 #[inline(always)]
192 pub fn ncpha(&self) -> NcphaR {
193 NcphaR::new(((self.bits >> 1) & 1) != 0)
194 }
195 #[doc = "Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
196 #[inline(always)]
197 pub fn csnaat(&self) -> CsnaatR {
198 CsnaatR::new(((self.bits >> 2) & 1) != 0)
199 }
200 #[doc = "Bit 3 - Chip Select Active After Transfer"]
201 #[inline(always)]
202 pub fn csaat(&self) -> CsaatR {
203 CsaatR::new(((self.bits >> 3) & 1) != 0)
204 }
205 #[doc = "Bits 4:7 - Bits Per Transfer"]
206 #[inline(always)]
207 pub fn bits_(&self) -> BitsR {
208 BitsR::new(((self.bits >> 4) & 0x0f) as u8)
209 }
210 #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
211 #[inline(always)]
212 pub fn scbr(&self) -> ScbrR {
213 ScbrR::new(((self.bits >> 8) & 0xff) as u8)
214 }
215 #[doc = "Bits 16:23 - Delay Before SPCK"]
216 #[inline(always)]
217 pub fn dlybs(&self) -> DlybsR {
218 DlybsR::new(((self.bits >> 16) & 0xff) as u8)
219 }
220 #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
221 #[inline(always)]
222 pub fn dlybct(&self) -> DlybctR {
223 DlybctR::new(((self.bits >> 24) & 0xff) as u8)
224 }
225}
226impl W {
227 #[doc = "Bit 0 - Clock Polarity"]
228 #[inline(always)]
229 #[must_use]
230 pub fn cpol(&mut self) -> CpolW<Csr1Spec> {
231 CpolW::new(self, 0)
232 }
233 #[doc = "Bit 1 - Clock Phase"]
234 #[inline(always)]
235 #[must_use]
236 pub fn ncpha(&mut self) -> NcphaW<Csr1Spec> {
237 NcphaW::new(self, 1)
238 }
239 #[doc = "Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"]
240 #[inline(always)]
241 #[must_use]
242 pub fn csnaat(&mut self) -> CsnaatW<Csr1Spec> {
243 CsnaatW::new(self, 2)
244 }
245 #[doc = "Bit 3 - Chip Select Active After Transfer"]
246 #[inline(always)]
247 #[must_use]
248 pub fn csaat(&mut self) -> CsaatW<Csr1Spec> {
249 CsaatW::new(self, 3)
250 }
251 #[doc = "Bits 4:7 - Bits Per Transfer"]
252 #[inline(always)]
253 #[must_use]
254 pub fn bits_(&mut self) -> BitsW<Csr1Spec> {
255 BitsW::new(self, 4)
256 }
257 #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
258 #[inline(always)]
259 #[must_use]
260 pub fn scbr(&mut self) -> ScbrW<Csr1Spec> {
261 ScbrW::new(self, 8)
262 }
263 #[doc = "Bits 16:23 - Delay Before SPCK"]
264 #[inline(always)]
265 #[must_use]
266 pub fn dlybs(&mut self) -> DlybsW<Csr1Spec> {
267 DlybsW::new(self, 16)
268 }
269 #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
270 #[inline(always)]
271 #[must_use]
272 pub fn dlybct(&mut self) -> DlybctW<Csr1Spec> {
273 DlybctW::new(self, 24)
274 }
275}
276#[doc = "Chip Select Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr1::R`](R). You can [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct Csr1Spec;
278impl crate::RegisterSpec for Csr1Spec {
279 type Ux = u32;
280}
281#[doc = "`read()` method returns [`csr1::R`](R) reader structure"]
282impl crate::Readable for Csr1Spec {}
283#[doc = "`write(|w| ..)` method takes [`csr1::W`](W) writer structure"]
284impl crate::Writable for Csr1Spec {
285 type Safety = crate::Unsafe;
286 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
288}