atsam3s2a/uart1/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub type R = crate::R<ImrSpec>;
3#[doc = "Field `RXRDY` reader - Mask RXRDY Interrupt"]
4pub type RxrdyR = crate::BitReader;
5#[doc = "Field `TXRDY` reader - Disable TXRDY Interrupt"]
6pub type TxrdyR = crate::BitReader;
7#[doc = "Field `ENDRX` reader - Mask End of Receive Transfer Interrupt"]
8pub type EndrxR = crate::BitReader;
9#[doc = "Field `ENDTX` reader - Mask End of Transmit Interrupt"]
10pub type EndtxR = crate::BitReader;
11#[doc = "Field `OVRE` reader - Mask Overrun Error Interrupt"]
12pub type OvreR = crate::BitReader;
13#[doc = "Field `FRAME` reader - Mask Framing Error Interrupt"]
14pub type FrameR = crate::BitReader;
15#[doc = "Field `PARE` reader - Mask Parity Error Interrupt"]
16pub type PareR = crate::BitReader;
17#[doc = "Field `TXEMPTY` reader - Mask TXEMPTY Interrupt"]
18pub type TxemptyR = crate::BitReader;
19#[doc = "Field `TXBUFE` reader - Mask TXBUFE Interrupt"]
20pub type TxbufeR = crate::BitReader;
21#[doc = "Field `RXBUFF` reader - Mask RXBUFF Interrupt"]
22pub type RxbuffR = crate::BitReader;
23impl R {
24    #[doc = "Bit 0 - Mask RXRDY Interrupt"]
25    #[inline(always)]
26    pub fn rxrdy(&self) -> RxrdyR {
27        RxrdyR::new((self.bits & 1) != 0)
28    }
29    #[doc = "Bit 1 - Disable TXRDY Interrupt"]
30    #[inline(always)]
31    pub fn txrdy(&self) -> TxrdyR {
32        TxrdyR::new(((self.bits >> 1) & 1) != 0)
33    }
34    #[doc = "Bit 3 - Mask End of Receive Transfer Interrupt"]
35    #[inline(always)]
36    pub fn endrx(&self) -> EndrxR {
37        EndrxR::new(((self.bits >> 3) & 1) != 0)
38    }
39    #[doc = "Bit 4 - Mask End of Transmit Interrupt"]
40    #[inline(always)]
41    pub fn endtx(&self) -> EndtxR {
42        EndtxR::new(((self.bits >> 4) & 1) != 0)
43    }
44    #[doc = "Bit 5 - Mask Overrun Error Interrupt"]
45    #[inline(always)]
46    pub fn ovre(&self) -> OvreR {
47        OvreR::new(((self.bits >> 5) & 1) != 0)
48    }
49    #[doc = "Bit 6 - Mask Framing Error Interrupt"]
50    #[inline(always)]
51    pub fn frame(&self) -> FrameR {
52        FrameR::new(((self.bits >> 6) & 1) != 0)
53    }
54    #[doc = "Bit 7 - Mask Parity Error Interrupt"]
55    #[inline(always)]
56    pub fn pare(&self) -> PareR {
57        PareR::new(((self.bits >> 7) & 1) != 0)
58    }
59    #[doc = "Bit 9 - Mask TXEMPTY Interrupt"]
60    #[inline(always)]
61    pub fn txempty(&self) -> TxemptyR {
62        TxemptyR::new(((self.bits >> 9) & 1) != 0)
63    }
64    #[doc = "Bit 11 - Mask TXBUFE Interrupt"]
65    #[inline(always)]
66    pub fn txbufe(&self) -> TxbufeR {
67        TxbufeR::new(((self.bits >> 11) & 1) != 0)
68    }
69    #[doc = "Bit 12 - Mask RXBUFF Interrupt"]
70    #[inline(always)]
71    pub fn rxbuff(&self) -> RxbuffR {
72        RxbuffR::new(((self.bits >> 12) & 1) != 0)
73    }
74}
75#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
76pub struct ImrSpec;
77impl crate::RegisterSpec for ImrSpec {
78    type Ux = u32;
79}
80#[doc = "`read()` method returns [`imr::R`](R) reader structure"]
81impl crate::Readable for ImrSpec {}
82#[doc = "`reset()` method sets IMR to value 0"]
83impl crate::Resettable for ImrSpec {
84    const RESET_VALUE: u32 = 0;
85}
atsam3s2a/uart1/imr.rs

atsam3s2a/uart1/
imr.rs
