atsam3n1c/pwm/
cdty3.rs

1#[doc = "Register `CDTY3` reader"]
2pub type R = crate::R<Cdty3Spec>;
3#[doc = "Register `CDTY3` writer"]
4pub type W = crate::W<Cdty3Spec>;
5#[doc = "Field `CDTY` reader - Channel Duty Cycle"]
6pub type CdtyR = crate::FieldReader<u32>;
7#[doc = "Field `CDTY` writer - Channel Duty Cycle"]
8pub type CdtyW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Channel Duty Cycle"]
11    #[inline(always)]
12    pub fn cdty(&self) -> CdtyR {
13        CdtyR::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - Channel Duty Cycle"]
18    #[inline(always)]
19    #[must_use]
20    pub fn cdty(&mut self) -> CdtyW<Cdty3Spec> {
21        CdtyW::new(self, 0)
22    }
23}
24#[doc = "PWM Channel Duty Cycle Register (ch_num = 3)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdty3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdty3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
25pub struct Cdty3Spec;
26impl crate::RegisterSpec for Cdty3Spec {
27    type Ux = u32;
28}
29#[doc = "`read()` method returns [`cdty3::R`](R) reader structure"]
30impl crate::Readable for Cdty3Spec {}
31#[doc = "`write(|w| ..)` method takes [`cdty3::W`](W) writer structure"]
32impl crate::Writable for Cdty3Spec {
33    type Safety = crate::Unsafe;
34    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
36}
37#[doc = "`reset()` method sets CDTY3 to value 0"]
38impl crate::Resettable for Cdty3Spec {
39    const RESET_VALUE: u32 = 0;
40}
atsam3n1c/pwm/cdty3.rs

atsam3n1c/pwm/
cdty3.rs
