atm90e32_async/
error.rs

1// SPDX-License-Identifier: (GPL-2.0-or-later OR Apache-2.0)
2// Copyright (c) Viacheslav Bocharov <v@baodeep.com> and JetHome (r)
3
4//! Error types returned by the driver.
5
6/// Errors that can occur while talking to the ATM90E32.
7///
8/// The generic parameter `E` is the underlying SPI transport error type
9/// (usually `<SPI as embedded_hal_async::spi::ErrorType>::Error`).
10///
11/// This enum is marked `#[non_exhaustive]` so future variants can be added
12/// without a semver-breaking change.
13#[derive(Debug)]
14#[non_exhaustive]
15#[cfg_attr(feature = "defmt", derive(defmt::Format))]
16pub enum Error<E> {
17    /// Underlying SPI transport error.
18    Spi(E),
19    /// Probe did not find a responsive chip. The SysStatus0 register read
20    /// back as `0x0000` or `0xFFFF`, indicating either a missing device or
21    /// a floating SPI bus.
22    NotPresent,
23    /// The initialization sequence failed at the given stage.
24    InitFailed(InitStage),
25}
26
27/// The stage of [`Atm90e32::init`](crate::Atm90e32::init) at which a failure
28/// occurred.
29///
30/// Useful for diagnostics and logging. Marked `#[non_exhaustive]` to allow
31/// future variants.
32///
33/// [`Atm90e32::init`]: crate::Atm90e32::init
34#[derive(Debug, Clone, Copy, PartialEq, Eq)]
35#[non_exhaustive]
36#[cfg_attr(feature = "defmt", derive(defmt::Format))]
37pub enum InitStage {
38    /// Soft reset register write (`REG_SOFTRESET`).
39    SoftReset,
40    /// Unlocking the configuration registers (`REG_CFGREGACCEN = 0x55AA`).
41    UnlockConfig,
42    /// Enabling metering (`REG_METEREN = 0x0001`).
43    EnableMeter,
44    /// Writing the sag/peak detector configuration (`REG_SAGPEAKDETCFG`).
45    WriteSagPeak,
46    /// Writing the PL constant pair (`REG_PLCONSTH`, `REG_PLCONSTL`).
47    WritePlConst,
48    /// Writing the zero-crossing configuration (`REG_ZXCONFIG`).
49    WriteZxConfig,
50    /// Writing the metering mode 0 register (`REG_MMODE0`).
51    WriteMMode0,
52    /// Writing the metering mode 1 register (`REG_MMODE1`) — PGA gain.
53    WriteMMode1,
54    /// Writing the frequency high/low threshold pair.
55    WriteFreqThresholds,
56    /// Writing the startup thresholds (P/Q/S start and per-phase thresholds).
57    WriteStartupThresholds,
58    /// Writing the per-phase voltage gain registers.
59    WriteVoltageGains,
60    /// Writing the per-phase current gain registers.
61    WriteCurrentGains,
62    /// Locking the configuration registers (`REG_CFGREGACCEN = 0x0000`).
63    LockConfig,
64}
atm90e32_async/error.rs

atm90e32_async/
error.rs
