at32f4xx_pac/at32f423/gpioa/
muxl.rs

1#[doc = "Register `MUXL` reader"]
2pub type R = crate::R<MUXL_SPEC>;
3#[doc = "Register `MUXL` writer"]
4pub type W = crate::W<MUXL_SPEC>;
5#[doc = "Field `MUX(0-7)` reader - GPIOx pin %s muxing"]
6pub type MUX_R = crate::FieldReader;
7#[doc = "Field `MUX(0-7)` writer - GPIOx pin %s muxing"]
8pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9impl R {
10    #[doc = "GPIOx pin (0-7) muxing"]
11    #[doc = ""]
12    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `MUX0` field.</div>"]
13    #[inline(always)]
14    pub fn mux(&self, n: u8) -> MUX_R {
15        #[allow(clippy::no_effect)]
16        [(); 8][n as usize];
17        MUX_R::new(((self.bits >> (n * 4)) & 0x0f) as u8)
18    }
19    #[doc = "Iterator for array of:"]
20    #[doc = "GPIOx pin (0-7) muxing"]
21    #[inline(always)]
22    pub fn mux_iter(&self) -> impl Iterator<Item = MUX_R> + '_ {
23        (0..8).map(move |n| MUX_R::new(((self.bits >> (n * 4)) & 0x0f) as u8))
24    }
25    #[doc = "Bits 0:3 - GPIOx pin 0 muxing"]
26    #[inline(always)]
27    pub fn mux0(&self) -> MUX_R {
28        MUX_R::new((self.bits & 0x0f) as u8)
29    }
30    #[doc = "Bits 4:7 - GPIOx pin 1 muxing"]
31    #[inline(always)]
32    pub fn mux1(&self) -> MUX_R {
33        MUX_R::new(((self.bits >> 4) & 0x0f) as u8)
34    }
35    #[doc = "Bits 8:11 - GPIOx pin 2 muxing"]
36    #[inline(always)]
37    pub fn mux2(&self) -> MUX_R {
38        MUX_R::new(((self.bits >> 8) & 0x0f) as u8)
39    }
40    #[doc = "Bits 12:15 - GPIOx pin 3 muxing"]
41    #[inline(always)]
42    pub fn mux3(&self) -> MUX_R {
43        MUX_R::new(((self.bits >> 12) & 0x0f) as u8)
44    }
45    #[doc = "Bits 16:19 - GPIOx pin 4 muxing"]
46    #[inline(always)]
47    pub fn mux4(&self) -> MUX_R {
48        MUX_R::new(((self.bits >> 16) & 0x0f) as u8)
49    }
50    #[doc = "Bits 20:23 - GPIOx pin 5 muxing"]
51    #[inline(always)]
52    pub fn mux5(&self) -> MUX_R {
53        MUX_R::new(((self.bits >> 20) & 0x0f) as u8)
54    }
55    #[doc = "Bits 24:27 - GPIOx pin 6 muxing"]
56    #[inline(always)]
57    pub fn mux6(&self) -> MUX_R {
58        MUX_R::new(((self.bits >> 24) & 0x0f) as u8)
59    }
60    #[doc = "Bits 28:31 - GPIOx pin 7 muxing"]
61    #[inline(always)]
62    pub fn mux7(&self) -> MUX_R {
63        MUX_R::new(((self.bits >> 28) & 0x0f) as u8)
64    }
65}
66impl core::fmt::Debug for R {
67    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
68        f.debug_struct("MUXL")
69            .field("mux0", &self.mux0())
70            .field("mux1", &self.mux1())
71            .field("mux2", &self.mux2())
72            .field("mux3", &self.mux3())
73            .field("mux4", &self.mux4())
74            .field("mux5", &self.mux5())
75            .field("mux6", &self.mux6())
76            .field("mux7", &self.mux7())
77            .finish()
78    }
79}
80impl W {
81    #[doc = "GPIOx pin (0-7) muxing"]
82    #[doc = ""]
83    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `MUX0` field.</div>"]
84    #[inline(always)]
85    pub fn mux(&mut self, n: u8) -> MUX_W<'_, MUXL_SPEC> {
86        #[allow(clippy::no_effect)]
87        [(); 8][n as usize];
88        MUX_W::new(self, n * 4)
89    }
90    #[doc = "Bits 0:3 - GPIOx pin 0 muxing"]
91    #[inline(always)]
92    pub fn mux0(&mut self) -> MUX_W<'_, MUXL_SPEC> {
93        MUX_W::new(self, 0)
94    }
95    #[doc = "Bits 4:7 - GPIOx pin 1 muxing"]
96    #[inline(always)]
97    pub fn mux1(&mut self) -> MUX_W<'_, MUXL_SPEC> {
98        MUX_W::new(self, 4)
99    }
100    #[doc = "Bits 8:11 - GPIOx pin 2 muxing"]
101    #[inline(always)]
102    pub fn mux2(&mut self) -> MUX_W<'_, MUXL_SPEC> {
103        MUX_W::new(self, 8)
104    }
105    #[doc = "Bits 12:15 - GPIOx pin 3 muxing"]
106    #[inline(always)]
107    pub fn mux3(&mut self) -> MUX_W<'_, MUXL_SPEC> {
108        MUX_W::new(self, 12)
109    }
110    #[doc = "Bits 16:19 - GPIOx pin 4 muxing"]
111    #[inline(always)]
112    pub fn mux4(&mut self) -> MUX_W<'_, MUXL_SPEC> {
113        MUX_W::new(self, 16)
114    }
115    #[doc = "Bits 20:23 - GPIOx pin 5 muxing"]
116    #[inline(always)]
117    pub fn mux5(&mut self) -> MUX_W<'_, MUXL_SPEC> {
118        MUX_W::new(self, 20)
119    }
120    #[doc = "Bits 24:27 - GPIOx pin 6 muxing"]
121    #[inline(always)]
122    pub fn mux6(&mut self) -> MUX_W<'_, MUXL_SPEC> {
123        MUX_W::new(self, 24)
124    }
125    #[doc = "Bits 28:31 - GPIOx pin 7 muxing"]
126    #[inline(always)]
127    pub fn mux7(&mut self) -> MUX_W<'_, MUXL_SPEC> {
128        MUX_W::new(self, 28)
129    }
130}
131#[doc = "GPIO muxing function low register\n\nYou can [`read`](crate::Reg::read) this register and get [`muxl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`muxl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
132pub struct MUXL_SPEC;
133impl crate::RegisterSpec for MUXL_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [`muxl::R`](R) reader structure"]
137impl crate::Readable for MUXL_SPEC {}
138#[doc = "`write(|w| ..)` method takes [`muxl::W`](W) writer structure"]
139impl crate::Writable for MUXL_SPEC {
140    type Safety = crate::Unsafe;
141}
142#[doc = "`reset()` method sets MUXL to value 0"]
143impl crate::Resettable for MUXL_SPEC {}
at32f4xx_pac/at32f423/gpioa/muxl.rs

at32f4xx_pac/at32f423/gpioa/
muxl.rs
