at32f4xx_pac/at32f415/tmr2/
cctrl.rs

1#[doc = "Register `CCTRL` reader"]
2pub type R = crate::R<CCTRL_SPEC>;
3#[doc = "Register `CCTRL` writer"]
4pub type W = crate::W<CCTRL_SPEC>;
5#[doc = "Channel %s enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum C1enr {
8    #[doc = "0: Channel is disabled"]
9    Disabled = 0,
10    #[doc = "1: Channel is enabled"]
11    Enabled = 1,
12}
13impl From<C1enr> for bool {
14    #[inline(always)]
15    fn from(variant: C1enr) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CEN(1-4)` reader - Channel %s enable"]
20pub type CEN_R = crate::BitReader<C1enr>;
21impl CEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> C1enr {
25        match self.bits {
26            false => C1enr::Disabled,
27            true => C1enr::Enabled,
28        }
29    }
30    #[doc = "Channel is disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == C1enr::Disabled
34    }
35    #[doc = "Channel is enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == C1enr::Enabled
39    }
40}
41#[doc = "Channel %s enable\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum C1enwWO {
44    #[doc = "0: Channel disable"]
45    Disable = 0,
46    #[doc = "1: Channel enable"]
47    Enable = 1,
48}
49impl From<C1enwWO> for bool {
50    #[inline(always)]
51    fn from(variant: C1enwWO) -> Self {
52        variant as u8 != 0
53    }
54}
55#[doc = "Field `CEN(1-4)` writer - Channel %s enable"]
56pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG, C1enwWO>;
57impl<'a, REG> CEN_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60{
61    #[doc = "Channel disable"]
62    #[inline(always)]
63    pub fn disable(self) -> &'a mut crate::W<REG> {
64        self.variant(C1enwWO::Disable)
65    }
66    #[doc = "Channel enable"]
67    #[inline(always)]
68    pub fn enable(self) -> &'a mut crate::W<REG> {
69        self.variant(C1enwWO::Enable)
70    }
71}
72#[doc = "Channel %s polarity\n\nValue on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum C1P_A {
75    #[doc = "0: Output active high or Input active rising edge"]
76    High = 0,
77    #[doc = "1: Output active low or Input active falling edge"]
78    Low = 1,
79}
80impl From<C1P_A> for bool {
81    #[inline(always)]
82    fn from(variant: C1P_A) -> Self {
83        variant as u8 != 0
84    }
85}
86#[doc = "Field `CP(1-4)` reader - Channel %s polarity"]
87pub type CP_R = crate::BitReader<C1P_A>;
88impl CP_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> C1P_A {
92        match self.bits {
93            false => C1P_A::High,
94            true => C1P_A::Low,
95        }
96    }
97    #[doc = "Output active high or Input active rising edge"]
98    #[inline(always)]
99    pub fn is_high(&self) -> bool {
100        *self == C1P_A::High
101    }
102    #[doc = "Output active low or Input active falling edge"]
103    #[inline(always)]
104    pub fn is_low(&self) -> bool {
105        *self == C1P_A::Low
106    }
107}
108#[doc = "Field `CP(1-4)` writer - Channel %s polarity"]
109pub type CP_W<'a, REG> = crate::BitWriter<'a, REG, C1P_A>;
110impl<'a, REG> CP_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113{
114    #[doc = "Output active high or Input active rising edge"]
115    #[inline(always)]
116    pub fn high(self) -> &'a mut crate::W<REG> {
117        self.variant(C1P_A::High)
118    }
119    #[doc = "Output active low or Input active falling edge"]
120    #[inline(always)]
121    pub fn low(self) -> &'a mut crate::W<REG> {
122        self.variant(C1P_A::Low)
123    }
124}
125impl R {
126    #[doc = "Channel (1-4) enable"]
127    #[doc = ""]
128    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1EN` field.</div>"]
129    #[inline(always)]
130    pub fn cen(&self, n: u8) -> CEN_R {
131        #[allow(clippy::no_effect)]
132        [(); 4][n as usize];
133        CEN_R::new(((self.bits >> (n * 4)) & 1) != 0)
134    }
135    #[doc = "Iterator for array of:"]
136    #[doc = "Channel (1-4) enable"]
137    #[inline(always)]
138    pub fn cen_iter(&self) -> impl Iterator<Item = CEN_R> + '_ {
139        (0..4).map(move |n| CEN_R::new(((self.bits >> (n * 4)) & 1) != 0))
140    }
141    #[doc = "Bit 0 - Channel 1 enable"]
142    #[inline(always)]
143    pub fn c1en(&self) -> CEN_R {
144        CEN_R::new((self.bits & 1) != 0)
145    }
146    #[doc = "Bit 4 - Channel 2 enable"]
147    #[inline(always)]
148    pub fn c2en(&self) -> CEN_R {
149        CEN_R::new(((self.bits >> 4) & 1) != 0)
150    }
151    #[doc = "Bit 8 - Channel 3 enable"]
152    #[inline(always)]
153    pub fn c3en(&self) -> CEN_R {
154        CEN_R::new(((self.bits >> 8) & 1) != 0)
155    }
156    #[doc = "Bit 12 - Channel 4 enable"]
157    #[inline(always)]
158    pub fn c4en(&self) -> CEN_R {
159        CEN_R::new(((self.bits >> 12) & 1) != 0)
160    }
161    #[doc = "Channel (1-4) polarity"]
162    #[doc = ""]
163    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1P` field.</div>"]
164    #[inline(always)]
165    pub fn cp(&self, n: u8) -> CP_R {
166        #[allow(clippy::no_effect)]
167        [(); 4][n as usize];
168        CP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
169    }
170    #[doc = "Iterator for array of:"]
171    #[doc = "Channel (1-4) polarity"]
172    #[inline(always)]
173    pub fn cp_iter(&self) -> impl Iterator<Item = CP_R> + '_ {
174        (0..4).map(move |n| CP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
175    }
176    #[doc = "Bit 1 - Channel 1 polarity"]
177    #[inline(always)]
178    pub fn c1p(&self) -> CP_R {
179        CP_R::new(((self.bits >> 1) & 1) != 0)
180    }
181    #[doc = "Bit 5 - Channel 2 polarity"]
182    #[inline(always)]
183    pub fn c2p(&self) -> CP_R {
184        CP_R::new(((self.bits >> 5) & 1) != 0)
185    }
186    #[doc = "Bit 9 - Channel 3 polarity"]
187    #[inline(always)]
188    pub fn c3p(&self) -> CP_R {
189        CP_R::new(((self.bits >> 9) & 1) != 0)
190    }
191    #[doc = "Bit 13 - Channel 4 polarity"]
192    #[inline(always)]
193    pub fn c4p(&self) -> CP_R {
194        CP_R::new(((self.bits >> 13) & 1) != 0)
195    }
196}
197impl core::fmt::Debug for R {
198    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
199        f.debug_struct("CCTRL")
200            .field("c1p", &self.c1p())
201            .field("c2p", &self.c2p())
202            .field("c3p", &self.c3p())
203            .field("c4p", &self.c4p())
204            .field("c1en", &self.c1en())
205            .field("c2en", &self.c2en())
206            .field("c3en", &self.c3en())
207            .field("c4en", &self.c4en())
208            .finish()
209    }
210}
211impl W {
212    #[doc = "Channel (1-4) enable"]
213    #[doc = ""]
214    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1EN` field.</div>"]
215    #[inline(always)]
216    pub fn cen(&mut self, n: u8) -> CEN_W<'_, CCTRL_SPEC> {
217        #[allow(clippy::no_effect)]
218        [(); 4][n as usize];
219        CEN_W::new(self, n * 4)
220    }
221    #[doc = "Bit 0 - Channel 1 enable"]
222    #[inline(always)]
223    pub fn c1en(&mut self) -> CEN_W<'_, CCTRL_SPEC> {
224        CEN_W::new(self, 0)
225    }
226    #[doc = "Bit 4 - Channel 2 enable"]
227    #[inline(always)]
228    pub fn c2en(&mut self) -> CEN_W<'_, CCTRL_SPEC> {
229        CEN_W::new(self, 4)
230    }
231    #[doc = "Bit 8 - Channel 3 enable"]
232    #[inline(always)]
233    pub fn c3en(&mut self) -> CEN_W<'_, CCTRL_SPEC> {
234        CEN_W::new(self, 8)
235    }
236    #[doc = "Bit 12 - Channel 4 enable"]
237    #[inline(always)]
238    pub fn c4en(&mut self) -> CEN_W<'_, CCTRL_SPEC> {
239        CEN_W::new(self, 12)
240    }
241    #[doc = "Channel (1-4) polarity"]
242    #[doc = ""]
243    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1P` field.</div>"]
244    #[inline(always)]
245    pub fn cp(&mut self, n: u8) -> CP_W<'_, CCTRL_SPEC> {
246        #[allow(clippy::no_effect)]
247        [(); 4][n as usize];
248        CP_W::new(self, n * 4 + 1)
249    }
250    #[doc = "Bit 1 - Channel 1 polarity"]
251    #[inline(always)]
252    pub fn c1p(&mut self) -> CP_W<'_, CCTRL_SPEC> {
253        CP_W::new(self, 1)
254    }
255    #[doc = "Bit 5 - Channel 2 polarity"]
256    #[inline(always)]
257    pub fn c2p(&mut self) -> CP_W<'_, CCTRL_SPEC> {
258        CP_W::new(self, 5)
259    }
260    #[doc = "Bit 9 - Channel 3 polarity"]
261    #[inline(always)]
262    pub fn c3p(&mut self) -> CP_W<'_, CCTRL_SPEC> {
263        CP_W::new(self, 9)
264    }
265    #[doc = "Bit 13 - Channel 4 polarity"]
266    #[inline(always)]
267    pub fn c4p(&mut self) -> CP_W<'_, CCTRL_SPEC> {
268        CP_W::new(self, 13)
269    }
270}
271#[doc = "Channel control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct CCTRL_SPEC;
273impl crate::RegisterSpec for CCTRL_SPEC {
274    type Ux = u32;
275}
276#[doc = "`read()` method returns [`cctrl::R`](R) reader structure"]
277impl crate::Readable for CCTRL_SPEC {}
278#[doc = "`write(|w| ..)` method takes [`cctrl::W`](W) writer structure"]
279impl crate::Writable for CCTRL_SPEC {
280    type Safety = crate::Unsafe;
281}
282#[doc = "`reset()` method sets CCTRL to value 0"]
283impl crate::Resettable for CCTRL_SPEC {}
at32f4xx_pac/at32f415/tmr2/cctrl.rs

at32f4xx_pac/at32f415/tmr2/
cctrl.rs
