at32f4xx_pac/at32f421/tmr1/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Channel buffer control\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Cbctrlr {
8    #[doc = "0: CxEN, CxCEN and CxOCTRL bits are not buffered"]
9    Disabled = 0,
10    #[doc = "1: CxEN, CxCEN and CxOCTRL bits are buffered"]
11    Enabled = 1,
12}
13impl From<Cbctrlr> for bool {
14    #[inline(always)]
15    fn from(variant: Cbctrlr) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CBCTRL` reader - Channel buffer control"]
20pub type CBCTRL_R = crate::BitReader<Cbctrlr>;
21impl CBCTRL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Cbctrlr {
25        match self.bits {
26            false => Cbctrlr::Disabled,
27            true => Cbctrlr::Enabled,
28        }
29    }
30    #[doc = "CxEN, CxCEN and CxOCTRL bits are not buffered"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Cbctrlr::Disabled
34    }
35    #[doc = "CxEN, CxCEN and CxOCTRL bits are buffered"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Cbctrlr::Enabled
39    }
40}
41#[doc = "Channel buffer control\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum CbctrlwWO {
44    #[doc = "0: CxEN, CxCEN and CxOCTRL bits buffer disable"]
45    Disable = 0,
46    #[doc = "1: CxEN, CxCEN and CxOCTRL bits buffer enable"]
47    Enable = 1,
48}
49impl From<CbctrlwWO> for bool {
50    #[inline(always)]
51    fn from(variant: CbctrlwWO) -> Self {
52        variant as u8 != 0
53    }
54}
55#[doc = "Field `CBCTRL` writer - Channel buffer control"]
56pub type CBCTRL_W<'a, REG> = crate::BitWriter<'a, REG, CbctrlwWO>;
57impl<'a, REG> CBCTRL_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60{
61    #[doc = "CxEN, CxCEN and CxOCTRL bits buffer disable"]
62    #[inline(always)]
63    pub fn disable(self) -> &'a mut crate::W<REG> {
64        self.variant(CbctrlwWO::Disable)
65    }
66    #[doc = "CxEN, CxCEN and CxOCTRL bits buffer enable"]
67    #[inline(always)]
68    pub fn enable(self) -> &'a mut crate::W<REG> {
69        self.variant(CbctrlwWO::Enable)
70    }
71}
72#[doc = "Channel control bit refresh select\n\nValue on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum CCFS_A {
75    #[doc = "0: Control bits are updated by setting the HALL bit"]
76    Hall = 0,
77    #[doc = "1: Control bits are updated by setting the HALL bit or a rising edge on TRGIN"]
78    Trgin = 1,
79}
80impl From<CCFS_A> for bool {
81    #[inline(always)]
82    fn from(variant: CCFS_A) -> Self {
83        variant as u8 != 0
84    }
85}
86#[doc = "Field `CCFS` reader - Channel control bit refresh select"]
87pub type CCFS_R = crate::BitReader<CCFS_A>;
88impl CCFS_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> CCFS_A {
92        match self.bits {
93            false => CCFS_A::Hall,
94            true => CCFS_A::Trgin,
95        }
96    }
97    #[doc = "Control bits are updated by setting the HALL bit"]
98    #[inline(always)]
99    pub fn is_hall(&self) -> bool {
100        *self == CCFS_A::Hall
101    }
102    #[doc = "Control bits are updated by setting the HALL bit or a rising edge on TRGIN"]
103    #[inline(always)]
104    pub fn is_trgin(&self) -> bool {
105        *self == CCFS_A::Trgin
106    }
107}
108#[doc = "Field `CCFS` writer - Channel control bit refresh select"]
109pub type CCFS_W<'a, REG> = crate::BitWriter<'a, REG, CCFS_A>;
110impl<'a, REG> CCFS_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113{
114    #[doc = "Control bits are updated by setting the HALL bit"]
115    #[inline(always)]
116    pub fn hall(self) -> &'a mut crate::W<REG> {
117        self.variant(CCFS_A::Hall)
118    }
119    #[doc = "Control bits are updated by setting the HALL bit or a rising edge on TRGIN"]
120    #[inline(always)]
121    pub fn trgin(self) -> &'a mut crate::W<REG> {
122        self.variant(CCFS_A::Trgin)
123    }
124}
125#[doc = "DMA request source\n\nValue on reset: 0"]
126#[derive(Clone, Copy, Debug, PartialEq, Eq)]
127pub enum DRS_A {
128    #[doc = "0: Capture/compare event"]
129    CaptureCompare = 0,
130    #[doc = "1: Overflow event"]
131    Overflow = 1,
132}
133impl From<DRS_A> for bool {
134    #[inline(always)]
135    fn from(variant: DRS_A) -> Self {
136        variant as u8 != 0
137    }
138}
139#[doc = "Field `DRS` reader - DMA request source"]
140pub type DRS_R = crate::BitReader<DRS_A>;
141impl DRS_R {
142    #[doc = "Get enumerated values variant"]
143    #[inline(always)]
144    pub const fn variant(&self) -> DRS_A {
145        match self.bits {
146            false => DRS_A::CaptureCompare,
147            true => DRS_A::Overflow,
148        }
149    }
150    #[doc = "Capture/compare event"]
151    #[inline(always)]
152    pub fn is_capture_compare(&self) -> bool {
153        *self == DRS_A::CaptureCompare
154    }
155    #[doc = "Overflow event"]
156    #[inline(always)]
157    pub fn is_overflow(&self) -> bool {
158        *self == DRS_A::Overflow
159    }
160}
161#[doc = "Field `DRS` writer - DMA request source"]
162pub type DRS_W<'a, REG> = crate::BitWriter<'a, REG, DRS_A>;
163impl<'a, REG> DRS_W<'a, REG>
164where
165    REG: crate::Writable + crate::RegisterSpec,
166{
167    #[doc = "Capture/compare event"]
168    #[inline(always)]
169    pub fn capture_compare(self) -> &'a mut crate::W<REG> {
170        self.variant(DRS_A::CaptureCompare)
171    }
172    #[doc = "Overflow event"]
173    #[inline(always)]
174    pub fn overflow(self) -> &'a mut crate::W<REG> {
175        self.variant(DRS_A::Overflow)
176    }
177}
178#[doc = "Primary TMR output selection\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq, Eq)]
180#[repr(u8)]
181pub enum PTOS_A {
182    #[doc = "0: Reset"]
183    Reset = 0,
184    #[doc = "1: Enable"]
185    Enable = 1,
186    #[doc = "2: Update"]
187    Update = 2,
188    #[doc = "3: Compare pulse"]
189    ComparePulse = 3,
190    #[doc = "4: C1ORAW signal"]
191    C1oraw = 4,
192    #[doc = "5: C2ORAW signal"]
193    C2oraw = 5,
194    #[doc = "6: C3ORAW signal"]
195    C3oraw = 6,
196    #[doc = "7: C4ORAW signal"]
197    C4oraw = 7,
198}
199impl From<PTOS_A> for u8 {
200    #[inline(always)]
201    fn from(variant: PTOS_A) -> Self {
202        variant as _
203    }
204}
205impl crate::FieldSpec for PTOS_A {
206    type Ux = u8;
207}
208impl crate::IsEnum for PTOS_A {}
209#[doc = "Field `PTOS` reader - Primary TMR output selection"]
210pub type PTOS_R = crate::FieldReader<PTOS_A>;
211impl PTOS_R {
212    #[doc = "Get enumerated values variant"]
213    #[inline(always)]
214    pub const fn variant(&self) -> PTOS_A {
215        match self.bits {
216            0 => PTOS_A::Reset,
217            1 => PTOS_A::Enable,
218            2 => PTOS_A::Update,
219            3 => PTOS_A::ComparePulse,
220            4 => PTOS_A::C1oraw,
221            5 => PTOS_A::C2oraw,
222            6 => PTOS_A::C3oraw,
223            7 => PTOS_A::C4oraw,
224            _ => unreachable!(),
225        }
226    }
227    #[doc = "Reset"]
228    #[inline(always)]
229    pub fn is_reset(&self) -> bool {
230        *self == PTOS_A::Reset
231    }
232    #[doc = "Enable"]
233    #[inline(always)]
234    pub fn is_enable(&self) -> bool {
235        *self == PTOS_A::Enable
236    }
237    #[doc = "Update"]
238    #[inline(always)]
239    pub fn is_update(&self) -> bool {
240        *self == PTOS_A::Update
241    }
242    #[doc = "Compare pulse"]
243    #[inline(always)]
244    pub fn is_compare_pulse(&self) -> bool {
245        *self == PTOS_A::ComparePulse
246    }
247    #[doc = "C1ORAW signal"]
248    #[inline(always)]
249    pub fn is_c1oraw(&self) -> bool {
250        *self == PTOS_A::C1oraw
251    }
252    #[doc = "C2ORAW signal"]
253    #[inline(always)]
254    pub fn is_c2oraw(&self) -> bool {
255        *self == PTOS_A::C2oraw
256    }
257    #[doc = "C3ORAW signal"]
258    #[inline(always)]
259    pub fn is_c3oraw(&self) -> bool {
260        *self == PTOS_A::C3oraw
261    }
262    #[doc = "C4ORAW signal"]
263    #[inline(always)]
264    pub fn is_c4oraw(&self) -> bool {
265        *self == PTOS_A::C4oraw
266    }
267}
268#[doc = "Field `PTOS` writer - Primary TMR output selection"]
269pub type PTOS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PTOS_A, crate::Safe>;
270impl<'a, REG> PTOS_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273    REG::Ux: From<u8>,
274{
275    #[doc = "Reset"]
276    #[inline(always)]
277    pub fn reset(self) -> &'a mut crate::W<REG> {
278        self.variant(PTOS_A::Reset)
279    }
280    #[doc = "Enable"]
281    #[inline(always)]
282    pub fn enable(self) -> &'a mut crate::W<REG> {
283        self.variant(PTOS_A::Enable)
284    }
285    #[doc = "Update"]
286    #[inline(always)]
287    pub fn update(self) -> &'a mut crate::W<REG> {
288        self.variant(PTOS_A::Update)
289    }
290    #[doc = "Compare pulse"]
291    #[inline(always)]
292    pub fn compare_pulse(self) -> &'a mut crate::W<REG> {
293        self.variant(PTOS_A::ComparePulse)
294    }
295    #[doc = "C1ORAW signal"]
296    #[inline(always)]
297    pub fn c1oraw(self) -> &'a mut crate::W<REG> {
298        self.variant(PTOS_A::C1oraw)
299    }
300    #[doc = "C2ORAW signal"]
301    #[inline(always)]
302    pub fn c2oraw(self) -> &'a mut crate::W<REG> {
303        self.variant(PTOS_A::C2oraw)
304    }
305    #[doc = "C3ORAW signal"]
306    #[inline(always)]
307    pub fn c3oraw(self) -> &'a mut crate::W<REG> {
308        self.variant(PTOS_A::C3oraw)
309    }
310    #[doc = "C4ORAW signal"]
311    #[inline(always)]
312    pub fn c4oraw(self) -> &'a mut crate::W<REG> {
313        self.variant(PTOS_A::C4oraw)
314    }
315}
316#[doc = "C1IN selection\n\nValue on reset: 0"]
317#[derive(Clone, Copy, Debug, PartialEq, Eq)]
318pub enum C1INSEL_A {
319    #[doc = "0: CH1 pin is connected to C1IRAW input"]
320    Ch1 = 0,
321    #[doc = "1: The XOR result of CH1, CH2 and CH3 pins is connected to C1IRAW input"]
322    Xor = 1,
323}
324impl From<C1INSEL_A> for bool {
325    #[inline(always)]
326    fn from(variant: C1INSEL_A) -> Self {
327        variant as u8 != 0
328    }
329}
330#[doc = "Field `C1INSEL` reader - C1IN selection"]
331pub type C1INSEL_R = crate::BitReader<C1INSEL_A>;
332impl C1INSEL_R {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> C1INSEL_A {
336        match self.bits {
337            false => C1INSEL_A::Ch1,
338            true => C1INSEL_A::Xor,
339        }
340    }
341    #[doc = "CH1 pin is connected to C1IRAW input"]
342    #[inline(always)]
343    pub fn is_ch1(&self) -> bool {
344        *self == C1INSEL_A::Ch1
345    }
346    #[doc = "The XOR result of CH1, CH2 and CH3 pins is connected to C1IRAW input"]
347    #[inline(always)]
348    pub fn is_xor(&self) -> bool {
349        *self == C1INSEL_A::Xor
350    }
351}
352#[doc = "Field `C1INSEL` writer - C1IN selection"]
353pub type C1INSEL_W<'a, REG> = crate::BitWriter<'a, REG, C1INSEL_A>;
354impl<'a, REG> C1INSEL_W<'a, REG>
355where
356    REG: crate::Writable + crate::RegisterSpec,
357{
358    #[doc = "CH1 pin is connected to C1IRAW input"]
359    #[inline(always)]
360    pub fn ch1(self) -> &'a mut crate::W<REG> {
361        self.variant(C1INSEL_A::Ch1)
362    }
363    #[doc = "The XOR result of CH1, CH2 and CH3 pins is connected to C1IRAW input"]
364    #[inline(always)]
365    pub fn xor(self) -> &'a mut crate::W<REG> {
366        self.variant(C1INSEL_A::Xor)
367    }
368}
369#[doc = "Channel %s idle output state\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq, Eq)]
371pub enum C1IOS_A {
372    #[doc = "0: After dead-time state is low"]
373    Low = 0,
374    #[doc = "1: After dead-time state is high"]
375    High = 1,
376}
377impl From<C1IOS_A> for bool {
378    #[inline(always)]
379    fn from(variant: C1IOS_A) -> Self {
380        variant as u8 != 0
381    }
382}
383#[doc = "Field `CIOS(1-4)` reader - Channel %s idle output state"]
384pub type CIOS_R = crate::BitReader<C1IOS_A>;
385impl CIOS_R {
386    #[doc = "Get enumerated values variant"]
387    #[inline(always)]
388    pub const fn variant(&self) -> C1IOS_A {
389        match self.bits {
390            false => C1IOS_A::Low,
391            true => C1IOS_A::High,
392        }
393    }
394    #[doc = "After dead-time state is low"]
395    #[inline(always)]
396    pub fn is_low(&self) -> bool {
397        *self == C1IOS_A::Low
398    }
399    #[doc = "After dead-time state is high"]
400    #[inline(always)]
401    pub fn is_high(&self) -> bool {
402        *self == C1IOS_A::High
403    }
404}
405#[doc = "Field `CIOS(1-4)` writer - Channel %s idle output state"]
406pub type CIOS_W<'a, REG> = crate::BitWriter<'a, REG, C1IOS_A>;
407impl<'a, REG> CIOS_W<'a, REG>
408where
409    REG: crate::Writable + crate::RegisterSpec,
410{
411    #[doc = "After dead-time state is low"]
412    #[inline(always)]
413    pub fn low(self) -> &'a mut crate::W<REG> {
414        self.variant(C1IOS_A::Low)
415    }
416    #[doc = "After dead-time state is high"]
417    #[inline(always)]
418    pub fn high(self) -> &'a mut crate::W<REG> {
419        self.variant(C1IOS_A::High)
420    }
421}
422#[doc = "Channel %s complementary idle output state\n\nValue on reset: 0"]
423#[derive(Clone, Copy, Debug, PartialEq, Eq)]
424pub enum C1CIOS_A {
425    #[doc = "0: After dead-time state is low"]
426    Low = 0,
427    #[doc = "1: After dead-time state is high"]
428    High = 1,
429}
430impl From<C1CIOS_A> for bool {
431    #[inline(always)]
432    fn from(variant: C1CIOS_A) -> Self {
433        variant as u8 != 0
434    }
435}
436#[doc = "Field `CCIOS(1-3)` reader - Channel %s complementary idle output state"]
437pub type CCIOS_R = crate::BitReader<C1CIOS_A>;
438impl CCIOS_R {
439    #[doc = "Get enumerated values variant"]
440    #[inline(always)]
441    pub const fn variant(&self) -> C1CIOS_A {
442        match self.bits {
443            false => C1CIOS_A::Low,
444            true => C1CIOS_A::High,
445        }
446    }
447    #[doc = "After dead-time state is low"]
448    #[inline(always)]
449    pub fn is_low(&self) -> bool {
450        *self == C1CIOS_A::Low
451    }
452    #[doc = "After dead-time state is high"]
453    #[inline(always)]
454    pub fn is_high(&self) -> bool {
455        *self == C1CIOS_A::High
456    }
457}
458#[doc = "Field `CCIOS(1-3)` writer - Channel %s complementary idle output state"]
459pub type CCIOS_W<'a, REG> = crate::BitWriter<'a, REG, C1CIOS_A>;
460impl<'a, REG> CCIOS_W<'a, REG>
461where
462    REG: crate::Writable + crate::RegisterSpec,
463{
464    #[doc = "After dead-time state is low"]
465    #[inline(always)]
466    pub fn low(self) -> &'a mut crate::W<REG> {
467        self.variant(C1CIOS_A::Low)
468    }
469    #[doc = "After dead-time state is high"]
470    #[inline(always)]
471    pub fn high(self) -> &'a mut crate::W<REG> {
472        self.variant(C1CIOS_A::High)
473    }
474}
475impl R {
476    #[doc = "Bit 0 - Channel buffer control"]
477    #[inline(always)]
478    pub fn cbctrl(&self) -> CBCTRL_R {
479        CBCTRL_R::new((self.bits & 1) != 0)
480    }
481    #[doc = "Bit 2 - Channel control bit refresh select"]
482    #[inline(always)]
483    pub fn ccfs(&self) -> CCFS_R {
484        CCFS_R::new(((self.bits >> 2) & 1) != 0)
485    }
486    #[doc = "Bit 3 - DMA request source"]
487    #[inline(always)]
488    pub fn drs(&self) -> DRS_R {
489        DRS_R::new(((self.bits >> 3) & 1) != 0)
490    }
491    #[doc = "Bits 4:6 - Primary TMR output selection"]
492    #[inline(always)]
493    pub fn ptos(&self) -> PTOS_R {
494        PTOS_R::new(((self.bits >> 4) & 7) as u8)
495    }
496    #[doc = "Bit 7 - C1IN selection"]
497    #[inline(always)]
498    pub fn c1insel(&self) -> C1INSEL_R {
499        C1INSEL_R::new(((self.bits >> 7) & 1) != 0)
500    }
501    #[doc = "Channel (1-4) idle output state"]
502    #[doc = ""]
503    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1IOS` field.</div>"]
504    #[inline(always)]
505    pub fn cios(&self, n: u8) -> CIOS_R {
506        #[allow(clippy::no_effect)]
507        [(); 4][n as usize];
508        CIOS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0)
509    }
510    #[doc = "Iterator for array of:"]
511    #[doc = "Channel (1-4) idle output state"]
512    #[inline(always)]
513    pub fn cios_iter(&self) -> impl Iterator<Item = CIOS_R> + '_ {
514        (0..4).map(move |n| CIOS_R::new(((self.bits >> (n * 2 + 8)) & 1) != 0))
515    }
516    #[doc = "Bit 8 - Channel 1 idle output state"]
517    #[inline(always)]
518    pub fn c1ios(&self) -> CIOS_R {
519        CIOS_R::new(((self.bits >> 8) & 1) != 0)
520    }
521    #[doc = "Bit 10 - Channel 2 idle output state"]
522    #[inline(always)]
523    pub fn c2ios(&self) -> CIOS_R {
524        CIOS_R::new(((self.bits >> 10) & 1) != 0)
525    }
526    #[doc = "Bit 12 - Channel 3 idle output state"]
527    #[inline(always)]
528    pub fn c3ios(&self) -> CIOS_R {
529        CIOS_R::new(((self.bits >> 12) & 1) != 0)
530    }
531    #[doc = "Bit 14 - Channel 4 idle output state"]
532    #[inline(always)]
533    pub fn c4ios(&self) -> CIOS_R {
534        CIOS_R::new(((self.bits >> 14) & 1) != 0)
535    }
536    #[doc = "Channel (1-3) complementary idle output state"]
537    #[doc = ""]
538    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1CIOS` field.</div>"]
539    #[inline(always)]
540    pub fn ccios(&self, n: u8) -> CCIOS_R {
541        #[allow(clippy::no_effect)]
542        [(); 3][n as usize];
543        CCIOS_R::new(((self.bits >> (n * 2 + 9)) & 1) != 0)
544    }
545    #[doc = "Iterator for array of:"]
546    #[doc = "Channel (1-3) complementary idle output state"]
547    #[inline(always)]
548    pub fn ccios_iter(&self) -> impl Iterator<Item = CCIOS_R> + '_ {
549        (0..3).map(move |n| CCIOS_R::new(((self.bits >> (n * 2 + 9)) & 1) != 0))
550    }
551    #[doc = "Bit 9 - Channel 1 complementary idle output state"]
552    #[inline(always)]
553    pub fn c1cios(&self) -> CCIOS_R {
554        CCIOS_R::new(((self.bits >> 9) & 1) != 0)
555    }
556    #[doc = "Bit 11 - Channel 2 complementary idle output state"]
557    #[inline(always)]
558    pub fn c2cios(&self) -> CCIOS_R {
559        CCIOS_R::new(((self.bits >> 11) & 1) != 0)
560    }
561    #[doc = "Bit 13 - Channel 3 complementary idle output state"]
562    #[inline(always)]
563    pub fn c3cios(&self) -> CCIOS_R {
564        CCIOS_R::new(((self.bits >> 13) & 1) != 0)
565    }
566}
567impl core::fmt::Debug for R {
568    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
569        f.debug_struct("CTRL2")
570            .field("c1ios", &self.c1ios())
571            .field("c2ios", &self.c2ios())
572            .field("c3ios", &self.c3ios())
573            .field("c4ios", &self.c4ios())
574            .field("c1cios", &self.c1cios())
575            .field("c2cios", &self.c2cios())
576            .field("c3cios", &self.c3cios())
577            .field("c1insel", &self.c1insel())
578            .field("ptos", &self.ptos())
579            .field("drs", &self.drs())
580            .field("ccfs", &self.ccfs())
581            .field("cbctrl", &self.cbctrl())
582            .finish()
583    }
584}
585impl W {
586    #[doc = "Bit 0 - Channel buffer control"]
587    #[inline(always)]
588    pub fn cbctrl(&mut self) -> CBCTRL_W<'_, CTRL2_SPEC> {
589        CBCTRL_W::new(self, 0)
590    }
591    #[doc = "Bit 2 - Channel control bit refresh select"]
592    #[inline(always)]
593    pub fn ccfs(&mut self) -> CCFS_W<'_, CTRL2_SPEC> {
594        CCFS_W::new(self, 2)
595    }
596    #[doc = "Bit 3 - DMA request source"]
597    #[inline(always)]
598    pub fn drs(&mut self) -> DRS_W<'_, CTRL2_SPEC> {
599        DRS_W::new(self, 3)
600    }
601    #[doc = "Bits 4:6 - Primary TMR output selection"]
602    #[inline(always)]
603    pub fn ptos(&mut self) -> PTOS_W<'_, CTRL2_SPEC> {
604        PTOS_W::new(self, 4)
605    }
606    #[doc = "Bit 7 - C1IN selection"]
607    #[inline(always)]
608    pub fn c1insel(&mut self) -> C1INSEL_W<'_, CTRL2_SPEC> {
609        C1INSEL_W::new(self, 7)
610    }
611    #[doc = "Channel (1-4) idle output state"]
612    #[doc = ""]
613    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1IOS` field.</div>"]
614    #[inline(always)]
615    pub fn cios(&mut self, n: u8) -> CIOS_W<'_, CTRL2_SPEC> {
616        #[allow(clippy::no_effect)]
617        [(); 4][n as usize];
618        CIOS_W::new(self, n * 2 + 8)
619    }
620    #[doc = "Bit 8 - Channel 1 idle output state"]
621    #[inline(always)]
622    pub fn c1ios(&mut self) -> CIOS_W<'_, CTRL2_SPEC> {
623        CIOS_W::new(self, 8)
624    }
625    #[doc = "Bit 10 - Channel 2 idle output state"]
626    #[inline(always)]
627    pub fn c2ios(&mut self) -> CIOS_W<'_, CTRL2_SPEC> {
628        CIOS_W::new(self, 10)
629    }
630    #[doc = "Bit 12 - Channel 3 idle output state"]
631    #[inline(always)]
632    pub fn c3ios(&mut self) -> CIOS_W<'_, CTRL2_SPEC> {
633        CIOS_W::new(self, 12)
634    }
635    #[doc = "Bit 14 - Channel 4 idle output state"]
636    #[inline(always)]
637    pub fn c4ios(&mut self) -> CIOS_W<'_, CTRL2_SPEC> {
638        CIOS_W::new(self, 14)
639    }
640    #[doc = "Channel (1-3) complementary idle output state"]
641    #[doc = ""]
642    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C1CIOS` field.</div>"]
643    #[inline(always)]
644    pub fn ccios(&mut self, n: u8) -> CCIOS_W<'_, CTRL2_SPEC> {
645        #[allow(clippy::no_effect)]
646        [(); 3][n as usize];
647        CCIOS_W::new(self, n * 2 + 9)
648    }
649    #[doc = "Bit 9 - Channel 1 complementary idle output state"]
650    #[inline(always)]
651    pub fn c1cios(&mut self) -> CCIOS_W<'_, CTRL2_SPEC> {
652        CCIOS_W::new(self, 9)
653    }
654    #[doc = "Bit 11 - Channel 2 complementary idle output state"]
655    #[inline(always)]
656    pub fn c2cios(&mut self) -> CCIOS_W<'_, CTRL2_SPEC> {
657        CCIOS_W::new(self, 11)
658    }
659    #[doc = "Bit 13 - Channel 3 complementary idle output state"]
660    #[inline(always)]
661    pub fn c3cios(&mut self) -> CCIOS_W<'_, CTRL2_SPEC> {
662        CCIOS_W::new(self, 13)
663    }
664}
665#[doc = "Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
666pub struct CTRL2_SPEC;
667impl crate::RegisterSpec for CTRL2_SPEC {
668    type Ux = u32;
669}
670#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
671impl crate::Readable for CTRL2_SPEC {}
672#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
673impl crate::Writable for CTRL2_SPEC {
674    type Safety = crate::Unsafe;
675}
676#[doc = "`reset()` method sets CTRL2 to value 0"]
677impl crate::Resettable for CTRL2_SPEC {}
at32f4xx_pac/at32f421/tmr1/ctrl2.rs

at32f4xx_pac/at32f421/tmr1/
ctrl2.rs
