at32f4xx_pac/at32a403a/adc2/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "A/D converter enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Adcenr {
8    #[doc = "0: ADC is disabled"]
9    Disabled = 0,
10    #[doc = "1: ADC is enabled"]
11    Enabled = 1,
12}
13impl From<Adcenr> for bool {
14    #[inline(always)]
15    fn from(variant: Adcenr) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `ADCEN` reader - A/D converter enable"]
20pub type ADCEN_R = crate::BitReader<Adcenr>;
21impl ADCEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Adcenr {
25        match self.bits {
26            false => Adcenr::Disabled,
27            true => Adcenr::Enabled,
28        }
29    }
30    #[doc = "ADC is disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Adcenr::Disabled
34    }
35    #[doc = "ADC is enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Adcenr::Enabled
39    }
40}
41#[doc = "A/D converter enable\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum AdcenwWO {
44    #[doc = "0: ADC disable"]
45    Disable = 0,
46    #[doc = "1: ADC enable"]
47    Enable = 1,
48}
49impl From<AdcenwWO> for bool {
50    #[inline(always)]
51    fn from(variant: AdcenwWO) -> Self {
52        variant as u8 != 0
53    }
54}
55#[doc = "Field `ADCEN` writer - A/D converter enable"]
56pub type ADCEN_W<'a, REG> = crate::BitWriter<'a, REG, AdcenwWO>;
57impl<'a, REG> ADCEN_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60{
61    #[doc = "ADC disable"]
62    #[inline(always)]
63    pub fn disable(self) -> &'a mut crate::W<REG> {
64        self.variant(AdcenwWO::Disable)
65    }
66    #[doc = "ADC enable"]
67    #[inline(always)]
68    pub fn enable(self) -> &'a mut crate::W<REG> {
69        self.variant(AdcenwWO::Enable)
70    }
71}
72#[doc = "Repeat mode enable\n\nValue on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum Rpenr {
75    #[doc = "0: Repetition mode is disabled"]
76    Disabled = 0,
77    #[doc = "1: Repetition mode is enabled"]
78    Enabled = 1,
79}
80impl From<Rpenr> for bool {
81    #[inline(always)]
82    fn from(variant: Rpenr) -> Self {
83        variant as u8 != 0
84    }
85}
86#[doc = "Field `RPEN` reader - Repeat mode enable"]
87pub type RPEN_R = crate::BitReader<Rpenr>;
88impl RPEN_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Rpenr {
92        match self.bits {
93            false => Rpenr::Disabled,
94            true => Rpenr::Enabled,
95        }
96    }
97    #[doc = "Repetition mode is disabled"]
98    #[inline(always)]
99    pub fn is_disabled(&self) -> bool {
100        *self == Rpenr::Disabled
101    }
102    #[doc = "Repetition mode is enabled"]
103    #[inline(always)]
104    pub fn is_enabled(&self) -> bool {
105        *self == Rpenr::Enabled
106    }
107}
108#[doc = "Repeat mode enable\n\nValue on reset: 0"]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum RpenwWO {
111    #[doc = "0: Repetition mode disable"]
112    Disable = 0,
113    #[doc = "1: Repetition mode enable"]
114    Enable = 1,
115}
116impl From<RpenwWO> for bool {
117    #[inline(always)]
118    fn from(variant: RpenwWO) -> Self {
119        variant as u8 != 0
120    }
121}
122#[doc = "Field `RPEN` writer - Repeat mode enable"]
123pub type RPEN_W<'a, REG> = crate::BitWriter<'a, REG, RpenwWO>;
124impl<'a, REG> RPEN_W<'a, REG>
125where
126    REG: crate::Writable + crate::RegisterSpec,
127{
128    #[doc = "Repetition mode disable"]
129    #[inline(always)]
130    pub fn disable(self) -> &'a mut crate::W<REG> {
131        self.variant(RpenwWO::Disable)
132    }
133    #[doc = "Repetition mode enable"]
134    #[inline(always)]
135    pub fn enable(self) -> &'a mut crate::W<REG> {
136        self.variant(RpenwWO::Enable)
137    }
138}
139#[doc = "A/D Calibration\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum Adcalr {
142    #[doc = "0: Calibration completed"]
143    Completed = 0,
144    #[doc = "1: Calibration is in process"]
145    InProgress = 1,
146}
147impl From<Adcalr> for bool {
148    #[inline(always)]
149    fn from(variant: Adcalr) -> Self {
150        variant as u8 != 0
151    }
152}
153#[doc = "Field `ADCAL` reader - A/D Calibration"]
154pub type ADCAL_R = crate::BitReader<Adcalr>;
155impl ADCAL_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub const fn variant(&self) -> Adcalr {
159        match self.bits {
160            false => Adcalr::Completed,
161            true => Adcalr::InProgress,
162        }
163    }
164    #[doc = "Calibration completed"]
165    #[inline(always)]
166    pub fn is_completed(&self) -> bool {
167        *self == Adcalr::Completed
168    }
169    #[doc = "Calibration is in process"]
170    #[inline(always)]
171    pub fn is_in_progress(&self) -> bool {
172        *self == Adcalr::InProgress
173    }
174}
175#[doc = "A/D Calibration\n\nValue on reset: 0"]
176#[derive(Clone, Copy, Debug, PartialEq, Eq)]
177pub enum AdcalwWO {
178    #[doc = "1: Enable calibration"]
179    Calibrate = 1,
180}
181impl From<AdcalwWO> for bool {
182    #[inline(always)]
183    fn from(variant: AdcalwWO) -> Self {
184        variant as u8 != 0
185    }
186}
187#[doc = "Field `ADCAL` writer - A/D Calibration"]
188pub type ADCAL_W<'a, REG> = crate::BitWriter<'a, REG, AdcalwWO>;
189impl<'a, REG> ADCAL_W<'a, REG>
190where
191    REG: crate::Writable + crate::RegisterSpec,
192{
193    #[doc = "Enable calibration"]
194    #[inline(always)]
195    pub fn calibrate(self) -> &'a mut crate::W<REG> {
196        self.variant(AdcalwWO::Calibrate)
197    }
198}
199#[doc = "initialize A/D calibration\n\nValue on reset: 0"]
200#[derive(Clone, Copy, Debug, PartialEq, Eq)]
201pub enum Adcalinitr {
202    #[doc = "0: Initialization completed"]
203    Completed = 0,
204    #[doc = "1: Initialization is in process"]
205    InProgress = 1,
206}
207impl From<Adcalinitr> for bool {
208    #[inline(always)]
209    fn from(variant: Adcalinitr) -> Self {
210        variant as u8 != 0
211    }
212}
213#[doc = "Field `ADCALINIT` reader - initialize A/D calibration"]
214pub type ADCALINIT_R = crate::BitReader<Adcalinitr>;
215impl ADCALINIT_R {
216    #[doc = "Get enumerated values variant"]
217    #[inline(always)]
218    pub const fn variant(&self) -> Adcalinitr {
219        match self.bits {
220            false => Adcalinitr::Completed,
221            true => Adcalinitr::InProgress,
222        }
223    }
224    #[doc = "Initialization completed"]
225    #[inline(always)]
226    pub fn is_completed(&self) -> bool {
227        *self == Adcalinitr::Completed
228    }
229    #[doc = "Initialization is in process"]
230    #[inline(always)]
231    pub fn is_in_progress(&self) -> bool {
232        *self == Adcalinitr::InProgress
233    }
234}
235#[doc = "initialize A/D calibration\n\nValue on reset: 0"]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237pub enum AdcalinitwWO {
238    #[doc = "1: Enable initialization"]
239    Init = 1,
240}
241impl From<AdcalinitwWO> for bool {
242    #[inline(always)]
243    fn from(variant: AdcalinitwWO) -> Self {
244        variant as u8 != 0
245    }
246}
247#[doc = "Field `ADCALINIT` writer - initialize A/D calibration"]
248pub type ADCALINIT_W<'a, REG> = crate::BitWriter<'a, REG, AdcalinitwWO>;
249impl<'a, REG> ADCALINIT_W<'a, REG>
250where
251    REG: crate::Writable + crate::RegisterSpec,
252{
253    #[doc = "Enable initialization"]
254    #[inline(always)]
255    pub fn init(self) -> &'a mut crate::W<REG> {
256        self.variant(AdcalinitwWO::Init)
257    }
258}
259#[doc = "Data alignment\n\nValue on reset: 0"]
260#[derive(Clone, Copy, Debug, PartialEq, Eq)]
261pub enum DTALIGN_A {
262    #[doc = "0: Right alignment"]
263    Right = 0,
264    #[doc = "1: Left alignment"]
265    Left = 1,
266}
267impl From<DTALIGN_A> for bool {
268    #[inline(always)]
269    fn from(variant: DTALIGN_A) -> Self {
270        variant as u8 != 0
271    }
272}
273#[doc = "Field `DTALIGN` reader - Data alignment"]
274pub type DTALIGN_R = crate::BitReader<DTALIGN_A>;
275impl DTALIGN_R {
276    #[doc = "Get enumerated values variant"]
277    #[inline(always)]
278    pub const fn variant(&self) -> DTALIGN_A {
279        match self.bits {
280            false => DTALIGN_A::Right,
281            true => DTALIGN_A::Left,
282        }
283    }
284    #[doc = "Right alignment"]
285    #[inline(always)]
286    pub fn is_right(&self) -> bool {
287        *self == DTALIGN_A::Right
288    }
289    #[doc = "Left alignment"]
290    #[inline(always)]
291    pub fn is_left(&self) -> bool {
292        *self == DTALIGN_A::Left
293    }
294}
295#[doc = "Field `DTALIGN` writer - Data alignment"]
296pub type DTALIGN_W<'a, REG> = crate::BitWriter<'a, REG, DTALIGN_A>;
297impl<'a, REG> DTALIGN_W<'a, REG>
298where
299    REG: crate::Writable + crate::RegisterSpec,
300{
301    #[doc = "Right alignment"]
302    #[inline(always)]
303    pub fn right(self) -> &'a mut crate::W<REG> {
304        self.variant(DTALIGN_A::Right)
305    }
306    #[doc = "Left alignment"]
307    #[inline(always)]
308    pub fn left(self) -> &'a mut crate::W<REG> {
309        self.variant(DTALIGN_A::Left)
310    }
311}
312#[doc = "Field `PCTESEL_L` reader - Low bit of trigger event select for preempted channels conversion"]
313pub type PCTESEL_L_R = crate::FieldReader;
314#[doc = "Field `PCTESEL_L` writer - Low bit of trigger event select for preempted channels conversion"]
315pub type PCTESEL_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
316#[doc = "Field `PCTEN` reader - Trigger mode enable for preempted channels conversion"]
317pub type PCTEN_R = crate::BitReader;
318#[doc = "Field `PCTEN` writer - Trigger mode enable for preempted channels conversion"]
319pub type PCTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
320#[doc = "Field `OCTESEL_L` reader - Low bit of trigger event select for ordinary channels conversion"]
321pub type OCTESEL_L_R = crate::FieldReader;
322#[doc = "Field `OCTESEL_L` writer - Low bit of trigger event select for ordinary channels conversion"]
323pub type OCTESEL_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
324#[doc = "Field `OCTEN` reader - Trigger mode enable for ordinary channels conversion"]
325pub type OCTEN_R = crate::BitReader;
326#[doc = "Field `OCTEN` writer - Trigger mode enable for ordinary channels conversion"]
327pub type OCTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
328#[doc = "Conversion trigger by software of preempted channels\n\nValue on reset: 0"]
329#[derive(Clone, Copy, Debug, PartialEq, Eq)]
330pub enum PCSWTRG_A {
331    #[doc = "0: Conversion of ordinary channels not triggered"]
332    NotTriggered = 0,
333    #[doc = "1: Conversion of ordinary channels triggered"]
334    Triggered = 1,
335}
336impl From<PCSWTRG_A> for bool {
337    #[inline(always)]
338    fn from(variant: PCSWTRG_A) -> Self {
339        variant as u8 != 0
340    }
341}
342#[doc = "Field `PCSWTRG` reader - Conversion trigger by software of preempted channels"]
343pub type PCSWTRG_R = crate::BitReader<PCSWTRG_A>;
344impl PCSWTRG_R {
345    #[doc = "Get enumerated values variant"]
346    #[inline(always)]
347    pub const fn variant(&self) -> PCSWTRG_A {
348        match self.bits {
349            false => PCSWTRG_A::NotTriggered,
350            true => PCSWTRG_A::Triggered,
351        }
352    }
353    #[doc = "Conversion of ordinary channels not triggered"]
354    #[inline(always)]
355    pub fn is_not_triggered(&self) -> bool {
356        *self == PCSWTRG_A::NotTriggered
357    }
358    #[doc = "Conversion of ordinary channels triggered"]
359    #[inline(always)]
360    pub fn is_triggered(&self) -> bool {
361        *self == PCSWTRG_A::Triggered
362    }
363}
364#[doc = "Field `PCSWTRG` writer - Conversion trigger by software of preempted channels"]
365pub type PCSWTRG_W<'a, REG> = crate::BitWriter<'a, REG, PCSWTRG_A>;
366impl<'a, REG> PCSWTRG_W<'a, REG>
367where
368    REG: crate::Writable + crate::RegisterSpec,
369{
370    #[doc = "Conversion of ordinary channels not triggered"]
371    #[inline(always)]
372    pub fn not_triggered(self) -> &'a mut crate::W<REG> {
373        self.variant(PCSWTRG_A::NotTriggered)
374    }
375    #[doc = "Conversion of ordinary channels triggered"]
376    #[inline(always)]
377    pub fn triggered(self) -> &'a mut crate::W<REG> {
378        self.variant(PCSWTRG_A::Triggered)
379    }
380}
381#[doc = "Field `OCSWTRG` reader - Conversion trigger by software of ordinary channels"]
382pub use PCSWTRG_R as OCSWTRG_R;
383#[doc = "Field `OCSWTRG` writer - Conversion trigger by software of ordinary channels"]
384pub use PCSWTRG_W as OCSWTRG_W;
385#[doc = "Field `PCTESEL_H` reader - High bit of trigger event select for preempted channels conversion"]
386pub type PCTESEL_H_R = crate::BitReader;
387#[doc = "Field `PCTESEL_H` writer - High bit of trigger event select for preempted channels conversion"]
388pub type PCTESEL_H_W<'a, REG> = crate::BitWriter<'a, REG>;
389#[doc = "Field `OCTESEL_H` reader - High bit of trigger event select for ordinary channels conversion"]
390pub type OCTESEL_H_R = crate::BitReader;
391#[doc = "Field `OCTESEL_H` writer - High bit of trigger event select for ordinary channels conversion"]
392pub type OCTESEL_H_W<'a, REG> = crate::BitWriter<'a, REG>;
393impl R {
394    #[doc = "Bit 0 - A/D converter enable"]
395    #[inline(always)]
396    pub fn adcen(&self) -> ADCEN_R {
397        ADCEN_R::new((self.bits & 1) != 0)
398    }
399    #[doc = "Bit 1 - Repeat mode enable"]
400    #[inline(always)]
401    pub fn rpen(&self) -> RPEN_R {
402        RPEN_R::new(((self.bits >> 1) & 1) != 0)
403    }
404    #[doc = "Bit 2 - A/D Calibration"]
405    #[inline(always)]
406    pub fn adcal(&self) -> ADCAL_R {
407        ADCAL_R::new(((self.bits >> 2) & 1) != 0)
408    }
409    #[doc = "Bit 3 - initialize A/D calibration"]
410    #[inline(always)]
411    pub fn adcalinit(&self) -> ADCALINIT_R {
412        ADCALINIT_R::new(((self.bits >> 3) & 1) != 0)
413    }
414    #[doc = "Bit 11 - Data alignment"]
415    #[inline(always)]
416    pub fn dtalign(&self) -> DTALIGN_R {
417        DTALIGN_R::new(((self.bits >> 11) & 1) != 0)
418    }
419    #[doc = "Bits 12:14 - Low bit of trigger event select for preempted channels conversion"]
420    #[inline(always)]
421    pub fn pctesel_l(&self) -> PCTESEL_L_R {
422        PCTESEL_L_R::new(((self.bits >> 12) & 7) as u8)
423    }
424    #[doc = "Bit 15 - Trigger mode enable for preempted channels conversion"]
425    #[inline(always)]
426    pub fn pcten(&self) -> PCTEN_R {
427        PCTEN_R::new(((self.bits >> 15) & 1) != 0)
428    }
429    #[doc = "Bits 17:19 - Low bit of trigger event select for ordinary channels conversion"]
430    #[inline(always)]
431    pub fn octesel_l(&self) -> OCTESEL_L_R {
432        OCTESEL_L_R::new(((self.bits >> 17) & 7) as u8)
433    }
434    #[doc = "Bit 20 - Trigger mode enable for ordinary channels conversion"]
435    #[inline(always)]
436    pub fn octen(&self) -> OCTEN_R {
437        OCTEN_R::new(((self.bits >> 20) & 1) != 0)
438    }
439    #[doc = "Bit 21 - Conversion trigger by software of preempted channels"]
440    #[inline(always)]
441    pub fn pcswtrg(&self) -> PCSWTRG_R {
442        PCSWTRG_R::new(((self.bits >> 21) & 1) != 0)
443    }
444    #[doc = "Bit 22 - Conversion trigger by software of ordinary channels"]
445    #[inline(always)]
446    pub fn ocswtrg(&self) -> OCSWTRG_R {
447        OCSWTRG_R::new(((self.bits >> 22) & 1) != 0)
448    }
449    #[doc = "Bit 24 - High bit of trigger event select for preempted channels conversion"]
450    #[inline(always)]
451    pub fn pctesel_h(&self) -> PCTESEL_H_R {
452        PCTESEL_H_R::new(((self.bits >> 24) & 1) != 0)
453    }
454    #[doc = "Bit 25 - High bit of trigger event select for ordinary channels conversion"]
455    #[inline(always)]
456    pub fn octesel_h(&self) -> OCTESEL_H_R {
457        OCTESEL_H_R::new(((self.bits >> 25) & 1) != 0)
458    }
459}
460impl core::fmt::Debug for R {
461    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
462        f.debug_struct("CTRL2")
463            .field("octesel_h", &self.octesel_h())
464            .field("pctesel_h", &self.pctesel_h())
465            .field("pcswtrg", &self.pcswtrg())
466            .field("ocswtrg", &self.ocswtrg())
467            .field("octen", &self.octen())
468            .field("octesel_l", &self.octesel_l())
469            .field("pcten", &self.pcten())
470            .field("pctesel_l", &self.pctesel_l())
471            .field("dtalign", &self.dtalign())
472            .field("adcalinit", &self.adcalinit())
473            .field("adcal", &self.adcal())
474            .field("rpen", &self.rpen())
475            .field("adcen", &self.adcen())
476            .finish()
477    }
478}
479impl W {
480    #[doc = "Bit 0 - A/D converter enable"]
481    #[inline(always)]
482    pub fn adcen(&mut self) -> ADCEN_W<'_, CTRL2_SPEC> {
483        ADCEN_W::new(self, 0)
484    }
485    #[doc = "Bit 1 - Repeat mode enable"]
486    #[inline(always)]
487    pub fn rpen(&mut self) -> RPEN_W<'_, CTRL2_SPEC> {
488        RPEN_W::new(self, 1)
489    }
490    #[doc = "Bit 2 - A/D Calibration"]
491    #[inline(always)]
492    pub fn adcal(&mut self) -> ADCAL_W<'_, CTRL2_SPEC> {
493        ADCAL_W::new(self, 2)
494    }
495    #[doc = "Bit 3 - initialize A/D calibration"]
496    #[inline(always)]
497    pub fn adcalinit(&mut self) -> ADCALINIT_W<'_, CTRL2_SPEC> {
498        ADCALINIT_W::new(self, 3)
499    }
500    #[doc = "Bit 11 - Data alignment"]
501    #[inline(always)]
502    pub fn dtalign(&mut self) -> DTALIGN_W<'_, CTRL2_SPEC> {
503        DTALIGN_W::new(self, 11)
504    }
505    #[doc = "Bits 12:14 - Low bit of trigger event select for preempted channels conversion"]
506    #[inline(always)]
507    pub fn pctesel_l(&mut self) -> PCTESEL_L_W<'_, CTRL2_SPEC> {
508        PCTESEL_L_W::new(self, 12)
509    }
510    #[doc = "Bit 15 - Trigger mode enable for preempted channels conversion"]
511    #[inline(always)]
512    pub fn pcten(&mut self) -> PCTEN_W<'_, CTRL2_SPEC> {
513        PCTEN_W::new(self, 15)
514    }
515    #[doc = "Bits 17:19 - Low bit of trigger event select for ordinary channels conversion"]
516    #[inline(always)]
517    pub fn octesel_l(&mut self) -> OCTESEL_L_W<'_, CTRL2_SPEC> {
518        OCTESEL_L_W::new(self, 17)
519    }
520    #[doc = "Bit 20 - Trigger mode enable for ordinary channels conversion"]
521    #[inline(always)]
522    pub fn octen(&mut self) -> OCTEN_W<'_, CTRL2_SPEC> {
523        OCTEN_W::new(self, 20)
524    }
525    #[doc = "Bit 21 - Conversion trigger by software of preempted channels"]
526    #[inline(always)]
527    pub fn pcswtrg(&mut self) -> PCSWTRG_W<'_, CTRL2_SPEC> {
528        PCSWTRG_W::new(self, 21)
529    }
530    #[doc = "Bit 22 - Conversion trigger by software of ordinary channels"]
531    #[inline(always)]
532    pub fn ocswtrg(&mut self) -> OCSWTRG_W<'_, CTRL2_SPEC> {
533        OCSWTRG_W::new(self, 22)
534    }
535    #[doc = "Bit 24 - High bit of trigger event select for preempted channels conversion"]
536    #[inline(always)]
537    pub fn pctesel_h(&mut self) -> PCTESEL_H_W<'_, CTRL2_SPEC> {
538        PCTESEL_H_W::new(self, 24)
539    }
540    #[doc = "Bit 25 - High bit of trigger event select for ordinary channels conversion"]
541    #[inline(always)]
542    pub fn octesel_h(&mut self) -> OCTESEL_H_W<'_, CTRL2_SPEC> {
543        OCTESEL_H_W::new(self, 25)
544    }
545}
546#[doc = "control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
547pub struct CTRL2_SPEC;
548impl crate::RegisterSpec for CTRL2_SPEC {
549    type Ux = u32;
550}
551#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
552impl crate::Readable for CTRL2_SPEC {}
553#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
554impl crate::Writable for CTRL2_SPEC {
555    type Safety = crate::Unsafe;
556}
557#[doc = "`reset()` method sets CTRL2 to value 0"]
558impl crate::Resettable for CTRL2_SPEC {}
at32f4xx_pac/at32a403a/adc2/ctrl2.rs

at32f4xx_pac/at32a403a/adc2/
ctrl2.rs
