at32f4xx_pac/at32wb415/spi2/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "DMA receive enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum Dmarenr {
8    #[doc = "0: DMA receive is disabled"]
9    Disabled = 0,
10    #[doc = "1: DMA receive is enabled"]
11    Enabled = 1,
12}
13impl From<Dmarenr> for bool {
14    #[inline(always)]
15    fn from(variant: Dmarenr) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `DMAREN` reader - DMA receive enable"]
20pub type DMAREN_R = crate::BitReader<Dmarenr>;
21impl DMAREN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> Dmarenr {
25        match self.bits {
26            false => Dmarenr::Disabled,
27            true => Dmarenr::Enabled,
28        }
29    }
30    #[doc = "DMA receive is disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == Dmarenr::Disabled
34    }
35    #[doc = "DMA receive is enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == Dmarenr::Enabled
39    }
40}
41#[doc = "DMA receive enable\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum DmarenwWO {
44    #[doc = "0: DMA receive disable"]
45    Disable = 0,
46    #[doc = "1: DMA receive enable"]
47    Enable = 1,
48}
49impl From<DmarenwWO> for bool {
50    #[inline(always)]
51    fn from(variant: DmarenwWO) -> Self {
52        variant as u8 != 0
53    }
54}
55#[doc = "Field `DMAREN` writer - DMA receive enable"]
56pub type DMAREN_W<'a, REG> = crate::BitWriter<'a, REG, DmarenwWO>;
57impl<'a, REG> DMAREN_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60{
61    #[doc = "DMA receive disable"]
62    #[inline(always)]
63    pub fn disable(self) -> &'a mut crate::W<REG> {
64        self.variant(DmarenwWO::Disable)
65    }
66    #[doc = "DMA receive enable"]
67    #[inline(always)]
68    pub fn enable(self) -> &'a mut crate::W<REG> {
69        self.variant(DmarenwWO::Enable)
70    }
71}
72#[doc = "DMA transmit enable\n\nValue on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74pub enum Dmatenr {
75    #[doc = "0: DMA transmit is disabled"]
76    Disabled = 0,
77    #[doc = "1: DMA transmit is enabled"]
78    Enabled = 1,
79}
80impl From<Dmatenr> for bool {
81    #[inline(always)]
82    fn from(variant: Dmatenr) -> Self {
83        variant as u8 != 0
84    }
85}
86#[doc = "Field `DMATEN` reader - DMA transmit enable"]
87pub type DMATEN_R = crate::BitReader<Dmatenr>;
88impl DMATEN_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Dmatenr {
92        match self.bits {
93            false => Dmatenr::Disabled,
94            true => Dmatenr::Enabled,
95        }
96    }
97    #[doc = "DMA transmit is disabled"]
98    #[inline(always)]
99    pub fn is_disabled(&self) -> bool {
100        *self == Dmatenr::Disabled
101    }
102    #[doc = "DMA transmit is enabled"]
103    #[inline(always)]
104    pub fn is_enabled(&self) -> bool {
105        *self == Dmatenr::Enabled
106    }
107}
108#[doc = "DMA transmit enable\n\nValue on reset: 0"]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum DmatenwWO {
111    #[doc = "0: DMA transmit disable"]
112    Disable = 0,
113    #[doc = "1: DMA transmit enable"]
114    Enable = 1,
115}
116impl From<DmatenwWO> for bool {
117    #[inline(always)]
118    fn from(variant: DmatenwWO) -> Self {
119        variant as u8 != 0
120    }
121}
122#[doc = "Field `DMATEN` writer - DMA transmit enable"]
123pub type DMATEN_W<'a, REG> = crate::BitWriter<'a, REG, DmatenwWO>;
124impl<'a, REG> DMATEN_W<'a, REG>
125where
126    REG: crate::Writable + crate::RegisterSpec,
127{
128    #[doc = "DMA transmit disable"]
129    #[inline(always)]
130    pub fn disable(self) -> &'a mut crate::W<REG> {
131        self.variant(DmatenwWO::Disable)
132    }
133    #[doc = "DMA transmit enable"]
134    #[inline(always)]
135    pub fn enable(self) -> &'a mut crate::W<REG> {
136        self.variant(DmatenwWO::Enable)
137    }
138}
139#[doc = "Error interrupt enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum Errier {
142    #[doc = "0: Error interrupt is disabled"]
143    Disabled = 0,
144    #[doc = "1: Error interrupt is enabled"]
145    Enabled = 1,
146}
147impl From<Errier> for bool {
148    #[inline(always)]
149    fn from(variant: Errier) -> Self {
150        variant as u8 != 0
151    }
152}
153#[doc = "Field `ERRIE` reader - Error interrupt enable"]
154pub type ERRIE_R = crate::BitReader<Errier>;
155impl ERRIE_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub const fn variant(&self) -> Errier {
159        match self.bits {
160            false => Errier::Disabled,
161            true => Errier::Enabled,
162        }
163    }
164    #[doc = "Error interrupt is disabled"]
165    #[inline(always)]
166    pub fn is_disabled(&self) -> bool {
167        *self == Errier::Disabled
168    }
169    #[doc = "Error interrupt is enabled"]
170    #[inline(always)]
171    pub fn is_enabled(&self) -> bool {
172        *self == Errier::Enabled
173    }
174}
175#[doc = "Error interrupt enable\n\nValue on reset: 0"]
176#[derive(Clone, Copy, Debug, PartialEq, Eq)]
177pub enum ErriewWO {
178    #[doc = "0: Error interrupt disable"]
179    Disable = 0,
180    #[doc = "1: Error interrupt enable"]
181    Enable = 1,
182}
183impl From<ErriewWO> for bool {
184    #[inline(always)]
185    fn from(variant: ErriewWO) -> Self {
186        variant as u8 != 0
187    }
188}
189#[doc = "Field `ERRIE` writer - Error interrupt enable"]
190pub type ERRIE_W<'a, REG> = crate::BitWriter<'a, REG, ErriewWO>;
191impl<'a, REG> ERRIE_W<'a, REG>
192where
193    REG: crate::Writable + crate::RegisterSpec,
194{
195    #[doc = "Error interrupt disable"]
196    #[inline(always)]
197    pub fn disable(self) -> &'a mut crate::W<REG> {
198        self.variant(ErriewWO::Disable)
199    }
200    #[doc = "Error interrupt enable"]
201    #[inline(always)]
202    pub fn enable(self) -> &'a mut crate::W<REG> {
203        self.variant(ErriewWO::Enable)
204    }
205}
206#[doc = "Receive data buffer full interrupt enable\n\nValue on reset: 0"]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum Rdbfier {
209    #[doc = "0: Receive data buffer full interrupt is disabled"]
210    Disabled = 0,
211    #[doc = "1: Receive data buffer full interrupt is enabled"]
212    Enabled = 1,
213}
214impl From<Rdbfier> for bool {
215    #[inline(always)]
216    fn from(variant: Rdbfier) -> Self {
217        variant as u8 != 0
218    }
219}
220#[doc = "Field `RDBFIE` reader - Receive data buffer full interrupt enable"]
221pub type RDBFIE_R = crate::BitReader<Rdbfier>;
222impl RDBFIE_R {
223    #[doc = "Get enumerated values variant"]
224    #[inline(always)]
225    pub const fn variant(&self) -> Rdbfier {
226        match self.bits {
227            false => Rdbfier::Disabled,
228            true => Rdbfier::Enabled,
229        }
230    }
231    #[doc = "Receive data buffer full interrupt is disabled"]
232    #[inline(always)]
233    pub fn is_disabled(&self) -> bool {
234        *self == Rdbfier::Disabled
235    }
236    #[doc = "Receive data buffer full interrupt is enabled"]
237    #[inline(always)]
238    pub fn is_enabled(&self) -> bool {
239        *self == Rdbfier::Enabled
240    }
241}
242#[doc = "Receive data buffer full interrupt enable\n\nValue on reset: 0"]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244pub enum RdbfiewWO {
245    #[doc = "0: Receive data buffer full interrupt disable"]
246    Disable = 0,
247    #[doc = "1: Receive data buffer full interrupt enable"]
248    Enable = 1,
249}
250impl From<RdbfiewWO> for bool {
251    #[inline(always)]
252    fn from(variant: RdbfiewWO) -> Self {
253        variant as u8 != 0
254    }
255}
256#[doc = "Field `RDBFIE` writer - Receive data buffer full interrupt enable"]
257pub type RDBFIE_W<'a, REG> = crate::BitWriter<'a, REG, RdbfiewWO>;
258impl<'a, REG> RDBFIE_W<'a, REG>
259where
260    REG: crate::Writable + crate::RegisterSpec,
261{
262    #[doc = "Receive data buffer full interrupt disable"]
263    #[inline(always)]
264    pub fn disable(self) -> &'a mut crate::W<REG> {
265        self.variant(RdbfiewWO::Disable)
266    }
267    #[doc = "Receive data buffer full interrupt enable"]
268    #[inline(always)]
269    pub fn enable(self) -> &'a mut crate::W<REG> {
270        self.variant(RdbfiewWO::Enable)
271    }
272}
273#[doc = "Transmit data buffer empty interrupt enable\n\nValue on reset: 0"]
274#[derive(Clone, Copy, Debug, PartialEq, Eq)]
275pub enum Tdbeier {
276    #[doc = "0: Transmit data buffer empty interrupt is disabled"]
277    Disabled = 0,
278    #[doc = "1: Transmit data buffer empty interrupt is enabled"]
279    Enabled = 1,
280}
281impl From<Tdbeier> for bool {
282    #[inline(always)]
283    fn from(variant: Tdbeier) -> Self {
284        variant as u8 != 0
285    }
286}
287#[doc = "Field `TDBEIE` reader - Transmit data buffer empty interrupt enable"]
288pub type TDBEIE_R = crate::BitReader<Tdbeier>;
289impl TDBEIE_R {
290    #[doc = "Get enumerated values variant"]
291    #[inline(always)]
292    pub const fn variant(&self) -> Tdbeier {
293        match self.bits {
294            false => Tdbeier::Disabled,
295            true => Tdbeier::Enabled,
296        }
297    }
298    #[doc = "Transmit data buffer empty interrupt is disabled"]
299    #[inline(always)]
300    pub fn is_disabled(&self) -> bool {
301        *self == Tdbeier::Disabled
302    }
303    #[doc = "Transmit data buffer empty interrupt is enabled"]
304    #[inline(always)]
305    pub fn is_enabled(&self) -> bool {
306        *self == Tdbeier::Enabled
307    }
308}
309#[doc = "Transmit data buffer empty interrupt enable\n\nValue on reset: 0"]
310#[derive(Clone, Copy, Debug, PartialEq, Eq)]
311pub enum TdbeiewWO {
312    #[doc = "0: Transmit data buffer empty interrupt disable"]
313    Disable = 0,
314    #[doc = "1: Transmit data buffer empty interrupt enable"]
315    Enable = 1,
316}
317impl From<TdbeiewWO> for bool {
318    #[inline(always)]
319    fn from(variant: TdbeiewWO) -> Self {
320        variant as u8 != 0
321    }
322}
323#[doc = "Field `TDBEIE` writer - Transmit data buffer empty interrupt enable"]
324pub type TDBEIE_W<'a, REG> = crate::BitWriter<'a, REG, TdbeiewWO>;
325impl<'a, REG> TDBEIE_W<'a, REG>
326where
327    REG: crate::Writable + crate::RegisterSpec,
328{
329    #[doc = "Transmit data buffer empty interrupt disable"]
330    #[inline(always)]
331    pub fn disable(self) -> &'a mut crate::W<REG> {
332        self.variant(TdbeiewWO::Disable)
333    }
334    #[doc = "Transmit data buffer empty interrupt enable"]
335    #[inline(always)]
336    pub fn enable(self) -> &'a mut crate::W<REG> {
337        self.variant(TdbeiewWO::Enable)
338    }
339}
340#[doc = "Field `MDIV3` reader - Master clock frequency division bit3"]
341pub type MDIV3_R = crate::BitReader;
342#[doc = "Field `MDIV3` writer - Master clock frequency division bit3"]
343pub type MDIV3_W<'a, REG> = crate::BitWriter<'a, REG>;
344impl R {
345    #[doc = "Bit 0 - DMA receive enable"]
346    #[inline(always)]
347    pub fn dmaren(&self) -> DMAREN_R {
348        DMAREN_R::new((self.bits & 1) != 0)
349    }
350    #[doc = "Bit 1 - DMA transmit enable"]
351    #[inline(always)]
352    pub fn dmaten(&self) -> DMATEN_R {
353        DMATEN_R::new(((self.bits >> 1) & 1) != 0)
354    }
355    #[doc = "Bit 5 - Error interrupt enable"]
356    #[inline(always)]
357    pub fn errie(&self) -> ERRIE_R {
358        ERRIE_R::new(((self.bits >> 5) & 1) != 0)
359    }
360    #[doc = "Bit 6 - Receive data buffer full interrupt enable"]
361    #[inline(always)]
362    pub fn rdbfie(&self) -> RDBFIE_R {
363        RDBFIE_R::new(((self.bits >> 6) & 1) != 0)
364    }
365    #[doc = "Bit 7 - Transmit data buffer empty interrupt enable"]
366    #[inline(always)]
367    pub fn tdbeie(&self) -> TDBEIE_R {
368        TDBEIE_R::new(((self.bits >> 7) & 1) != 0)
369    }
370    #[doc = "Bit 8 - Master clock frequency division bit3"]
371    #[inline(always)]
372    pub fn mdiv3(&self) -> MDIV3_R {
373        MDIV3_R::new(((self.bits >> 8) & 1) != 0)
374    }
375}
376impl core::fmt::Debug for R {
377    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
378        f.debug_struct("CTRL2")
379            .field("mdiv3", &self.mdiv3())
380            .field("tdbeie", &self.tdbeie())
381            .field("rdbfie", &self.rdbfie())
382            .field("errie", &self.errie())
383            .field("dmaten", &self.dmaten())
384            .field("dmaren", &self.dmaren())
385            .finish()
386    }
387}
388impl W {
389    #[doc = "Bit 0 - DMA receive enable"]
390    #[inline(always)]
391    #[must_use]
392    pub fn dmaren(&mut self) -> DMAREN_W<CTRL2_SPEC> {
393        DMAREN_W::new(self, 0)
394    }
395    #[doc = "Bit 1 - DMA transmit enable"]
396    #[inline(always)]
397    #[must_use]
398    pub fn dmaten(&mut self) -> DMATEN_W<CTRL2_SPEC> {
399        DMATEN_W::new(self, 1)
400    }
401    #[doc = "Bit 5 - Error interrupt enable"]
402    #[inline(always)]
403    #[must_use]
404    pub fn errie(&mut self) -> ERRIE_W<CTRL2_SPEC> {
405        ERRIE_W::new(self, 5)
406    }
407    #[doc = "Bit 6 - Receive data buffer full interrupt enable"]
408    #[inline(always)]
409    #[must_use]
410    pub fn rdbfie(&mut self) -> RDBFIE_W<CTRL2_SPEC> {
411        RDBFIE_W::new(self, 6)
412    }
413    #[doc = "Bit 7 - Transmit data buffer empty interrupt enable"]
414    #[inline(always)]
415    #[must_use]
416    pub fn tdbeie(&mut self) -> TDBEIE_W<CTRL2_SPEC> {
417        TDBEIE_W::new(self, 7)
418    }
419    #[doc = "Bit 8 - Master clock frequency division bit3"]
420    #[inline(always)]
421    #[must_use]
422    pub fn mdiv3(&mut self) -> MDIV3_W<CTRL2_SPEC> {
423        MDIV3_W::new(self, 8)
424    }
425}
426#[doc = "control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
427pub struct CTRL2_SPEC;
428impl crate::RegisterSpec for CTRL2_SPEC {
429    type Ux = u32;
430}
431#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
432impl crate::Readable for CTRL2_SPEC {}
433#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
434impl crate::Writable for CTRL2_SPEC {
435    type Safety = crate::Unsafe;
436    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
437    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
438}
439#[doc = "`reset()` method sets CTRL2 to value 0"]
440impl crate::Resettable for CTRL2_SPEC {
441    const RESET_VALUE: u32 = 0;
442}
at32f4xx_pac/at32wb415/spi2/ctrl2.rs

at32f4xx_pac/at32wb415/spi2/
ctrl2.rs
