at32f4xx_pac/at32f413/tmr3/
cm2_input.rs

1#[doc = "Register `CM2_INPUT` reader"]
2pub type R = crate::R<CM2_INPUT_SPEC>;
3#[doc = "Register `CM2_INPUT` writer"]
4pub type W = crate::W<CM2_INPUT_SPEC>;
5#[doc = "Channel 3 configure\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum C3C_A {
9    #[doc = "0: C3IN channel is configured as output"]
10    Output = 0,
11    #[doc = "1: Input, C3IN is mapped on C3IFP3"]
12    C3ifp3 = 1,
13    #[doc = "2: Input, C3IN is mapped on C4IFP3"]
14    C4ifp3 = 2,
15    #[doc = "3: Input, C3IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
16    Stis = 3,
17}
18impl From<C3C_A> for u8 {
19    #[inline(always)]
20    fn from(variant: C3C_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for C3C_A {
25    type Ux = u8;
26}
27impl crate::IsEnum for C3C_A {}
28#[doc = "Field `C3C` reader - Channel 3 configure"]
29pub type C3C_R = crate::FieldReader<C3C_A>;
30impl C3C_R {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> C3C_A {
34        match self.bits {
35            0 => C3C_A::Output,
36            1 => C3C_A::C3ifp3,
37            2 => C3C_A::C4ifp3,
38            3 => C3C_A::Stis,
39            _ => unreachable!(),
40        }
41    }
42    #[doc = "C3IN channel is configured as output"]
43    #[inline(always)]
44    pub fn is_output(&self) -> bool {
45        *self == C3C_A::Output
46    }
47    #[doc = "Input, C3IN is mapped on C3IFP3"]
48    #[inline(always)]
49    pub fn is_c3ifp3(&self) -> bool {
50        *self == C3C_A::C3ifp3
51    }
52    #[doc = "Input, C3IN is mapped on C4IFP3"]
53    #[inline(always)]
54    pub fn is_c4ifp3(&self) -> bool {
55        *self == C3C_A::C4ifp3
56    }
57    #[doc = "Input, C3IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
58    #[inline(always)]
59    pub fn is_stis(&self) -> bool {
60        *self == C3C_A::Stis
61    }
62}
63#[doc = "Field `C3C` writer - Channel 3 configure"]
64pub type C3C_W<'a, REG> = crate::FieldWriter<'a, REG, 2, C3C_A, crate::Safe>;
65impl<'a, REG> C3C_W<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "C3IN channel is configured as output"]
71    #[inline(always)]
72    pub fn output(self) -> &'a mut crate::W<REG> {
73        self.variant(C3C_A::Output)
74    }
75    #[doc = "Input, C3IN is mapped on C3IFP3"]
76    #[inline(always)]
77    pub fn c3ifp3(self) -> &'a mut crate::W<REG> {
78        self.variant(C3C_A::C3ifp3)
79    }
80    #[doc = "Input, C3IN is mapped on C4IFP3"]
81    #[inline(always)]
82    pub fn c4ifp3(self) -> &'a mut crate::W<REG> {
83        self.variant(C3C_A::C4ifp3)
84    }
85    #[doc = "Input, C3IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
86    #[inline(always)]
87    pub fn stis(self) -> &'a mut crate::W<REG> {
88        self.variant(C3C_A::Stis)
89    }
90}
91#[doc = "Channel %s input divider\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93#[repr(u8)]
94pub enum C3IDIV_A {
95    #[doc = "0: No divider. An input capture is generated at each active edge."]
96    Every = 0,
97    #[doc = "1: An input compare is generated every 2 active edges"]
98    Div2 = 1,
99    #[doc = "2: An input compare is generated every 4 active edges"]
100    Div4 = 2,
101    #[doc = "3: An input compare is generated every 8 active edges"]
102    Div8 = 3,
103}
104impl From<C3IDIV_A> for u8 {
105    #[inline(always)]
106    fn from(variant: C3IDIV_A) -> Self {
107        variant as _
108    }
109}
110impl crate::FieldSpec for C3IDIV_A {
111    type Ux = u8;
112}
113impl crate::IsEnum for C3IDIV_A {}
114#[doc = "Field `CIDIV(3-4)` reader - Channel %s input divider"]
115pub type CIDIV_R = crate::FieldReader<C3IDIV_A>;
116impl CIDIV_R {
117    #[doc = "Get enumerated values variant"]
118    #[inline(always)]
119    pub const fn variant(&self) -> C3IDIV_A {
120        match self.bits {
121            0 => C3IDIV_A::Every,
122            1 => C3IDIV_A::Div2,
123            2 => C3IDIV_A::Div4,
124            3 => C3IDIV_A::Div8,
125            _ => unreachable!(),
126        }
127    }
128    #[doc = "No divider. An input capture is generated at each active edge."]
129    #[inline(always)]
130    pub fn is_every(&self) -> bool {
131        *self == C3IDIV_A::Every
132    }
133    #[doc = "An input compare is generated every 2 active edges"]
134    #[inline(always)]
135    pub fn is_div2(&self) -> bool {
136        *self == C3IDIV_A::Div2
137    }
138    #[doc = "An input compare is generated every 4 active edges"]
139    #[inline(always)]
140    pub fn is_div4(&self) -> bool {
141        *self == C3IDIV_A::Div4
142    }
143    #[doc = "An input compare is generated every 8 active edges"]
144    #[inline(always)]
145    pub fn is_div8(&self) -> bool {
146        *self == C3IDIV_A::Div8
147    }
148}
149#[doc = "Field `CIDIV(3-4)` writer - Channel %s input divider"]
150pub type CIDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2, C3IDIV_A, crate::Safe>;
151impl<'a, REG> CIDIV_W<'a, REG>
152where
153    REG: crate::Writable + crate::RegisterSpec,
154    REG::Ux: From<u8>,
155{
156    #[doc = "No divider. An input capture is generated at each active edge."]
157    #[inline(always)]
158    pub fn every(self) -> &'a mut crate::W<REG> {
159        self.variant(C3IDIV_A::Every)
160    }
161    #[doc = "An input compare is generated every 2 active edges"]
162    #[inline(always)]
163    pub fn div2(self) -> &'a mut crate::W<REG> {
164        self.variant(C3IDIV_A::Div2)
165    }
166    #[doc = "An input compare is generated every 4 active edges"]
167    #[inline(always)]
168    pub fn div4(self) -> &'a mut crate::W<REG> {
169        self.variant(C3IDIV_A::Div4)
170    }
171    #[doc = "An input compare is generated every 8 active edges"]
172    #[inline(always)]
173    pub fn div8(self) -> &'a mut crate::W<REG> {
174        self.variant(C3IDIV_A::Div8)
175    }
176}
177#[doc = "Field `CDF(3-4)` reader - Channel %s digital filter"]
178pub type CDF_R = crate::FieldReader;
179#[doc = "Field `CDF(3-4)` writer - Channel %s digital filter"]
180pub type CDF_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
181#[doc = "Channel 4 configure\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183#[repr(u8)]
184pub enum C4C_A {
185    #[doc = "0: C4IN channel is configured as output"]
186    Output = 0,
187    #[doc = "1: Input, C4IN is mapped on C4IFP4"]
188    C4ifp4 = 1,
189    #[doc = "2: Input, C4IN is mapped on C3IFP4"]
190    C3ifp4 = 2,
191    #[doc = "3: Input, C4IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
192    Stis = 3,
193}
194impl From<C4C_A> for u8 {
195    #[inline(always)]
196    fn from(variant: C4C_A) -> Self {
197        variant as _
198    }
199}
200impl crate::FieldSpec for C4C_A {
201    type Ux = u8;
202}
203impl crate::IsEnum for C4C_A {}
204#[doc = "Field `C4C` reader - Channel 4 configure"]
205pub type C4C_R = crate::FieldReader<C4C_A>;
206impl C4C_R {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub const fn variant(&self) -> C4C_A {
210        match self.bits {
211            0 => C4C_A::Output,
212            1 => C4C_A::C4ifp4,
213            2 => C4C_A::C3ifp4,
214            3 => C4C_A::Stis,
215            _ => unreachable!(),
216        }
217    }
218    #[doc = "C4IN channel is configured as output"]
219    #[inline(always)]
220    pub fn is_output(&self) -> bool {
221        *self == C4C_A::Output
222    }
223    #[doc = "Input, C4IN is mapped on C4IFP4"]
224    #[inline(always)]
225    pub fn is_c4ifp4(&self) -> bool {
226        *self == C4C_A::C4ifp4
227    }
228    #[doc = "Input, C4IN is mapped on C3IFP4"]
229    #[inline(always)]
230    pub fn is_c3ifp4(&self) -> bool {
231        *self == C4C_A::C3ifp4
232    }
233    #[doc = "Input, C4IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
234    #[inline(always)]
235    pub fn is_stis(&self) -> bool {
236        *self == C4C_A::Stis
237    }
238}
239#[doc = "Field `C4C` writer - Channel 4 configure"]
240pub type C4C_W<'a, REG> = crate::FieldWriter<'a, REG, 2, C4C_A, crate::Safe>;
241impl<'a, REG> C4C_W<'a, REG>
242where
243    REG: crate::Writable + crate::RegisterSpec,
244    REG::Ux: From<u8>,
245{
246    #[doc = "C4IN channel is configured as output"]
247    #[inline(always)]
248    pub fn output(self) -> &'a mut crate::W<REG> {
249        self.variant(C4C_A::Output)
250    }
251    #[doc = "Input, C4IN is mapped on C4IFP4"]
252    #[inline(always)]
253    pub fn c4ifp4(self) -> &'a mut crate::W<REG> {
254        self.variant(C4C_A::C4ifp4)
255    }
256    #[doc = "Input, C4IN is mapped on C3IFP4"]
257    #[inline(always)]
258    pub fn c3ifp4(self) -> &'a mut crate::W<REG> {
259        self.variant(C4C_A::C3ifp4)
260    }
261    #[doc = "Input, C4IN is mapped on STCI. This mode works only when the internal trigger input is selected by STIS."]
262    #[inline(always)]
263    pub fn stis(self) -> &'a mut crate::W<REG> {
264        self.variant(C4C_A::Stis)
265    }
266}
267impl R {
268    #[doc = "Bits 0:1 - Channel 3 configure"]
269    #[inline(always)]
270    pub fn c3c(&self) -> C3C_R {
271        C3C_R::new((self.bits & 3) as u8)
272    }
273    #[doc = "Channel (3-4) input divider"]
274    #[doc = ""]
275    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C3IDIV` field.</div>"]
276    #[inline(always)]
277    pub fn cidiv(&self, n: u8) -> CIDIV_R {
278        #[allow(clippy::no_effect)]
279        [(); 2][n as usize];
280        CIDIV_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8)
281    }
282    #[doc = "Iterator for array of:"]
283    #[doc = "Channel (3-4) input divider"]
284    #[inline(always)]
285    pub fn cidiv_iter(&self) -> impl Iterator<Item = CIDIV_R> + '_ {
286        (0..2).map(move |n| CIDIV_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8))
287    }
288    #[doc = "Bits 2:3 - Channel 3 input divider"]
289    #[inline(always)]
290    pub fn c3idiv(&self) -> CIDIV_R {
291        CIDIV_R::new(((self.bits >> 2) & 3) as u8)
292    }
293    #[doc = "Bits 10:11 - Channel 4 input divider"]
294    #[inline(always)]
295    pub fn c4idiv(&self) -> CIDIV_R {
296        CIDIV_R::new(((self.bits >> 10) & 3) as u8)
297    }
298    #[doc = "Channel (3-4) digital filter"]
299    #[doc = ""]
300    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C3DF` field.</div>"]
301    #[inline(always)]
302    pub fn cdf(&self, n: u8) -> CDF_R {
303        #[allow(clippy::no_effect)]
304        [(); 2][n as usize];
305        CDF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8)
306    }
307    #[doc = "Iterator for array of:"]
308    #[doc = "Channel (3-4) digital filter"]
309    #[inline(always)]
310    pub fn cdf_iter(&self) -> impl Iterator<Item = CDF_R> + '_ {
311        (0..2).map(move |n| CDF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8))
312    }
313    #[doc = "Bits 4:7 - Channel 3 digital filter"]
314    #[inline(always)]
315    pub fn c3df(&self) -> CDF_R {
316        CDF_R::new(((self.bits >> 4) & 0x0f) as u8)
317    }
318    #[doc = "Bits 12:15 - Channel 4 digital filter"]
319    #[inline(always)]
320    pub fn c4df(&self) -> CDF_R {
321        CDF_R::new(((self.bits >> 12) & 0x0f) as u8)
322    }
323    #[doc = "Bits 8:9 - Channel 4 configure"]
324    #[inline(always)]
325    pub fn c4c(&self) -> C4C_R {
326        C4C_R::new(((self.bits >> 8) & 3) as u8)
327    }
328}
329impl core::fmt::Debug for R {
330    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
331        f.debug_struct("CM2_INPUT")
332            .field("c3df", &self.c3df())
333            .field("c4df", &self.c4df())
334            .field("c3idiv", &self.c3idiv())
335            .field("c4idiv", &self.c4idiv())
336            .field("c4c", &self.c4c())
337            .field("c3c", &self.c3c())
338            .finish()
339    }
340}
341impl W {
342    #[doc = "Bits 0:1 - Channel 3 configure"]
343    #[inline(always)]
344    #[must_use]
345    pub fn c3c(&mut self) -> C3C_W<CM2_INPUT_SPEC> {
346        C3C_W::new(self, 0)
347    }
348    #[doc = "Channel (3-4) input divider"]
349    #[doc = ""]
350    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C3IDIV` field.</div>"]
351    #[inline(always)]
352    #[must_use]
353    pub fn cidiv(&mut self, n: u8) -> CIDIV_W<CM2_INPUT_SPEC> {
354        #[allow(clippy::no_effect)]
355        [(); 2][n as usize];
356        CIDIV_W::new(self, n * 8 + 2)
357    }
358    #[doc = "Bits 2:3 - Channel 3 input divider"]
359    #[inline(always)]
360    #[must_use]
361    pub fn c3idiv(&mut self) -> CIDIV_W<CM2_INPUT_SPEC> {
362        CIDIV_W::new(self, 2)
363    }
364    #[doc = "Bits 10:11 - Channel 4 input divider"]
365    #[inline(always)]
366    #[must_use]
367    pub fn c4idiv(&mut self) -> CIDIV_W<CM2_INPUT_SPEC> {
368        CIDIV_W::new(self, 10)
369    }
370    #[doc = "Channel (3-4) digital filter"]
371    #[doc = ""]
372    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `C3DF` field.</div>"]
373    #[inline(always)]
374    #[must_use]
375    pub fn cdf(&mut self, n: u8) -> CDF_W<CM2_INPUT_SPEC> {
376        #[allow(clippy::no_effect)]
377        [(); 2][n as usize];
378        CDF_W::new(self, n * 8 + 4)
379    }
380    #[doc = "Bits 4:7 - Channel 3 digital filter"]
381    #[inline(always)]
382    #[must_use]
383    pub fn c3df(&mut self) -> CDF_W<CM2_INPUT_SPEC> {
384        CDF_W::new(self, 4)
385    }
386    #[doc = "Bits 12:15 - Channel 4 digital filter"]
387    #[inline(always)]
388    #[must_use]
389    pub fn c4df(&mut self) -> CDF_W<CM2_INPUT_SPEC> {
390        CDF_W::new(self, 12)
391    }
392    #[doc = "Bits 8:9 - Channel 4 configure"]
393    #[inline(always)]
394    #[must_use]
395    pub fn c4c(&mut self) -> C4C_W<CM2_INPUT_SPEC> {
396        C4C_W::new(self, 8)
397    }
398}
399#[doc = "Channel input mode register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cm2_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cm2_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
400pub struct CM2_INPUT_SPEC;
401impl crate::RegisterSpec for CM2_INPUT_SPEC {
402    type Ux = u32;
403}
404#[doc = "`read()` method returns [`cm2_input::R`](R) reader structure"]
405impl crate::Readable for CM2_INPUT_SPEC {}
406#[doc = "`write(|w| ..)` method takes [`cm2_input::W`](W) writer structure"]
407impl crate::Writable for CM2_INPUT_SPEC {
408    type Safety = crate::Unsafe;
409    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
410    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
411}
412#[doc = "`reset()` method sets CM2_INPUT to value 0"]
413impl crate::Resettable for CM2_INPUT_SPEC {
414    const RESET_VALUE: u32 = 0;
415}
at32f4xx_pac/at32f413/tmr3/cm2_input.rs

at32f4xx_pac/at32f413/tmr3/
cm2_input.rs
