async_ltc681x/driver/registers/
cfgb.rs

1use super::base::{BitPos, RegisterBlock};
2/// Represents the Configuration Register Group B of the chip
3///
4/// For now only the GPIO parts are defined
5#[derive(Debug, Clone, Copy)]
6pub struct CfgB {
7    reg: RegisterBlock,
8}
9/// Enumeration of all GPIOs in [`CfgB`] which can be [`pulled down`](CfgB::pulldown_gpio) or [`released`](CfgB::release_gpio) (This is a Open Drain GPIO!)
10#[derive(Debug, Clone, Copy, PartialEq)]
11pub enum Gpio {
12    Gpio6,
13    Gpio7,
14    Gpio8,
15    Gpio9,
16}
17
18impl From<Gpio> for BitPos {
19    fn from(value: Gpio) -> Self {
20        match value {
21            Gpio::Gpio6 => BitPos::Pos0,
22            Gpio::Gpio7 => BitPos::Pos1,
23            Gpio::Gpio8 => BitPos::Pos2,
24            Gpio::Gpio9 => BitPos::Pos3,
25        }
26    }
27}
28
29/// Enumeration of all Cell Balance Switches in [`CfgB`] which can be [`activated`](CfgB::activate_single_switch) or [`deactivated`](CfgB::deactivate_single_switch)
30#[derive(Debug, Copy, Clone, PartialEq)]
31pub enum BalancingSwitch {
32    SwitchCell13,
33    SwitchCell14,
34    SwitchCell15,
35    SwitchCell16,
36    SwitchCell17,
37    SwitchCell18,
38}
39impl From<BalancingSwitch> for BitPos {
40    fn from(value: BalancingSwitch) -> Self {
41        match value {
42            BalancingSwitch::SwitchCell13 => BitPos::Pos4,
43            BalancingSwitch::SwitchCell14 => BitPos::Pos5,
44            BalancingSwitch::SwitchCell15 => BitPos::Pos6,
45            BalancingSwitch::SwitchCell16 => BitPos::Pos7,
46            BalancingSwitch::SwitchCell17 => BitPos::Pos8,
47            BalancingSwitch::SwitchCell18 => BitPos::Pos9,
48        }
49    }
50}
51/// Creates a `CfgB` Structure with the default values of the chip. This does not read back the actual
52/// `CfgB` Register value from the chip. Default value is only guaranteed to be inline with the actual register value
53/// of the chip after power up.
54impl Default for CfgB {
55    fn default() -> Self {
56        let reg = Self {
57            reg: RegisterBlock::default(),
58        };
59        reg.release_gpio(Gpio::Gpio6)
60            .release_gpio(Gpio::Gpio7)
61            .release_gpio(Gpio::Gpio8)
62            .release_gpio(Gpio::Gpio9)
63    }
64}
65impl CfgB {
66    /// Activate the open drain pulldown of the given GPIO
67    #[must_use]
68    pub fn pulldown_gpio(mut self, io: Gpio) -> Self {
69        self.reg.reset_bits_reg1(0b1, io.into());
70        self
71    }
72    /// Deactivate the open drain pulldown of the given GPIO (Floating Input)
73    ///
74    /// If the GPIOs are used as an ADC input, the pulldown must be deactivted for this GPIO.
75    #[must_use]
76    pub fn release_gpio(mut self, io: Gpio) -> Self {
77        self.reg.set_bits_reg1(0b1, io.into());
78        self
79    }
80    /// Activates the given Balancing Switch
81    #[must_use]
82    pub fn activate_single_switch(mut self, switch_nr: BalancingSwitch) -> Self {
83        self.reg.set_bits_reg1(0b1, switch_nr.into());
84        self
85    }
86    /// Deactivates the given Balancing Switch
87    #[must_use]
88    pub fn deactivate_single_switch(mut self, switch_nr: BalancingSwitch) -> Self {
89        self.reg.reset_bits_reg1(0b1, switch_nr.into());
90        self
91    }
92}
93
94impl From<RegisterBlock> for CfgB {
95    fn from(value: RegisterBlock) -> Self {
96        Self { reg: value }
97    }
98}
99impl From<CfgB> for RegisterBlock {
100    fn from(value: CfgB) -> Self {
101        value.reg
102    }
103}
104
105#[cfg(test)]
106mod tests {
107    use super::*;
108    #[test]
109    fn some_test() {
110        let cfgb = CfgB::default();
111        assert_eq!(cfgb.reg.reg_1, 0b0000_0000_0000_1111);
112
113        let cfgb = cfgb.pulldown_gpio(Gpio::Gpio6).pulldown_gpio(Gpio::Gpio7);
114        assert_eq!(cfgb.reg.reg_1, 0b0000_0000_0000_1100);
115
116        let cfgb = cfgb.pulldown_gpio(Gpio::Gpio8);
117        assert_eq!(cfgb.reg.reg_1, 0b0000_0000_0000_1000);
118
119        let cfgb = cfgb.pulldown_gpio(Gpio::Gpio9);
120        assert_eq!(cfgb.reg.reg_1, 0b0000_0000_0000_0000);
121
122        assert_eq!(
123            CfgB::from(RegisterBlock::default()).reg,
124            RegisterBlock::default()
125        );
126        assert_eq!(RegisterBlock::from(CfgB::default()).reg_1, 15);
127    }
128}
async_ltc681x/driver/registers/cfgb.rs

async_ltc681x/driver/registers/
cfgb.rs
