async_ltc681x/driver/registers/
base.rs

1/// `LTC681x` works internally always in `RegisterBlocks` of 3x16Bit values
2///
3/// Every Read/Write has always the width of 3x16Bit
4#[derive(Debug, Default, Clone, Copy, PartialEq)]
5#[allow(clippy::struct_field_names)]
6pub struct RegisterBlock {
7    pub(crate) reg_1: u16,
8    pub(crate) reg_2: u16,
9    pub(crate) reg_3: u16,
10}
11/// Enumeration of all possible Bit position
12///
13/// Bitwise operations are need to configure the chip
14pub enum BitPos {
15    Pos0 = 0,
16    Pos1 = 1,
17    Pos2 = 2,
18    Pos3 = 3,
19    Pos4 = 4,
20    Pos5 = 5,
21    Pos6 = 6,
22    Pos7 = 7,
23    Pos8 = 8,
24    Pos9 = 9,
25    Pos10 = 10,
26    Pos11 = 11,
27    Pos12 = 12,
28    Pos13 = 13,
29    Pos14 = 14,
30    Pos15 = 15,
31}
32impl RegisterBlock {
33    /// Sets the given Bits at the given Position for Register 1 of the Block
34    ///
35    /// Set operation only modifies the given bit width
36    pub fn set_bits_reg1(&mut self, bits: u16, pos: BitPos) {
37        Self::set_bits(&mut self.reg_1, bits, pos);
38    }
39    /// Sets the given Bits at the given Position for Register 2 of the Block
40    ///
41    /// Set operation only modifies the given bit width
42    pub fn set_bits_reg2(&mut self, bits: u16, pos: BitPos) {
43        Self::set_bits(&mut self.reg_2, bits, pos);
44    }
45    /// Sets the given Bits at the given Position for Register 3 of the Block
46    ///
47    /// Set operation only modifies the given bit width
48    pub fn set_bits_reg3(&mut self, bits: u16, pos: BitPos) {
49        Self::set_bits(&mut self.reg_3, bits, pos);
50    }
51
52    /// Resets the given Bits at the given Position for Register 1 of the Block
53    ///
54    /// Set operation only modifies the given bit width
55    pub fn reset_bits_reg1(&mut self, bits: u16, pos: BitPos) {
56        Self::reset_bits(&mut self.reg_1, bits, pos);
57    }
58    /// Resets the given Bits at the given Position for Register 2 of the Block
59    ///
60    /// Set operation only modifies the given bit width
61    pub fn reset_bits_reg2(&mut self, bits: u16, pos: BitPos) {
62        Self::reset_bits(&mut self.reg_2, bits, pos);
63    }
64    /// Resets the given Bits at the given Position for Register 3 of the Block
65    ///
66    /// Set operation only modifies the given bit width
67    pub fn reset_bits_reg3(&mut self, bits: u16, pos: BitPos) {
68        Self::reset_bits(&mut self.reg_3, bits, pos);
69    }
70    fn set_bits(reg: &mut u16, bits: u16, pos: BitPos) {
71        *reg |= bits << (pos as u16);
72    }
73    fn reset_bits(reg: &mut u16, bits: u16, pos: BitPos) {
74        *reg &= !(bits << (pos as u16));
75    }
76}
77
78#[cfg(test)]
79mod test {
80    use super::*;
81    #[test]
82    fn basics() {
83        let mut reg = RegisterBlock::default();
84        reg.set_bits_reg1(0b11, BitPos::Pos5);
85        reg.set_bits_reg2(0b101, BitPos::Pos9);
86        reg.set_bits_reg3(0b111, BitPos::Pos3);
87        assert_eq!(reg.reg_1, 0b11 << 5);
88        assert_eq!(reg.reg_2, 0b101 << 9);
89        assert_eq!(reg.reg_3, 0b111 << 3);
90        let res = reg.reg_1;
91
92        reg.set_bits_reg1(0b101, BitPos::Pos10);
93        assert_eq!(reg.reg_1, res | (0b101 << 10));
94        reg.reset_bits_reg1(0b111, BitPos::Pos10);
95        assert_eq!(reg.reg_1, 0b11 << 5);
96        let mut reg = RegisterBlock::default();
97        reg.set_bits_reg1(0b1111_1111_1111_1111, BitPos::Pos15);
98        assert_eq!(reg.reg_1, 0b1000_0000_0000_0000);
99
100        reg.set_bits_reg2(0b101, BitPos::Pos9);
101        assert_eq!(reg.reg_2, 0b101 << 9);
102        reg.reset_bits_reg2(0b1, BitPos::Pos9);
103        assert_eq!(reg.reg_2, 0b100 << 9);
104        reg.reset_bits_reg2(0b1, BitPos::Pos11);
105        assert_eq!(reg.reg_2, 0);
106
107        reg.set_bits_reg3(0b111, BitPos::Pos3);
108        reg.reset_bits_reg3(0b111, BitPos::Pos4);
109        assert_eq!(reg.reg_3, 0b1 << 3);
110    }
111}
async_ltc681x/driver/registers/base.rs

async_ltc681x/driver/registers/
base.rs
