asmkit/x86/features/
AVX512CD.rs

1use super::super::opcodes::*;
2use crate::core::emitter::*;
3use crate::core::operand::*;
4use crate::x86::assembler::*;
5use crate::x86::operands::*;
6
7/// A dummy operand that represents no register. Here just for simplicity.
8const NOREG: Operand = Operand::new();
9
10/// `VPBROADCASTMB2Q`.
11///
12/// Supported operand variants:
13///
14/// ```text
15/// +---+-----------+
16/// | # | Operands  |
17/// +---+-----------+
18/// | 1 | Xmm, KReg |
19/// | 2 | Ymm, KReg |
20/// | 3 | Zmm, KReg |
21/// +---+-----------+
22/// ```
23pub trait Vpbroadcastmb2qEmitter<A, B> {
24    fn vpbroadcastmb2q(&mut self, op0: A, op1: B);
25}
26
27impl<'a> Vpbroadcastmb2qEmitter<Xmm, KReg> for Assembler<'a> {
28    fn vpbroadcastmb2q(&mut self, op0: Xmm, op1: KReg) {
29        self.emit(
30            VPBROADCASTMB2Q128RK,
31            op0.as_operand(),
32            op1.as_operand(),
33            &NOREG,
34            &NOREG,
35        );
36    }
37}
38
39impl<'a> Vpbroadcastmb2qEmitter<Ymm, KReg> for Assembler<'a> {
40    fn vpbroadcastmb2q(&mut self, op0: Ymm, op1: KReg) {
41        self.emit(
42            VPBROADCASTMB2Q256RK,
43            op0.as_operand(),
44            op1.as_operand(),
45            &NOREG,
46            &NOREG,
47        );
48    }
49}
50
51impl<'a> Vpbroadcastmb2qEmitter<Zmm, KReg> for Assembler<'a> {
52    fn vpbroadcastmb2q(&mut self, op0: Zmm, op1: KReg) {
53        self.emit(
54            VPBROADCASTMB2Q512RK,
55            op0.as_operand(),
56            op1.as_operand(),
57            &NOREG,
58            &NOREG,
59        );
60    }
61}
62
63/// `VPBROADCASTMW2D`.
64///
65/// Supported operand variants:
66///
67/// ```text
68/// +---+-----------+
69/// | # | Operands  |
70/// +---+-----------+
71/// | 1 | Xmm, KReg |
72/// | 2 | Ymm, KReg |
73/// | 3 | Zmm, KReg |
74/// +---+-----------+
75/// ```
76pub trait Vpbroadcastmw2dEmitter<A, B> {
77    fn vpbroadcastmw2d(&mut self, op0: A, op1: B);
78}
79
80impl<'a> Vpbroadcastmw2dEmitter<Xmm, KReg> for Assembler<'a> {
81    fn vpbroadcastmw2d(&mut self, op0: Xmm, op1: KReg) {
82        self.emit(
83            VPBROADCASTMW2D128RK,
84            op0.as_operand(),
85            op1.as_operand(),
86            &NOREG,
87            &NOREG,
88        );
89    }
90}
91
92impl<'a> Vpbroadcastmw2dEmitter<Ymm, KReg> for Assembler<'a> {
93    fn vpbroadcastmw2d(&mut self, op0: Ymm, op1: KReg) {
94        self.emit(
95            VPBROADCASTMW2D256RK,
96            op0.as_operand(),
97            op1.as_operand(),
98            &NOREG,
99            &NOREG,
100        );
101    }
102}
103
104impl<'a> Vpbroadcastmw2dEmitter<Zmm, KReg> for Assembler<'a> {
105    fn vpbroadcastmw2d(&mut self, op0: Zmm, op1: KReg) {
106        self.emit(
107            VPBROADCASTMW2D512RK,
108            op0.as_operand(),
109            op1.as_operand(),
110            &NOREG,
111            &NOREG,
112        );
113    }
114}
115
116/// `VPCONFLICTD`.
117///
118/// Supported operand variants:
119///
120/// ```text
121/// +---+----------+
122/// | # | Operands |
123/// +---+----------+
124/// | 1 | Xmm, Mem |
125/// | 2 | Xmm, Xmm |
126/// | 3 | Ymm, Mem |
127/// | 4 | Ymm, Ymm |
128/// | 5 | Zmm, Mem |
129/// | 6 | Zmm, Zmm |
130/// +---+----------+
131/// ```
132pub trait VpconflictdEmitter<A, B> {
133    fn vpconflictd(&mut self, op0: A, op1: B);
134}
135
136impl<'a> VpconflictdEmitter<Xmm, Xmm> for Assembler<'a> {
137    fn vpconflictd(&mut self, op0: Xmm, op1: Xmm) {
138        self.emit(
139            VPCONFLICTD128RR,
140            op0.as_operand(),
141            op1.as_operand(),
142            &NOREG,
143            &NOREG,
144        );
145    }
146}
147
148impl<'a> VpconflictdEmitter<Xmm, Mem> for Assembler<'a> {
149    fn vpconflictd(&mut self, op0: Xmm, op1: Mem) {
150        self.emit(
151            VPCONFLICTD128RM,
152            op0.as_operand(),
153            op1.as_operand(),
154            &NOREG,
155            &NOREG,
156        );
157    }
158}
159
160impl<'a> VpconflictdEmitter<Ymm, Ymm> for Assembler<'a> {
161    fn vpconflictd(&mut self, op0: Ymm, op1: Ymm) {
162        self.emit(
163            VPCONFLICTD256RR,
164            op0.as_operand(),
165            op1.as_operand(),
166            &NOREG,
167            &NOREG,
168        );
169    }
170}
171
172impl<'a> VpconflictdEmitter<Ymm, Mem> for Assembler<'a> {
173    fn vpconflictd(&mut self, op0: Ymm, op1: Mem) {
174        self.emit(
175            VPCONFLICTD256RM,
176            op0.as_operand(),
177            op1.as_operand(),
178            &NOREG,
179            &NOREG,
180        );
181    }
182}
183
184impl<'a> VpconflictdEmitter<Zmm, Zmm> for Assembler<'a> {
185    fn vpconflictd(&mut self, op0: Zmm, op1: Zmm) {
186        self.emit(
187            VPCONFLICTD512RR,
188            op0.as_operand(),
189            op1.as_operand(),
190            &NOREG,
191            &NOREG,
192        );
193    }
194}
195
196impl<'a> VpconflictdEmitter<Zmm, Mem> for Assembler<'a> {
197    fn vpconflictd(&mut self, op0: Zmm, op1: Mem) {
198        self.emit(
199            VPCONFLICTD512RM,
200            op0.as_operand(),
201            op1.as_operand(),
202            &NOREG,
203            &NOREG,
204        );
205    }
206}
207
208/// `VPCONFLICTD_MASK`.
209///
210/// Supported operand variants:
211///
212/// ```text
213/// +---+----------+
214/// | # | Operands |
215/// +---+----------+
216/// | 1 | Xmm, Mem |
217/// | 2 | Xmm, Xmm |
218/// | 3 | Ymm, Mem |
219/// | 4 | Ymm, Ymm |
220/// | 5 | Zmm, Mem |
221/// | 6 | Zmm, Zmm |
222/// +---+----------+
223/// ```
224pub trait VpconflictdMaskEmitter<A, B> {
225    fn vpconflictd_mask(&mut self, op0: A, op1: B);
226}
227
228impl<'a> VpconflictdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
229    fn vpconflictd_mask(&mut self, op0: Xmm, op1: Xmm) {
230        self.emit(
231            VPCONFLICTD128RR_MASK,
232            op0.as_operand(),
233            op1.as_operand(),
234            &NOREG,
235            &NOREG,
236        );
237    }
238}
239
240impl<'a> VpconflictdMaskEmitter<Xmm, Mem> for Assembler<'a> {
241    fn vpconflictd_mask(&mut self, op0: Xmm, op1: Mem) {
242        self.emit(
243            VPCONFLICTD128RM_MASK,
244            op0.as_operand(),
245            op1.as_operand(),
246            &NOREG,
247            &NOREG,
248        );
249    }
250}
251
252impl<'a> VpconflictdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
253    fn vpconflictd_mask(&mut self, op0: Ymm, op1: Ymm) {
254        self.emit(
255            VPCONFLICTD256RR_MASK,
256            op0.as_operand(),
257            op1.as_operand(),
258            &NOREG,
259            &NOREG,
260        );
261    }
262}
263
264impl<'a> VpconflictdMaskEmitter<Ymm, Mem> for Assembler<'a> {
265    fn vpconflictd_mask(&mut self, op0: Ymm, op1: Mem) {
266        self.emit(
267            VPCONFLICTD256RM_MASK,
268            op0.as_operand(),
269            op1.as_operand(),
270            &NOREG,
271            &NOREG,
272        );
273    }
274}
275
276impl<'a> VpconflictdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
277    fn vpconflictd_mask(&mut self, op0: Zmm, op1: Zmm) {
278        self.emit(
279            VPCONFLICTD512RR_MASK,
280            op0.as_operand(),
281            op1.as_operand(),
282            &NOREG,
283            &NOREG,
284        );
285    }
286}
287
288impl<'a> VpconflictdMaskEmitter<Zmm, Mem> for Assembler<'a> {
289    fn vpconflictd_mask(&mut self, op0: Zmm, op1: Mem) {
290        self.emit(
291            VPCONFLICTD512RM_MASK,
292            op0.as_operand(),
293            op1.as_operand(),
294            &NOREG,
295            &NOREG,
296        );
297    }
298}
299
300/// `VPCONFLICTD_MASKZ`.
301///
302/// Supported operand variants:
303///
304/// ```text
305/// +---+----------+
306/// | # | Operands |
307/// +---+----------+
308/// | 1 | Xmm, Mem |
309/// | 2 | Xmm, Xmm |
310/// | 3 | Ymm, Mem |
311/// | 4 | Ymm, Ymm |
312/// | 5 | Zmm, Mem |
313/// | 6 | Zmm, Zmm |
314/// +---+----------+
315/// ```
316pub trait VpconflictdMaskzEmitter<A, B> {
317    fn vpconflictd_maskz(&mut self, op0: A, op1: B);
318}
319
320impl<'a> VpconflictdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
321    fn vpconflictd_maskz(&mut self, op0: Xmm, op1: Xmm) {
322        self.emit(
323            VPCONFLICTD128RR_MASKZ,
324            op0.as_operand(),
325            op1.as_operand(),
326            &NOREG,
327            &NOREG,
328        );
329    }
330}
331
332impl<'a> VpconflictdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
333    fn vpconflictd_maskz(&mut self, op0: Xmm, op1: Mem) {
334        self.emit(
335            VPCONFLICTD128RM_MASKZ,
336            op0.as_operand(),
337            op1.as_operand(),
338            &NOREG,
339            &NOREG,
340        );
341    }
342}
343
344impl<'a> VpconflictdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
345    fn vpconflictd_maskz(&mut self, op0: Ymm, op1: Ymm) {
346        self.emit(
347            VPCONFLICTD256RR_MASKZ,
348            op0.as_operand(),
349            op1.as_operand(),
350            &NOREG,
351            &NOREG,
352        );
353    }
354}
355
356impl<'a> VpconflictdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
357    fn vpconflictd_maskz(&mut self, op0: Ymm, op1: Mem) {
358        self.emit(
359            VPCONFLICTD256RM_MASKZ,
360            op0.as_operand(),
361            op1.as_operand(),
362            &NOREG,
363            &NOREG,
364        );
365    }
366}
367
368impl<'a> VpconflictdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
369    fn vpconflictd_maskz(&mut self, op0: Zmm, op1: Zmm) {
370        self.emit(
371            VPCONFLICTD512RR_MASKZ,
372            op0.as_operand(),
373            op1.as_operand(),
374            &NOREG,
375            &NOREG,
376        );
377    }
378}
379
380impl<'a> VpconflictdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
381    fn vpconflictd_maskz(&mut self, op0: Zmm, op1: Mem) {
382        self.emit(
383            VPCONFLICTD512RM_MASKZ,
384            op0.as_operand(),
385            op1.as_operand(),
386            &NOREG,
387            &NOREG,
388        );
389    }
390}
391
392/// `VPCONFLICTQ`.
393///
394/// Supported operand variants:
395///
396/// ```text
397/// +---+----------+
398/// | # | Operands |
399/// +---+----------+
400/// | 1 | Xmm, Mem |
401/// | 2 | Xmm, Xmm |
402/// | 3 | Ymm, Mem |
403/// | 4 | Ymm, Ymm |
404/// | 5 | Zmm, Mem |
405/// | 6 | Zmm, Zmm |
406/// +---+----------+
407/// ```
408pub trait VpconflictqEmitter<A, B> {
409    fn vpconflictq(&mut self, op0: A, op1: B);
410}
411
412impl<'a> VpconflictqEmitter<Xmm, Xmm> for Assembler<'a> {
413    fn vpconflictq(&mut self, op0: Xmm, op1: Xmm) {
414        self.emit(
415            VPCONFLICTQ128RR,
416            op0.as_operand(),
417            op1.as_operand(),
418            &NOREG,
419            &NOREG,
420        );
421    }
422}
423
424impl<'a> VpconflictqEmitter<Xmm, Mem> for Assembler<'a> {
425    fn vpconflictq(&mut self, op0: Xmm, op1: Mem) {
426        self.emit(
427            VPCONFLICTQ128RM,
428            op0.as_operand(),
429            op1.as_operand(),
430            &NOREG,
431            &NOREG,
432        );
433    }
434}
435
436impl<'a> VpconflictqEmitter<Ymm, Ymm> for Assembler<'a> {
437    fn vpconflictq(&mut self, op0: Ymm, op1: Ymm) {
438        self.emit(
439            VPCONFLICTQ256RR,
440            op0.as_operand(),
441            op1.as_operand(),
442            &NOREG,
443            &NOREG,
444        );
445    }
446}
447
448impl<'a> VpconflictqEmitter<Ymm, Mem> for Assembler<'a> {
449    fn vpconflictq(&mut self, op0: Ymm, op1: Mem) {
450        self.emit(
451            VPCONFLICTQ256RM,
452            op0.as_operand(),
453            op1.as_operand(),
454            &NOREG,
455            &NOREG,
456        );
457    }
458}
459
460impl<'a> VpconflictqEmitter<Zmm, Zmm> for Assembler<'a> {
461    fn vpconflictq(&mut self, op0: Zmm, op1: Zmm) {
462        self.emit(
463            VPCONFLICTQ512RR,
464            op0.as_operand(),
465            op1.as_operand(),
466            &NOREG,
467            &NOREG,
468        );
469    }
470}
471
472impl<'a> VpconflictqEmitter<Zmm, Mem> for Assembler<'a> {
473    fn vpconflictq(&mut self, op0: Zmm, op1: Mem) {
474        self.emit(
475            VPCONFLICTQ512RM,
476            op0.as_operand(),
477            op1.as_operand(),
478            &NOREG,
479            &NOREG,
480        );
481    }
482}
483
484/// `VPCONFLICTQ_MASK`.
485///
486/// Supported operand variants:
487///
488/// ```text
489/// +---+----------+
490/// | # | Operands |
491/// +---+----------+
492/// | 1 | Xmm, Mem |
493/// | 2 | Xmm, Xmm |
494/// | 3 | Ymm, Mem |
495/// | 4 | Ymm, Ymm |
496/// | 5 | Zmm, Mem |
497/// | 6 | Zmm, Zmm |
498/// +---+----------+
499/// ```
500pub trait VpconflictqMaskEmitter<A, B> {
501    fn vpconflictq_mask(&mut self, op0: A, op1: B);
502}
503
504impl<'a> VpconflictqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
505    fn vpconflictq_mask(&mut self, op0: Xmm, op1: Xmm) {
506        self.emit(
507            VPCONFLICTQ128RR_MASK,
508            op0.as_operand(),
509            op1.as_operand(),
510            &NOREG,
511            &NOREG,
512        );
513    }
514}
515
516impl<'a> VpconflictqMaskEmitter<Xmm, Mem> for Assembler<'a> {
517    fn vpconflictq_mask(&mut self, op0: Xmm, op1: Mem) {
518        self.emit(
519            VPCONFLICTQ128RM_MASK,
520            op0.as_operand(),
521            op1.as_operand(),
522            &NOREG,
523            &NOREG,
524        );
525    }
526}
527
528impl<'a> VpconflictqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
529    fn vpconflictq_mask(&mut self, op0: Ymm, op1: Ymm) {
530        self.emit(
531            VPCONFLICTQ256RR_MASK,
532            op0.as_operand(),
533            op1.as_operand(),
534            &NOREG,
535            &NOREG,
536        );
537    }
538}
539
540impl<'a> VpconflictqMaskEmitter<Ymm, Mem> for Assembler<'a> {
541    fn vpconflictq_mask(&mut self, op0: Ymm, op1: Mem) {
542        self.emit(
543            VPCONFLICTQ256RM_MASK,
544            op0.as_operand(),
545            op1.as_operand(),
546            &NOREG,
547            &NOREG,
548        );
549    }
550}
551
552impl<'a> VpconflictqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
553    fn vpconflictq_mask(&mut self, op0: Zmm, op1: Zmm) {
554        self.emit(
555            VPCONFLICTQ512RR_MASK,
556            op0.as_operand(),
557            op1.as_operand(),
558            &NOREG,
559            &NOREG,
560        );
561    }
562}
563
564impl<'a> VpconflictqMaskEmitter<Zmm, Mem> for Assembler<'a> {
565    fn vpconflictq_mask(&mut self, op0: Zmm, op1: Mem) {
566        self.emit(
567            VPCONFLICTQ512RM_MASK,
568            op0.as_operand(),
569            op1.as_operand(),
570            &NOREG,
571            &NOREG,
572        );
573    }
574}
575
576/// `VPCONFLICTQ_MASKZ`.
577///
578/// Supported operand variants:
579///
580/// ```text
581/// +---+----------+
582/// | # | Operands |
583/// +---+----------+
584/// | 1 | Xmm, Mem |
585/// | 2 | Xmm, Xmm |
586/// | 3 | Ymm, Mem |
587/// | 4 | Ymm, Ymm |
588/// | 5 | Zmm, Mem |
589/// | 6 | Zmm, Zmm |
590/// +---+----------+
591/// ```
592pub trait VpconflictqMaskzEmitter<A, B> {
593    fn vpconflictq_maskz(&mut self, op0: A, op1: B);
594}
595
596impl<'a> VpconflictqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
597    fn vpconflictq_maskz(&mut self, op0: Xmm, op1: Xmm) {
598        self.emit(
599            VPCONFLICTQ128RR_MASKZ,
600            op0.as_operand(),
601            op1.as_operand(),
602            &NOREG,
603            &NOREG,
604        );
605    }
606}
607
608impl<'a> VpconflictqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
609    fn vpconflictq_maskz(&mut self, op0: Xmm, op1: Mem) {
610        self.emit(
611            VPCONFLICTQ128RM_MASKZ,
612            op0.as_operand(),
613            op1.as_operand(),
614            &NOREG,
615            &NOREG,
616        );
617    }
618}
619
620impl<'a> VpconflictqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
621    fn vpconflictq_maskz(&mut self, op0: Ymm, op1: Ymm) {
622        self.emit(
623            VPCONFLICTQ256RR_MASKZ,
624            op0.as_operand(),
625            op1.as_operand(),
626            &NOREG,
627            &NOREG,
628        );
629    }
630}
631
632impl<'a> VpconflictqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
633    fn vpconflictq_maskz(&mut self, op0: Ymm, op1: Mem) {
634        self.emit(
635            VPCONFLICTQ256RM_MASKZ,
636            op0.as_operand(),
637            op1.as_operand(),
638            &NOREG,
639            &NOREG,
640        );
641    }
642}
643
644impl<'a> VpconflictqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
645    fn vpconflictq_maskz(&mut self, op0: Zmm, op1: Zmm) {
646        self.emit(
647            VPCONFLICTQ512RR_MASKZ,
648            op0.as_operand(),
649            op1.as_operand(),
650            &NOREG,
651            &NOREG,
652        );
653    }
654}
655
656impl<'a> VpconflictqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
657    fn vpconflictq_maskz(&mut self, op0: Zmm, op1: Mem) {
658        self.emit(
659            VPCONFLICTQ512RM_MASKZ,
660            op0.as_operand(),
661            op1.as_operand(),
662            &NOREG,
663            &NOREG,
664        );
665    }
666}
667
668/// `VPLZCNTD`.
669///
670/// Supported operand variants:
671///
672/// ```text
673/// +---+----------+
674/// | # | Operands |
675/// +---+----------+
676/// | 1 | Xmm, Mem |
677/// | 2 | Xmm, Xmm |
678/// | 3 | Ymm, Mem |
679/// | 4 | Ymm, Ymm |
680/// | 5 | Zmm, Mem |
681/// | 6 | Zmm, Zmm |
682/// +---+----------+
683/// ```
684pub trait VplzcntdEmitter<A, B> {
685    fn vplzcntd(&mut self, op0: A, op1: B);
686}
687
688impl<'a> VplzcntdEmitter<Xmm, Xmm> for Assembler<'a> {
689    fn vplzcntd(&mut self, op0: Xmm, op1: Xmm) {
690        self.emit(
691            VPLZCNTD128RR,
692            op0.as_operand(),
693            op1.as_operand(),
694            &NOREG,
695            &NOREG,
696        );
697    }
698}
699
700impl<'a> VplzcntdEmitter<Xmm, Mem> for Assembler<'a> {
701    fn vplzcntd(&mut self, op0: Xmm, op1: Mem) {
702        self.emit(
703            VPLZCNTD128RM,
704            op0.as_operand(),
705            op1.as_operand(),
706            &NOREG,
707            &NOREG,
708        );
709    }
710}
711
712impl<'a> VplzcntdEmitter<Ymm, Ymm> for Assembler<'a> {
713    fn vplzcntd(&mut self, op0: Ymm, op1: Ymm) {
714        self.emit(
715            VPLZCNTD256RR,
716            op0.as_operand(),
717            op1.as_operand(),
718            &NOREG,
719            &NOREG,
720        );
721    }
722}
723
724impl<'a> VplzcntdEmitter<Ymm, Mem> for Assembler<'a> {
725    fn vplzcntd(&mut self, op0: Ymm, op1: Mem) {
726        self.emit(
727            VPLZCNTD256RM,
728            op0.as_operand(),
729            op1.as_operand(),
730            &NOREG,
731            &NOREG,
732        );
733    }
734}
735
736impl<'a> VplzcntdEmitter<Zmm, Zmm> for Assembler<'a> {
737    fn vplzcntd(&mut self, op0: Zmm, op1: Zmm) {
738        self.emit(
739            VPLZCNTD512RR,
740            op0.as_operand(),
741            op1.as_operand(),
742            &NOREG,
743            &NOREG,
744        );
745    }
746}
747
748impl<'a> VplzcntdEmitter<Zmm, Mem> for Assembler<'a> {
749    fn vplzcntd(&mut self, op0: Zmm, op1: Mem) {
750        self.emit(
751            VPLZCNTD512RM,
752            op0.as_operand(),
753            op1.as_operand(),
754            &NOREG,
755            &NOREG,
756        );
757    }
758}
759
760/// `VPLZCNTD_MASK`.
761///
762/// Supported operand variants:
763///
764/// ```text
765/// +---+----------+
766/// | # | Operands |
767/// +---+----------+
768/// | 1 | Xmm, Mem |
769/// | 2 | Xmm, Xmm |
770/// | 3 | Ymm, Mem |
771/// | 4 | Ymm, Ymm |
772/// | 5 | Zmm, Mem |
773/// | 6 | Zmm, Zmm |
774/// +---+----------+
775/// ```
776pub trait VplzcntdMaskEmitter<A, B> {
777    fn vplzcntd_mask(&mut self, op0: A, op1: B);
778}
779
780impl<'a> VplzcntdMaskEmitter<Xmm, Xmm> for Assembler<'a> {
781    fn vplzcntd_mask(&mut self, op0: Xmm, op1: Xmm) {
782        self.emit(
783            VPLZCNTD128RR_MASK,
784            op0.as_operand(),
785            op1.as_operand(),
786            &NOREG,
787            &NOREG,
788        );
789    }
790}
791
792impl<'a> VplzcntdMaskEmitter<Xmm, Mem> for Assembler<'a> {
793    fn vplzcntd_mask(&mut self, op0: Xmm, op1: Mem) {
794        self.emit(
795            VPLZCNTD128RM_MASK,
796            op0.as_operand(),
797            op1.as_operand(),
798            &NOREG,
799            &NOREG,
800        );
801    }
802}
803
804impl<'a> VplzcntdMaskEmitter<Ymm, Ymm> for Assembler<'a> {
805    fn vplzcntd_mask(&mut self, op0: Ymm, op1: Ymm) {
806        self.emit(
807            VPLZCNTD256RR_MASK,
808            op0.as_operand(),
809            op1.as_operand(),
810            &NOREG,
811            &NOREG,
812        );
813    }
814}
815
816impl<'a> VplzcntdMaskEmitter<Ymm, Mem> for Assembler<'a> {
817    fn vplzcntd_mask(&mut self, op0: Ymm, op1: Mem) {
818        self.emit(
819            VPLZCNTD256RM_MASK,
820            op0.as_operand(),
821            op1.as_operand(),
822            &NOREG,
823            &NOREG,
824        );
825    }
826}
827
828impl<'a> VplzcntdMaskEmitter<Zmm, Zmm> for Assembler<'a> {
829    fn vplzcntd_mask(&mut self, op0: Zmm, op1: Zmm) {
830        self.emit(
831            VPLZCNTD512RR_MASK,
832            op0.as_operand(),
833            op1.as_operand(),
834            &NOREG,
835            &NOREG,
836        );
837    }
838}
839
840impl<'a> VplzcntdMaskEmitter<Zmm, Mem> for Assembler<'a> {
841    fn vplzcntd_mask(&mut self, op0: Zmm, op1: Mem) {
842        self.emit(
843            VPLZCNTD512RM_MASK,
844            op0.as_operand(),
845            op1.as_operand(),
846            &NOREG,
847            &NOREG,
848        );
849    }
850}
851
852/// `VPLZCNTD_MASKZ`.
853///
854/// Supported operand variants:
855///
856/// ```text
857/// +---+----------+
858/// | # | Operands |
859/// +---+----------+
860/// | 1 | Xmm, Mem |
861/// | 2 | Xmm, Xmm |
862/// | 3 | Ymm, Mem |
863/// | 4 | Ymm, Ymm |
864/// | 5 | Zmm, Mem |
865/// | 6 | Zmm, Zmm |
866/// +---+----------+
867/// ```
868pub trait VplzcntdMaskzEmitter<A, B> {
869    fn vplzcntd_maskz(&mut self, op0: A, op1: B);
870}
871
872impl<'a> VplzcntdMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
873    fn vplzcntd_maskz(&mut self, op0: Xmm, op1: Xmm) {
874        self.emit(
875            VPLZCNTD128RR_MASKZ,
876            op0.as_operand(),
877            op1.as_operand(),
878            &NOREG,
879            &NOREG,
880        );
881    }
882}
883
884impl<'a> VplzcntdMaskzEmitter<Xmm, Mem> for Assembler<'a> {
885    fn vplzcntd_maskz(&mut self, op0: Xmm, op1: Mem) {
886        self.emit(
887            VPLZCNTD128RM_MASKZ,
888            op0.as_operand(),
889            op1.as_operand(),
890            &NOREG,
891            &NOREG,
892        );
893    }
894}
895
896impl<'a> VplzcntdMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
897    fn vplzcntd_maskz(&mut self, op0: Ymm, op1: Ymm) {
898        self.emit(
899            VPLZCNTD256RR_MASKZ,
900            op0.as_operand(),
901            op1.as_operand(),
902            &NOREG,
903            &NOREG,
904        );
905    }
906}
907
908impl<'a> VplzcntdMaskzEmitter<Ymm, Mem> for Assembler<'a> {
909    fn vplzcntd_maskz(&mut self, op0: Ymm, op1: Mem) {
910        self.emit(
911            VPLZCNTD256RM_MASKZ,
912            op0.as_operand(),
913            op1.as_operand(),
914            &NOREG,
915            &NOREG,
916        );
917    }
918}
919
920impl<'a> VplzcntdMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
921    fn vplzcntd_maskz(&mut self, op0: Zmm, op1: Zmm) {
922        self.emit(
923            VPLZCNTD512RR_MASKZ,
924            op0.as_operand(),
925            op1.as_operand(),
926            &NOREG,
927            &NOREG,
928        );
929    }
930}
931
932impl<'a> VplzcntdMaskzEmitter<Zmm, Mem> for Assembler<'a> {
933    fn vplzcntd_maskz(&mut self, op0: Zmm, op1: Mem) {
934        self.emit(
935            VPLZCNTD512RM_MASKZ,
936            op0.as_operand(),
937            op1.as_operand(),
938            &NOREG,
939            &NOREG,
940        );
941    }
942}
943
944/// `VPLZCNTQ`.
945///
946/// Supported operand variants:
947///
948/// ```text
949/// +---+----------+
950/// | # | Operands |
951/// +---+----------+
952/// | 1 | Xmm, Mem |
953/// | 2 | Xmm, Xmm |
954/// | 3 | Ymm, Mem |
955/// | 4 | Ymm, Ymm |
956/// | 5 | Zmm, Mem |
957/// | 6 | Zmm, Zmm |
958/// +---+----------+
959/// ```
960pub trait VplzcntqEmitter<A, B> {
961    fn vplzcntq(&mut self, op0: A, op1: B);
962}
963
964impl<'a> VplzcntqEmitter<Xmm, Xmm> for Assembler<'a> {
965    fn vplzcntq(&mut self, op0: Xmm, op1: Xmm) {
966        self.emit(
967            VPLZCNTQ128RR,
968            op0.as_operand(),
969            op1.as_operand(),
970            &NOREG,
971            &NOREG,
972        );
973    }
974}
975
976impl<'a> VplzcntqEmitter<Xmm, Mem> for Assembler<'a> {
977    fn vplzcntq(&mut self, op0: Xmm, op1: Mem) {
978        self.emit(
979            VPLZCNTQ128RM,
980            op0.as_operand(),
981            op1.as_operand(),
982            &NOREG,
983            &NOREG,
984        );
985    }
986}
987
988impl<'a> VplzcntqEmitter<Ymm, Ymm> for Assembler<'a> {
989    fn vplzcntq(&mut self, op0: Ymm, op1: Ymm) {
990        self.emit(
991            VPLZCNTQ256RR,
992            op0.as_operand(),
993            op1.as_operand(),
994            &NOREG,
995            &NOREG,
996        );
997    }
998}
999
1000impl<'a> VplzcntqEmitter<Ymm, Mem> for Assembler<'a> {
1001    fn vplzcntq(&mut self, op0: Ymm, op1: Mem) {
1002        self.emit(
1003            VPLZCNTQ256RM,
1004            op0.as_operand(),
1005            op1.as_operand(),
1006            &NOREG,
1007            &NOREG,
1008        );
1009    }
1010}
1011
1012impl<'a> VplzcntqEmitter<Zmm, Zmm> for Assembler<'a> {
1013    fn vplzcntq(&mut self, op0: Zmm, op1: Zmm) {
1014        self.emit(
1015            VPLZCNTQ512RR,
1016            op0.as_operand(),
1017            op1.as_operand(),
1018            &NOREG,
1019            &NOREG,
1020        );
1021    }
1022}
1023
1024impl<'a> VplzcntqEmitter<Zmm, Mem> for Assembler<'a> {
1025    fn vplzcntq(&mut self, op0: Zmm, op1: Mem) {
1026        self.emit(
1027            VPLZCNTQ512RM,
1028            op0.as_operand(),
1029            op1.as_operand(),
1030            &NOREG,
1031            &NOREG,
1032        );
1033    }
1034}
1035
1036/// `VPLZCNTQ_MASK`.
1037///
1038/// Supported operand variants:
1039///
1040/// ```text
1041/// +---+----------+
1042/// | # | Operands |
1043/// +---+----------+
1044/// | 1 | Xmm, Mem |
1045/// | 2 | Xmm, Xmm |
1046/// | 3 | Ymm, Mem |
1047/// | 4 | Ymm, Ymm |
1048/// | 5 | Zmm, Mem |
1049/// | 6 | Zmm, Zmm |
1050/// +---+----------+
1051/// ```
1052pub trait VplzcntqMaskEmitter<A, B> {
1053    fn vplzcntq_mask(&mut self, op0: A, op1: B);
1054}
1055
1056impl<'a> VplzcntqMaskEmitter<Xmm, Xmm> for Assembler<'a> {
1057    fn vplzcntq_mask(&mut self, op0: Xmm, op1: Xmm) {
1058        self.emit(
1059            VPLZCNTQ128RR_MASK,
1060            op0.as_operand(),
1061            op1.as_operand(),
1062            &NOREG,
1063            &NOREG,
1064        );
1065    }
1066}
1067
1068impl<'a> VplzcntqMaskEmitter<Xmm, Mem> for Assembler<'a> {
1069    fn vplzcntq_mask(&mut self, op0: Xmm, op1: Mem) {
1070        self.emit(
1071            VPLZCNTQ128RM_MASK,
1072            op0.as_operand(),
1073            op1.as_operand(),
1074            &NOREG,
1075            &NOREG,
1076        );
1077    }
1078}
1079
1080impl<'a> VplzcntqMaskEmitter<Ymm, Ymm> for Assembler<'a> {
1081    fn vplzcntq_mask(&mut self, op0: Ymm, op1: Ymm) {
1082        self.emit(
1083            VPLZCNTQ256RR_MASK,
1084            op0.as_operand(),
1085            op1.as_operand(),
1086            &NOREG,
1087            &NOREG,
1088        );
1089    }
1090}
1091
1092impl<'a> VplzcntqMaskEmitter<Ymm, Mem> for Assembler<'a> {
1093    fn vplzcntq_mask(&mut self, op0: Ymm, op1: Mem) {
1094        self.emit(
1095            VPLZCNTQ256RM_MASK,
1096            op0.as_operand(),
1097            op1.as_operand(),
1098            &NOREG,
1099            &NOREG,
1100        );
1101    }
1102}
1103
1104impl<'a> VplzcntqMaskEmitter<Zmm, Zmm> for Assembler<'a> {
1105    fn vplzcntq_mask(&mut self, op0: Zmm, op1: Zmm) {
1106        self.emit(
1107            VPLZCNTQ512RR_MASK,
1108            op0.as_operand(),
1109            op1.as_operand(),
1110            &NOREG,
1111            &NOREG,
1112        );
1113    }
1114}
1115
1116impl<'a> VplzcntqMaskEmitter<Zmm, Mem> for Assembler<'a> {
1117    fn vplzcntq_mask(&mut self, op0: Zmm, op1: Mem) {
1118        self.emit(
1119            VPLZCNTQ512RM_MASK,
1120            op0.as_operand(),
1121            op1.as_operand(),
1122            &NOREG,
1123            &NOREG,
1124        );
1125    }
1126}
1127
1128/// `VPLZCNTQ_MASKZ`.
1129///
1130/// Supported operand variants:
1131///
1132/// ```text
1133/// +---+----------+
1134/// | # | Operands |
1135/// +---+----------+
1136/// | 1 | Xmm, Mem |
1137/// | 2 | Xmm, Xmm |
1138/// | 3 | Ymm, Mem |
1139/// | 4 | Ymm, Ymm |
1140/// | 5 | Zmm, Mem |
1141/// | 6 | Zmm, Zmm |
1142/// +---+----------+
1143/// ```
1144pub trait VplzcntqMaskzEmitter<A, B> {
1145    fn vplzcntq_maskz(&mut self, op0: A, op1: B);
1146}
1147
1148impl<'a> VplzcntqMaskzEmitter<Xmm, Xmm> for Assembler<'a> {
1149    fn vplzcntq_maskz(&mut self, op0: Xmm, op1: Xmm) {
1150        self.emit(
1151            VPLZCNTQ128RR_MASKZ,
1152            op0.as_operand(),
1153            op1.as_operand(),
1154            &NOREG,
1155            &NOREG,
1156        );
1157    }
1158}
1159
1160impl<'a> VplzcntqMaskzEmitter<Xmm, Mem> for Assembler<'a> {
1161    fn vplzcntq_maskz(&mut self, op0: Xmm, op1: Mem) {
1162        self.emit(
1163            VPLZCNTQ128RM_MASKZ,
1164            op0.as_operand(),
1165            op1.as_operand(),
1166            &NOREG,
1167            &NOREG,
1168        );
1169    }
1170}
1171
1172impl<'a> VplzcntqMaskzEmitter<Ymm, Ymm> for Assembler<'a> {
1173    fn vplzcntq_maskz(&mut self, op0: Ymm, op1: Ymm) {
1174        self.emit(
1175            VPLZCNTQ256RR_MASKZ,
1176            op0.as_operand(),
1177            op1.as_operand(),
1178            &NOREG,
1179            &NOREG,
1180        );
1181    }
1182}
1183
1184impl<'a> VplzcntqMaskzEmitter<Ymm, Mem> for Assembler<'a> {
1185    fn vplzcntq_maskz(&mut self, op0: Ymm, op1: Mem) {
1186        self.emit(
1187            VPLZCNTQ256RM_MASKZ,
1188            op0.as_operand(),
1189            op1.as_operand(),
1190            &NOREG,
1191            &NOREG,
1192        );
1193    }
1194}
1195
1196impl<'a> VplzcntqMaskzEmitter<Zmm, Zmm> for Assembler<'a> {
1197    fn vplzcntq_maskz(&mut self, op0: Zmm, op1: Zmm) {
1198        self.emit(
1199            VPLZCNTQ512RR_MASKZ,
1200            op0.as_operand(),
1201            op1.as_operand(),
1202            &NOREG,
1203            &NOREG,
1204        );
1205    }
1206}
1207
1208impl<'a> VplzcntqMaskzEmitter<Zmm, Mem> for Assembler<'a> {
1209    fn vplzcntq_maskz(&mut self, op0: Zmm, op1: Mem) {
1210        self.emit(
1211            VPLZCNTQ512RM_MASKZ,
1212            op0.as_operand(),
1213            op1.as_operand(),
1214            &NOREG,
1215            &NOREG,
1216        );
1217    }
1218}
1219
1220impl<'a> Assembler<'a> {
1221    /// `VPBROADCASTMB2Q`.
1222    ///
1223    /// Supported operand variants:
1224    ///
1225    /// ```text
1226    /// +---+-----------+
1227    /// | # | Operands  |
1228    /// +---+-----------+
1229    /// | 1 | Xmm, KReg |
1230    /// | 2 | Ymm, KReg |
1231    /// | 3 | Zmm, KReg |
1232    /// +---+-----------+
1233    /// ```
1234    #[inline]
1235    pub fn vpbroadcastmb2q<A, B>(&mut self, op0: A, op1: B)
1236    where
1237        Assembler<'a>: Vpbroadcastmb2qEmitter<A, B>,
1238    {
1239        <Self as Vpbroadcastmb2qEmitter<A, B>>::vpbroadcastmb2q(self, op0, op1);
1240    }
1241    /// `VPBROADCASTMW2D`.
1242    ///
1243    /// Supported operand variants:
1244    ///
1245    /// ```text
1246    /// +---+-----------+
1247    /// | # | Operands  |
1248    /// +---+-----------+
1249    /// | 1 | Xmm, KReg |
1250    /// | 2 | Ymm, KReg |
1251    /// | 3 | Zmm, KReg |
1252    /// +---+-----------+
1253    /// ```
1254    #[inline]
1255    pub fn vpbroadcastmw2d<A, B>(&mut self, op0: A, op1: B)
1256    where
1257        Assembler<'a>: Vpbroadcastmw2dEmitter<A, B>,
1258    {
1259        <Self as Vpbroadcastmw2dEmitter<A, B>>::vpbroadcastmw2d(self, op0, op1);
1260    }
1261    /// `VPCONFLICTD`.
1262    ///
1263    /// Supported operand variants:
1264    ///
1265    /// ```text
1266    /// +---+----------+
1267    /// | # | Operands |
1268    /// +---+----------+
1269    /// | 1 | Xmm, Mem |
1270    /// | 2 | Xmm, Xmm |
1271    /// | 3 | Ymm, Mem |
1272    /// | 4 | Ymm, Ymm |
1273    /// | 5 | Zmm, Mem |
1274    /// | 6 | Zmm, Zmm |
1275    /// +---+----------+
1276    /// ```
1277    #[inline]
1278    pub fn vpconflictd<A, B>(&mut self, op0: A, op1: B)
1279    where
1280        Assembler<'a>: VpconflictdEmitter<A, B>,
1281    {
1282        <Self as VpconflictdEmitter<A, B>>::vpconflictd(self, op0, op1);
1283    }
1284    /// `VPCONFLICTD_MASK`.
1285    ///
1286    /// Supported operand variants:
1287    ///
1288    /// ```text
1289    /// +---+----------+
1290    /// | # | Operands |
1291    /// +---+----------+
1292    /// | 1 | Xmm, Mem |
1293    /// | 2 | Xmm, Xmm |
1294    /// | 3 | Ymm, Mem |
1295    /// | 4 | Ymm, Ymm |
1296    /// | 5 | Zmm, Mem |
1297    /// | 6 | Zmm, Zmm |
1298    /// +---+----------+
1299    /// ```
1300    #[inline]
1301    pub fn vpconflictd_mask<A, B>(&mut self, op0: A, op1: B)
1302    where
1303        Assembler<'a>: VpconflictdMaskEmitter<A, B>,
1304    {
1305        <Self as VpconflictdMaskEmitter<A, B>>::vpconflictd_mask(self, op0, op1);
1306    }
1307    /// `VPCONFLICTD_MASKZ`.
1308    ///
1309    /// Supported operand variants:
1310    ///
1311    /// ```text
1312    /// +---+----------+
1313    /// | # | Operands |
1314    /// +---+----------+
1315    /// | 1 | Xmm, Mem |
1316    /// | 2 | Xmm, Xmm |
1317    /// | 3 | Ymm, Mem |
1318    /// | 4 | Ymm, Ymm |
1319    /// | 5 | Zmm, Mem |
1320    /// | 6 | Zmm, Zmm |
1321    /// +---+----------+
1322    /// ```
1323    #[inline]
1324    pub fn vpconflictd_maskz<A, B>(&mut self, op0: A, op1: B)
1325    where
1326        Assembler<'a>: VpconflictdMaskzEmitter<A, B>,
1327    {
1328        <Self as VpconflictdMaskzEmitter<A, B>>::vpconflictd_maskz(self, op0, op1);
1329    }
1330    /// `VPCONFLICTQ`.
1331    ///
1332    /// Supported operand variants:
1333    ///
1334    /// ```text
1335    /// +---+----------+
1336    /// | # | Operands |
1337    /// +---+----------+
1338    /// | 1 | Xmm, Mem |
1339    /// | 2 | Xmm, Xmm |
1340    /// | 3 | Ymm, Mem |
1341    /// | 4 | Ymm, Ymm |
1342    /// | 5 | Zmm, Mem |
1343    /// | 6 | Zmm, Zmm |
1344    /// +---+----------+
1345    /// ```
1346    #[inline]
1347    pub fn vpconflictq<A, B>(&mut self, op0: A, op1: B)
1348    where
1349        Assembler<'a>: VpconflictqEmitter<A, B>,
1350    {
1351        <Self as VpconflictqEmitter<A, B>>::vpconflictq(self, op0, op1);
1352    }
1353    /// `VPCONFLICTQ_MASK`.
1354    ///
1355    /// Supported operand variants:
1356    ///
1357    /// ```text
1358    /// +---+----------+
1359    /// | # | Operands |
1360    /// +---+----------+
1361    /// | 1 | Xmm, Mem |
1362    /// | 2 | Xmm, Xmm |
1363    /// | 3 | Ymm, Mem |
1364    /// | 4 | Ymm, Ymm |
1365    /// | 5 | Zmm, Mem |
1366    /// | 6 | Zmm, Zmm |
1367    /// +---+----------+
1368    /// ```
1369    #[inline]
1370    pub fn vpconflictq_mask<A, B>(&mut self, op0: A, op1: B)
1371    where
1372        Assembler<'a>: VpconflictqMaskEmitter<A, B>,
1373    {
1374        <Self as VpconflictqMaskEmitter<A, B>>::vpconflictq_mask(self, op0, op1);
1375    }
1376    /// `VPCONFLICTQ_MASKZ`.
1377    ///
1378    /// Supported operand variants:
1379    ///
1380    /// ```text
1381    /// +---+----------+
1382    /// | # | Operands |
1383    /// +---+----------+
1384    /// | 1 | Xmm, Mem |
1385    /// | 2 | Xmm, Xmm |
1386    /// | 3 | Ymm, Mem |
1387    /// | 4 | Ymm, Ymm |
1388    /// | 5 | Zmm, Mem |
1389    /// | 6 | Zmm, Zmm |
1390    /// +---+----------+
1391    /// ```
1392    #[inline]
1393    pub fn vpconflictq_maskz<A, B>(&mut self, op0: A, op1: B)
1394    where
1395        Assembler<'a>: VpconflictqMaskzEmitter<A, B>,
1396    {
1397        <Self as VpconflictqMaskzEmitter<A, B>>::vpconflictq_maskz(self, op0, op1);
1398    }
1399    /// `VPLZCNTD`.
1400    ///
1401    /// Supported operand variants:
1402    ///
1403    /// ```text
1404    /// +---+----------+
1405    /// | # | Operands |
1406    /// +---+----------+
1407    /// | 1 | Xmm, Mem |
1408    /// | 2 | Xmm, Xmm |
1409    /// | 3 | Ymm, Mem |
1410    /// | 4 | Ymm, Ymm |
1411    /// | 5 | Zmm, Mem |
1412    /// | 6 | Zmm, Zmm |
1413    /// +---+----------+
1414    /// ```
1415    #[inline]
1416    pub fn vplzcntd<A, B>(&mut self, op0: A, op1: B)
1417    where
1418        Assembler<'a>: VplzcntdEmitter<A, B>,
1419    {
1420        <Self as VplzcntdEmitter<A, B>>::vplzcntd(self, op0, op1);
1421    }
1422    /// `VPLZCNTD_MASK`.
1423    ///
1424    /// Supported operand variants:
1425    ///
1426    /// ```text
1427    /// +---+----------+
1428    /// | # | Operands |
1429    /// +---+----------+
1430    /// | 1 | Xmm, Mem |
1431    /// | 2 | Xmm, Xmm |
1432    /// | 3 | Ymm, Mem |
1433    /// | 4 | Ymm, Ymm |
1434    /// | 5 | Zmm, Mem |
1435    /// | 6 | Zmm, Zmm |
1436    /// +---+----------+
1437    /// ```
1438    #[inline]
1439    pub fn vplzcntd_mask<A, B>(&mut self, op0: A, op1: B)
1440    where
1441        Assembler<'a>: VplzcntdMaskEmitter<A, B>,
1442    {
1443        <Self as VplzcntdMaskEmitter<A, B>>::vplzcntd_mask(self, op0, op1);
1444    }
1445    /// `VPLZCNTD_MASKZ`.
1446    ///
1447    /// Supported operand variants:
1448    ///
1449    /// ```text
1450    /// +---+----------+
1451    /// | # | Operands |
1452    /// +---+----------+
1453    /// | 1 | Xmm, Mem |
1454    /// | 2 | Xmm, Xmm |
1455    /// | 3 | Ymm, Mem |
1456    /// | 4 | Ymm, Ymm |
1457    /// | 5 | Zmm, Mem |
1458    /// | 6 | Zmm, Zmm |
1459    /// +---+----------+
1460    /// ```
1461    #[inline]
1462    pub fn vplzcntd_maskz<A, B>(&mut self, op0: A, op1: B)
1463    where
1464        Assembler<'a>: VplzcntdMaskzEmitter<A, B>,
1465    {
1466        <Self as VplzcntdMaskzEmitter<A, B>>::vplzcntd_maskz(self, op0, op1);
1467    }
1468    /// `VPLZCNTQ`.
1469    ///
1470    /// Supported operand variants:
1471    ///
1472    /// ```text
1473    /// +---+----------+
1474    /// | # | Operands |
1475    /// +---+----------+
1476    /// | 1 | Xmm, Mem |
1477    /// | 2 | Xmm, Xmm |
1478    /// | 3 | Ymm, Mem |
1479    /// | 4 | Ymm, Ymm |
1480    /// | 5 | Zmm, Mem |
1481    /// | 6 | Zmm, Zmm |
1482    /// +---+----------+
1483    /// ```
1484    #[inline]
1485    pub fn vplzcntq<A, B>(&mut self, op0: A, op1: B)
1486    where
1487        Assembler<'a>: VplzcntqEmitter<A, B>,
1488    {
1489        <Self as VplzcntqEmitter<A, B>>::vplzcntq(self, op0, op1);
1490    }
1491    /// `VPLZCNTQ_MASK`.
1492    ///
1493    /// Supported operand variants:
1494    ///
1495    /// ```text
1496    /// +---+----------+
1497    /// | # | Operands |
1498    /// +---+----------+
1499    /// | 1 | Xmm, Mem |
1500    /// | 2 | Xmm, Xmm |
1501    /// | 3 | Ymm, Mem |
1502    /// | 4 | Ymm, Ymm |
1503    /// | 5 | Zmm, Mem |
1504    /// | 6 | Zmm, Zmm |
1505    /// +---+----------+
1506    /// ```
1507    #[inline]
1508    pub fn vplzcntq_mask<A, B>(&mut self, op0: A, op1: B)
1509    where
1510        Assembler<'a>: VplzcntqMaskEmitter<A, B>,
1511    {
1512        <Self as VplzcntqMaskEmitter<A, B>>::vplzcntq_mask(self, op0, op1);
1513    }
1514    /// `VPLZCNTQ_MASKZ`.
1515    ///
1516    /// Supported operand variants:
1517    ///
1518    /// ```text
1519    /// +---+----------+
1520    /// | # | Operands |
1521    /// +---+----------+
1522    /// | 1 | Xmm, Mem |
1523    /// | 2 | Xmm, Xmm |
1524    /// | 3 | Ymm, Mem |
1525    /// | 4 | Ymm, Ymm |
1526    /// | 5 | Zmm, Mem |
1527    /// | 6 | Zmm, Zmm |
1528    /// +---+----------+
1529    /// ```
1530    #[inline]
1531    pub fn vplzcntq_maskz<A, B>(&mut self, op0: A, op1: B)
1532    where
1533        Assembler<'a>: VplzcntqMaskzEmitter<A, B>,
1534    {
1535        <Self as VplzcntqMaskzEmitter<A, B>>::vplzcntq_maskz(self, op0, op1);
1536    }
1537}
asmkit/x86/features/AVX512CD.rs

asmkit/x86/features/
AVX512CD.rs
