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asmkit/aarch64/
instdb.rs

1/* Copyright (c) 2008-2024 The AsmJit Authors
2
3   This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software.
4
5   Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
6
7   The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required.
8   Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
9   This notice may not be removed or altered from any source distribution.
10*/
11
12use super::assembler::*;
13use super::operands::*;
14use crate::core::operand::RegType;
15
16pub const W: u32 = 0x1;
17pub const X: u32 = 0x2;
18pub const WX: u32 = W | X;
19
20pub const ZR: u32 = Gp::ID_ZR as u32;
21pub const SP: u32 = Gp::ID_SP as u32;
22
23#[derive(Debug, Clone, Copy, PartialEq, Eq)]
24pub enum RwInfo {
25    R,
26    RW,
27    RX,
28    RRW,
29    RWX,
30    W,
31    WRW,
32    WRX,
33    WRRW,
34    WRRX,
35    WW,
36    X,
37    XRX,
38    XXRRX,
39
40    LDn,
41    STn,
42}
43
44pub const RWI_R: u16 = RwInfo::R as u16;
45pub const RWI_RW: u16 = RwInfo::RW as u16;
46pub const RWI_RX: u16 = RwInfo::RX as u16;
47pub const RWI_RRW: u16 = RwInfo::RRW as u16;
48pub const RWI_RWX: u16 = RwInfo::RWX as u16;
49pub const RWI_W: u16 = RwInfo::W as u16;
50pub const RWI_WRW: u16 = RwInfo::WRW as u16;
51pub const RWI_WRX: u16 = RwInfo::WRX as u16;
52pub const RWI_WRRW: u16 = RwInfo::WRRW as u16;
53pub const RWI_WRRX: u16 = RwInfo::WRRX as u16;
54pub const RWI_WW: u16 = RwInfo::WW as u16;
55pub const RWI_X: u16 = RwInfo::X as u16;
56pub const RWI_XRX: u16 = RwInfo::XRX as u16;
57pub const RWI_XXRRX: u16 = RwInfo::XXRRX as u16;
58pub const RWI_LDN: u16 = RwInfo::LDn as u16;
59pub const RWI_STN: u16 = RwInfo::STn as u16;
60
61impl RwInfo {
62    pub const SPECIAL_START: Self = Self::LDn;
63}
64
65#[derive(Debug, Clone, Copy, PartialEq, Eq)]
66pub enum InstElementType {
67    None = VecElementType::None as isize,
68    B = VecElementType::B as isize,
69    H = VecElementType::H as isize,
70    S = VecElementType::S as isize,
71    D = VecElementType::D as isize,
72    _2H = VecElementType::H2 as isize,
73    _4B = VecElementType::B4 as isize,
74}
75
76#[derive(Debug, Clone, Copy, PartialEq, Eq)]
77pub enum GpType {
78    X,
79    W,
80    XSp,
81}
82
83#[derive(Debug, Clone, Copy, PartialEq, Eq)]
84#[repr(u32)]
85pub enum OpSignature {
86    GpW = Reg::signature_of(RegType::Gp32).bits,
87    GpX = Reg::signature_of(RegType::Gp64).bits,
88    B = Reg::signature_of(RegType::Vec8).bits,
89    H = Reg::signature_of(RegType::Vec16).bits,
90    S = Reg::signature_of(RegType::Vec32).bits,
91    D = Reg::signature_of(RegType::Vec64).bits,
92    Q = Reg::signature_of(RegType::Vec128).bits,
93    V8B = Self::D as u32 | Vec::SIGNATURE_ELEMENT_B,
94    V4H = Self::D as u32 | Vec::SIGNATURE_ELEMENT_H,
95    V2S = Self::D as u32 | Vec::SIGNATURE_ELEMENT_S,
96
97    V16B = Self::Q as u32 | Vec::SIGNATURE_ELEMENT_B,
98    V8H = Self::Q as u32 | Vec::SIGNATURE_ELEMENT_H,
99    V4S = Self::Q as u32 | Vec::SIGNATURE_ELEMENT_S,
100    V2D = Self::Q as u32 | Vec::SIGNATURE_ELEMENT_D,
101}
102
103#[derive(Debug, Clone, Copy, PartialEq, Eq)]
104pub enum HFConv {
105    N,
106    None,
107    A,
108    B,
109    C,
110    D,
111    Count,
112}
113
114pub enum VOType {
115    VB,
116    VBH,
117    VBH4S,
118    VBHS,
119    VBHSD2,
120    VHS,
121    VS,
122
123    VB8H4,
124    VB8H4S2,
125    VB8D1,
126    VH4S2,
127
128    VB16,
129    VB16H8,
130    VB16H8S4,
131    VB16D2,
132    VH8S4,
133    VS4,
134    VD2,
135
136    SVBHS,
137    SVB8H4S2,
138    SVHS,
139    VAny,
140    SVAny,
141
142    Count,
143}
144
145#[derive(Debug, Clone, Copy, PartialEq, Eq)]
146#[repr(u8)]
147pub enum Encoding {
148    None = 0,
149    BaseAddSub,
150    BaseAdr,
151    BaseAtDcIcTlbi,
152    BaseAtomicCasp,
153    BaseAtomicOp,
154    BaseAtomicSt,
155    BaseBfc,
156    BaseBfi,
157    BaseBfm,
158    BaseBfx,
159    BaseBranchCmp,
160    BaseBranchReg,
161    BaseBranchRel,
162    BaseBranchTst,
163    BaseCCmp,
164    BaseCInc,
165    BaseCSel,
166    BaseCSet,
167    BaseCmpCmn,
168    BaseExtend,
169    BaseExtract,
170    BaseLdSt,
171    BaseLdpStp,
172    BaseLdxp,
173    BaseLogical,
174    BaseMinMax,
175    BaseMov,
176    BaseMovKNZ,
177    BaseMrs,
178    BaseMsr,
179    BaseMvnNeg,
180    BaseOp,
181    BaseOpImm,
182    BaseOpX16,
183    BasePrfm,
184    BaseR,
185    BaseRMNoImm,
186    BaseRMSImm10,
187    BaseRMSImm9,
188    BaseRR,
189    BaseRRII,
190    BaseRRR,
191    BaseRRRR,
192    BaseRev,
193    BaseShift,
194    BaseStx,
195    BaseStxp,
196    BaseSys,
197    BaseTst,
198    FSimdPair,
199    FSimdSV,
200    FSimdVV,
201    FSimdVVV,
202    FSimdVVVV,
203    FSimdVVVe,
204    ISimdPair,
205    ISimdSV,
206    ISimdVV,
207    ISimdVVV,
208    ISimdVVVI,
209    ISimdVVVV,
210    ISimdVVVVx,
211    ISimdVVVe,
212    ISimdVVVx,
213    ISimdVVx,
214    ISimdWWV,
215    SimdBicOrr,
216    SimdCmp,
217    SimdDot,
218    SimdDup,
219    SimdFcadd,
220    SimdFccmpFccmpe,
221    SimdFcm,
222    SimdFcmla,
223    SimdFcmpFcmpe,
224    SimdFcsel,
225    SimdFcvt,
226    SimdFcvtLN,
227    SimdFcvtSV,
228    SimdFmlal,
229    SimdFmov,
230    SimdIns,
231    SimdLdNStN,
232    SimdLdSt,
233    SimdLdpStp,
234    SimdLdurStur,
235    SimdMov,
236    SimdMoviMvni,
237    SimdShift,
238    SimdShiftES,
239    SimdSm3tt,
240    SimdSmovUmov,
241    SimdSxtlUxtl,
242    SimdTblTbx,
243
244    Count,
245}
246
247impl TryFrom<u8> for Encoding {
248    type Error = ();
249
250    fn try_from(value: u8) -> Result<Self, Self::Error> {
251        // SAFETY: `Encoding` is `#[repr(u8)]`
252        unsafe {
253            if value >= Self::Count as u8 {
254                Err(())
255            } else {
256                Ok(::core::mem::transmute(value))
257            }
258        }
259    }
260}
261
262const HF_C: u32 = HFConv::C as u32;
263
264macro_rules! impl_const_new_zero {
265    ($name:ident { $($field:ident : $ty:ty),* $(,)? }) => {
266        impl $name {
267            pub const fn new($($field: $ty),*) -> Self {
268                Self {
269                    $($field),*
270                }
271            }
272        }
273    };
274}
275
276#[derive(Debug, Clone, Copy, Default)]
277pub struct BaseOp {
278    pub opcode: u32,
279}
280
281#[derive(Debug, Clone, Copy, Default)]
282pub struct BaseOpX16 {
283    pub opcode: u32,
284}
285
286#[derive(Debug, Clone, Copy, Default)]
287pub struct BaseOpImm {
288    pub opcode: u32,
289    pub imm_bits: u16,
290    pub imm_offset: u16,
291}
292
293#[derive(Debug, Clone, Copy, Default)]
294pub struct BaseR {
295    pub opcode: u32,
296    pub reg_type: u32,
297    pub reg_hi_id: u32,
298    pub r_shift: u32,
299}
300
301#[derive(Debug, Clone, Copy, Default)]
302pub struct BaseRR {
303    pub opcode: u32,
304    pub a_type: u32,
305    pub a_hi_id: u32,
306    pub a_shift: u32,
307    pub b_type: u32,
308    pub b_hi_id: u32,
309    pub b_shift: u32,
310    pub uniform: u32,
311}
312
313#[derive(Debug, Clone, Copy, Default)]
314pub struct BaseRRR {
315    opcode: u32,
316    pub a_type: u32,
317    pub a_hi_id: u32,
318    pub b_type: u32,
319    pub b_hi_id: u32,
320    pub c_type: u32,
321    pub c_hi_id: u32,
322    pub uniform: u32,
323}
324
325impl BaseRRR {
326    pub const fn opcode(&self) -> u32 {
327        self.opcode << 10
328    }
329}
330
331#[derive(Debug, Clone, Copy, Default)]
332pub struct BaseRRRR {
333    opcode: u32,
334    pub a_type: u32,
335    pub a_hi_id: u32,
336    pub b_type: u32,
337    pub b_hi_id: u32,
338    pub c_type: u32,
339    pub c_hi_id: u32,
340    pub d_type: u32,
341    pub d_hi_id: u32,
342    pub uniform: u32,
343}
344
345impl BaseRRRR {
346    pub const fn opcode(&self) -> u32 {
347        self.opcode << 10
348    }
349}
350
351#[derive(Debug, Clone, Copy, Default)]
352pub struct BaseRRII {
353    opcode: u32,
354    pub a_type: u32,
355    pub a_hi_id: u32,
356    pub b_type: u32,
357    pub b_hi_id: u32,
358    pub a_imm_size: u32,
359    pub a_imm_discard_lsb: u32,
360    pub a_imm_offset: u32,
361    pub b_imm_size: u32,
362    pub b_imm_discard_lsb: u32,
363    pub b_imm_offset: u32,
364}
365
366impl BaseRRII {
367    pub const fn opcode(&self) -> u32 {
368        self.opcode << 10
369    }
370}
371
372#[derive(Debug, Clone, Copy, Default)]
373pub struct BaseAtDcIcTlbi {
374    pub imm_verify_mask: u32,
375    pub imm_verify_data: u32,
376    pub mandatory_reg: u32,
377}
378
379#[derive(Debug, Clone, Copy, Default)]
380pub struct BaseAdcSbc {
381    pub opcode: u32,
382}
383
384#[derive(Debug, Clone, Copy, Default)]
385pub struct BaseMinMax {
386    pub register_op: u32,
387    pub immediate_op: u32,
388}
389
390#[derive(Debug, Clone, Copy, Default)]
391pub struct BaseAddSub {
392    pub shifted_op: u32,
393    pub extended_op: u32,
394    pub immediate_op: u32,
395}
396
397#[derive(Debug, Clone, Copy, Default)]
398pub struct BaseAdr {
399    opcode: u32,
400    pub offset_type: u8,
401}
402
403impl BaseAdr {
404    pub const fn opcode(&self) -> u32 {
405        self.opcode << 10
406    }
407}
408
409#[derive(Debug, Clone, Copy, Default)]
410pub struct BaseBfm {
411    pub opcode: u32,
412}
413
414#[derive(Debug, Clone, Copy, Default)]
415pub struct BaseCmpCmn {
416    pub shifted_op: u32,
417    pub extended_op: u32,
418    pub immediate_op: u32,
419}
420
421#[derive(Debug, Clone, Copy, Default)]
422pub struct BaseExtend {
423    opcode: u32,
424    pub reg_type: u32,
425    pub u: u32,
426}
427
428impl BaseExtend {
429    pub const fn opcode(&self) -> u32 {
430        self.opcode << 10
431    }
432}
433
434#[derive(Debug, Clone, Copy, Default)]
435pub struct BaseLogical {
436    pub shifted_op: u32,
437    pub immediate_op: u32,
438    pub negate_imm: u32,
439}
440
441#[derive(Debug, Clone, Copy, Default)]
442pub struct BaseMvnNeg {
443    pub opcode: u32,
444}
445
446#[derive(Debug, Clone, Copy, Default)]
447pub struct BaseShift {
448    pub register_op: u32,
449    pub immediate_op: u32,
450    pub ror: u32,
451}
452
453impl BaseShift {
454    pub const fn register_op(&self) -> u32 {
455        self.register_op << 10
456    }
457
458    pub const fn immediate_op(&self) -> u32 {
459        self.immediate_op << 10
460    }
461}
462
463#[derive(Debug, Clone, Copy, Default)]
464pub struct BaseTst {
465    pub shifted_op: u32,
466    pub immediate_op: u32,
467}
468
469#[derive(Debug, Clone, Copy, Default)]
470pub struct BaseRMNoImm {
471    opcode: u32,
472    pub reg_type: u32,
473    pub reg_hi_id: u32,
474    pub x_offset: u32,
475}
476
477impl BaseRMNoImm {
478    pub const fn opcode(&self) -> u32 {
479        self.opcode << 10
480    }
481}
482
483#[derive(Debug, Clone, Copy, Default)]
484pub struct BaseRMSImm9 {
485    pub offset_op: u32,
486    pub pre_post_op: u32,
487    pub reg_type: u32,
488    pub reg_hi_id: u32,
489    pub x_offset: u32,
490    pub imm_shift: u32,
491}
492
493impl BaseRMSImm9 {
494    pub const fn offset_op(&self) -> u32 {
495        self.offset_op << 10
496    }
497
498    pub const fn pre_post_op(&self) -> u32 {
499        self.pre_post_op << 10
500    }
501}
502
503#[derive(Debug, Clone, Copy, Default)]
504pub struct BaseRMSImm10 {
505    opcode: u32,
506    pub reg_type: u32,
507    pub reg_hi_id: u32,
508    pub x_offset: u32,
509    pub imm_shift: u32,
510}
511
512impl BaseRMSImm10 {
513    pub const fn opcode(&self) -> u32 {
514        self.opcode << 10
515    }
516}
517
518#[derive(Debug, Clone, Copy, Default)]
519pub struct BasePrfm {
520    pub register_op: u32,
521    pub s_offset_op: u32,
522    pub u_offset_op: u32,
523    pub literal_op: u32,
524}
525
526#[derive(Debug, Clone, Copy, Default)]
527pub struct BaseLdSt {
528    pub u_offset_op: u32,
529    pub pre_post_op: u32,
530    pub register_op: u32,
531    pub literal_op: u32,
532    pub reg_type: u32,
533    pub x_offset: u32,
534    pub u_offset_shift: u32,
535    pub u_alt_inst_id: u32,
536}
537
538#[derive(Debug, Clone, Copy, Default)]
539pub struct BaseLdpStp {
540    pub offset_op: u32,
541    pub pre_post_op: u32,
542    pub reg_type: u32,
543    pub x_offset: u32,
544    pub offset_shift: u32,
545}
546
547#[derive(Debug, Clone, Copy, Default)]
548pub struct BaseStx {
549    opcode: u32,
550    pub reg_type: u32,
551    pub x_offset: u32,
552}
553
554impl BaseStx {
555    pub const fn opcode(&self) -> u32 {
556        self.opcode << 10
557    }
558}
559
560#[derive(Debug, Clone, Copy, Default)]
561pub struct BaseLdxp {
562    opcode: u32,
563    pub reg_type: u32,
564    pub x_offset: u32,
565}
566
567impl BaseLdxp {
568    pub const fn opcode(&self) -> u32 {
569        self.opcode << 10
570    }
571}
572
573#[derive(Debug, Clone, Copy, Default)]
574pub struct BaseStxp {
575    opcode: u32,
576    pub reg_type: u32,
577    pub x_offset: u32,
578}
579
580impl BaseStxp {
581    pub const fn opcode(&self) -> u32 {
582        self.opcode << 10
583    }
584}
585
586#[derive(Debug, Clone, Copy, Default)]
587pub struct BaseAtomicOp {
588    opcode: u32,
589    pub reg_type: u32,
590    pub x_offset: u32,
591    pub zr_reg: u32,
592}
593
594impl BaseAtomicOp {
595    pub const fn opcode(&self) -> u32 {
596        self.opcode << 10
597    }
598}
599
600#[derive(Debug, Clone, Copy, Default)]
601pub struct BaseAtomicSt {
602    opcode: u32,
603    pub reg_type: u32,
604    pub x_offset: u32,
605}
606
607impl BaseAtomicSt {
608    pub const fn opcode(&self) -> u32 {
609        self.opcode << 10
610    }
611}
612
613#[derive(Debug, Clone, Copy, Default)]
614pub struct BaseAtomicCasp {
615    opcode: u32,
616    pub reg_type: u32,
617    pub x_offset: u32,
618}
619
620impl BaseAtomicCasp {
621    pub const fn opcode(&self) -> u32 {
622        self.opcode << 10
623    }
624}
625
626pub type BaseBranchReg = BaseOp;
627pub type BaseBranchRel = BaseOp;
628pub type BaseBranchCmp = BaseOp;
629pub type BaseBranchTst = BaseOp;
630pub type BaseExtract = BaseOp;
631pub type BaseBfc = BaseOp;
632pub type BaseBfi = BaseOp;
633pub type BaseBfx = BaseOp;
634pub type BaseCCmp = BaseOp;
635pub type BaseCInc = BaseOp;
636pub type BaseCSet = BaseOp;
637pub type BaseCSel = BaseOp;
638pub type BaseMovKNZ = BaseOp;
639pub type BaseMull = BaseOp;
640
641#[derive(Debug, Clone, Copy, Default)]
642pub struct FSimdGeneric {
643    scalar_op: u32,
644    scalar_hf: u32,
645    vector_op: u32,
646    vector_hf: u32,
647}
648
649impl FSimdGeneric {
650    pub const fn scalar_op(&self) -> u32 {
651        self.scalar_op << 10
652    }
653
654    pub const fn vector_op(&self) -> u32 {
655        self.vector_op << 10
656    }
657
658    pub const fn scalar_hf(&self) -> u32 {
659        self.scalar_hf
660    }
661
662    pub const fn vector_hf(&self) -> u32 {
663        self.vector_hf
664    }
665}
666
667pub type FSimdVV = FSimdGeneric;
668pub type FSimdVVV = FSimdGeneric;
669pub type FSimdVVVV = FSimdGeneric;
670
671#[derive(Debug, Clone, Copy, Default)]
672pub struct FSimdSV {
673    pub opcode: u32,
674}
675
676#[derive(Debug, Clone, Copy, Default)]
677pub struct FSimdVVVe {
678    scalar_op: u32,
679    scalar_hf: u32,
680    vector_op: u32,
681    element_op: u32,
682}
683
684impl FSimdVVVe {
685    pub const fn scalar_op(&self) -> u32 {
686        self.scalar_op << 10
687    }
688
689    pub const fn scalar_hf(&self) -> u32 {
690        self.scalar_hf
691    }
692
693    pub const fn vector_op(&self) -> u32 {
694        self.vector_op << 10
695    }
696
697    pub const fn vector_hf(&self) -> u32 {
698        HF_C
699    }
700
701    pub const fn element_scalar_op(&self) -> u32 {
702        (self.element_op << 10) | (0x5 << 28)
703    }
704
705    pub const fn element_vector_op(&self) -> u32 {
706        self.element_op << 10
707    }
708}
709
710#[derive(Debug, Clone, Copy, Default)]
711pub struct SimdFcadd {
712    opcode: u32,
713}
714
715impl SimdFcadd {
716    pub const fn opcode(&self) -> u32 {
717        self.opcode << 10
718    }
719}
720
721#[derive(Debug, Clone, Copy, Default)]
722pub struct SimdFcmla {
723    regular_op: u32,
724    element_op: u32,
725}
726
727impl SimdFcmla {
728    pub const fn regular_op(&self) -> u32 {
729        self.regular_op << 10
730    }
731
732    pub const fn element_op(&self) -> u32 {
733        self.element_op << 10
734    }
735}
736
737#[derive(Debug, Clone, Copy, Default)]
738pub struct SimdFccmpFccmpe {
739    opcode: u32,
740}
741
742impl SimdFccmpFccmpe {
743    pub const fn opcode(&self) -> u32 {
744        self.opcode
745    }
746}
747
748#[derive(Debug, Clone, Copy, Default)]
749pub struct SimdFcm {
750    register_op: u32,
751    register_hf: u32,
752    zero_op: u32,
753}
754
755impl SimdFcm {
756    pub const fn has_register_op(&self) -> bool {
757        self.register_op != 0
758    }
759
760    pub const fn has_zero_op(&self) -> bool {
761        self.zero_op != 0
762    }
763
764    pub const fn register_scalar_op(&self) -> u32 {
765        (self.register_op << 10) | (0x5 << 28)
766    }
767
768    pub const fn register_vector_op(&self) -> u32 {
769        self.register_op << 10
770    }
771
772    pub const fn register_scalar_hf(&self) -> u32 {
773        self.register_hf
774    }
775
776    pub const fn register_vector_hf(&self) -> u32 {
777        self.register_hf
778    }
779
780    pub const fn zero_scalar_op(&self) -> u32 {
781        (self.zero_op << 10) | (0x5 << 28)
782    }
783
784    pub const fn zero_vector_op(&self) -> u32 {
785        self.zero_op << 10
786    }
787}
788
789#[derive(Debug, Clone, Copy, Default)]
790pub struct SimdFcmpFcmpe {
791    opcode: u32,
792}
793
794impl SimdFcmpFcmpe {
795    pub const fn opcode(&self) -> u32 {
796        self.opcode
797    }
798}
799
800#[derive(Debug, Clone, Copy, Default)]
801pub struct SimdFcvtLN {
802    opcode: u32,
803    is_cvtxn: u32,
804    has_scalar: u32,
805}
806
807impl SimdFcvtLN {
808    pub const fn scalar_op(&self) -> u32 {
809        (self.opcode << 10) | (0x5 << 28)
810    }
811
812    pub const fn vector_op(&self) -> u32 {
813        self.opcode << 10
814    }
815
816    pub const fn is_cvtxn(&self) -> u32 {
817        self.is_cvtxn
818    }
819
820    pub const fn has_scalar(&self) -> u32 {
821        self.has_scalar
822    }
823}
824
825#[derive(Debug, Clone, Copy, Default)]
826pub struct SimdFcvtSV {
827    vector_int_op: u32,
828    vector_fp_op: u32,
829    general_op: u32,
830    is_float_to_int: u32,
831}
832
833impl SimdFcvtSV {
834    pub const fn scalar_int_op(&self) -> u32 {
835        (self.vector_int_op << 10) | (0x5 << 28)
836    }
837
838    pub const fn vector_int_op(&self) -> u32 {
839        self.vector_int_op << 10
840    }
841
842    pub const fn scalar_fp_op(&self) -> u32 {
843        (self.vector_fp_op << 10) | (0x5 << 28)
844    }
845
846    pub const fn vector_fp_op(&self) -> u32 {
847        self.vector_fp_op << 10
848    }
849
850    pub const fn general_op(&self) -> u32 {
851        self.general_op << 10
852    }
853
854    pub const fn is_float_to_int(&self) -> u32 {
855        self.is_float_to_int
856    }
857
858    pub const fn is_fixed_point(&self) -> bool {
859        self.vector_fp_op != 0
860    }
861}
862
863#[derive(Debug, Clone, Copy, Default)]
864pub struct SimdFmlal {
865    pub vector_op: u32,
866    pub element_op: u32,
867    pub optional_q: u8,
868    pub ta: u8,
869    pub tb: u8,
870    pub t_element: u8,
871}
872
873impl SimdFmlal {
874    pub const fn vector_op(&self) -> u32 {
875        self.vector_op << 10
876    }
877
878    pub const fn element_op(&self) -> u32 {
879        self.element_op << 10
880    }
881
882    pub const fn optional_q(&self) -> u32 {
883        self.optional_q as u32
884    }
885}
886
887#[derive(Debug, Clone, Copy, Default)]
888pub struct FSimdPair {
889    pub scalar_op: u32,
890    pub vector_op: u32,
891}
892
893impl FSimdPair {
894    pub const fn scalar_op(&self) -> u32 {
895        self.scalar_op << 10
896    }
897
898    pub const fn vector_op(&self) -> u32 {
899        self.vector_op << 10
900    }
901}
902
903#[derive(Debug, Clone, Copy, Default)]
904pub struct ISimdVV {
905    opcode: u32,
906    pub vec_op_type: u32,
907}
908
909impl ISimdVV {
910    pub const fn opcode(&self) -> u32 {
911        self.opcode << 10
912    }
913}
914
915#[derive(Debug, Clone, Copy, Default)]
916pub struct ISimdVVx {
917    opcode: u32,
918    pub op0_signature: u32,
919    pub op1_signature: u32,
920}
921
922impl ISimdVVx {
923    pub const fn opcode(&self) -> u32 {
924        self.opcode << 10
925    }
926}
927
928#[derive(Debug, Clone, Copy, Default)]
929pub struct ISimdSV {
930    opcode: u32,
931    pub vec_op_type: u32,
932}
933
934impl ISimdSV {
935    pub const fn opcode(&self) -> u32 {
936        self.opcode << 10
937    }
938}
939
940#[derive(Debug, Clone, Copy, Default)]
941pub struct ISimdVVV {
942    opcode: u32,
943    pub vec_op_type: u32,
944}
945
946impl ISimdVVV {
947    pub const fn opcode(&self) -> u32 {
948        self.opcode << 10
949    }
950}
951
952#[derive(Debug, Clone, Copy, Default)]
953pub struct ISimdVVVx {
954    opcode: u32,
955    pub op0_signature: u32,
956    pub op1_signature: u32,
957    pub op2_signature: u32,
958}
959
960impl ISimdVVVx {
961    pub const fn opcode(&self) -> u32 {
962        self.opcode << 10
963    }
964}
965
966#[derive(Debug, Clone, Copy, Default)]
967pub struct ISimdWWV {
968    opcode: u32,
969    pub vec_op_type: u32,
970}
971
972impl ISimdWWV {
973    pub const fn opcode(&self) -> u32 {
974        self.opcode << 10
975    }
976}
977
978#[derive(Debug, Clone, Copy, Default)]
979pub struct ISimdVVVe {
980    pub regular_op: u32,
981    pub regular_vec_type: u32,
982    pub element_op: u32,
983    pub element_vec_type: u32,
984}
985
986#[derive(Debug, Clone, Copy, Default)]
987pub struct ISimdVVVI {
988    opcode: u32,
989    pub vec_op_type: u32,
990    pub imm_size: u32,
991    pub imm_shift: u32,
992    pub imm64_has_one_bit_less: u32,
993}
994
995impl ISimdVVVI {
996    pub const fn opcode(&self) -> u32 {
997        self.opcode << 10
998    }
999}
1000
1001#[derive(Debug, Clone, Copy, Default)]
1002pub struct ISimdVVVV {
1003    pub opcode: u32,
1004    pub vec_op_type: u32,
1005}
1006
1007#[derive(Debug, Clone, Copy, Default)]
1008pub struct ISimdVVVVx {
1009    pub opcode: u32,
1010    pub op0_signature: u32,
1011    pub op1_signature: u32,
1012    pub op2_signature: u32,
1013    pub op3_signature: u32,
1014}
1015
1016#[derive(Debug, Clone, Copy, Default)]
1017pub struct SimdBicOrr {
1018    pub register_op: u32,
1019    pub immediate_op: u32,
1020}
1021
1022#[derive(Debug, Clone, Copy, Default)]
1023pub struct SimdCmp {
1024    pub register_op: u32,
1025    pub zero_op: u32,
1026    pub vec_op_type: u32,
1027}
1028
1029#[derive(Debug, Clone, Copy, Default)]
1030pub struct SimdDot {
1031    pub vector_op: u32,
1032    pub element_op: u32,
1033    pub ta: u8,
1034    pub tb: u8,
1035    pub t_element: u8,
1036}
1037
1038#[derive(Debug, Clone, Copy, Default)]
1039pub struct SimdMoviMvni {
1040    pub opcode: u32,
1041    pub inverted: u32,
1042}
1043
1044#[derive(Debug, Clone, Copy, Default)]
1045pub struct SimdLdSt {
1046    pub u_offset_op: u32,
1047    pub pre_post_op: u32,
1048    pub register_op: u32,
1049    pub literal_op: u32,
1050    pub u_alt_inst_id: u32,
1051}
1052
1053#[derive(Debug, Clone, Copy, Default)]
1054pub struct SimdLdNStN {
1055    pub single_op: u32,
1056    pub multiple_op: u32,
1057    pub n: u32,
1058    pub replicate: u32,
1059}
1060
1061#[derive(Debug, Clone, Copy, Default)]
1062pub struct SimdLdpStp {
1063    pub offset_op: u32,
1064    pub pre_post_op: u32,
1065}
1066
1067#[derive(Debug, Clone, Copy, Default)]
1068pub struct SimdLdurStur {
1069    pub opcode: u32,
1070}
1071
1072#[derive(Debug, Clone, Copy, Default)]
1073pub struct ISimdPair {
1074    pub opcode2: u32,
1075    pub opcode3: u32,
1076    pub op_type3: u32,
1077}
1078
1079#[derive(Debug, Clone, Copy, Default)]
1080pub struct SimdShift {
1081    pub register_op: u32,
1082    pub immediate_op: u32,
1083    pub inverted_imm: u32,
1084    pub vec_op_type: u32,
1085}
1086
1087#[derive(Debug, Clone, Copy, Default)]
1088pub struct SimdShiftES {
1089    pub opcode: u32,
1090    pub vec_op_type: u32,
1091}
1092
1093#[derive(Debug, Clone, Copy, Default)]
1094pub struct SimdSm3tt {
1095    pub opcode: u32,
1096}
1097
1098#[derive(Debug, Clone, Copy, Default)]
1099pub struct SimdSmovUmov {
1100    pub opcode: u32,
1101    pub vec_op_type: u32,
1102    pub is_signed: u32,
1103}
1104
1105#[derive(Debug, Clone, Copy, Default)]
1106pub struct SimdSxtlUxtl {
1107    pub opcode: u32,
1108    pub vec_op_type: u32,
1109}
1110
1111#[derive(Debug, Clone, Copy, Default)]
1112pub struct SimdTblTbx {
1113    pub opcode: u32,
1114}
1115
1116impl_const_new_zero!(BaseOp { opcode: u32 });
1117impl_const_new_zero!(BaseOpX16 { opcode: u32 });
1118impl_const_new_zero!(BaseOpImm {
1119    opcode: u32,
1120    imm_bits: u16,
1121    imm_offset: u16
1122});
1123impl_const_new_zero!(BaseR {
1124    opcode: u32,
1125    reg_type: u32,
1126    reg_hi_id: u32,
1127    r_shift: u32
1128});
1129impl_const_new_zero!(BaseRR {
1130    opcode: u32,
1131    a_type: u32,
1132    a_hi_id: u32,
1133    a_shift: u32,
1134    b_type: u32,
1135    b_hi_id: u32,
1136    b_shift: u32,
1137    uniform: u32,
1138});
1139impl_const_new_zero!(BaseRRR {
1140    opcode: u32,
1141    a_type: u32,
1142    a_hi_id: u32,
1143    b_type: u32,
1144    b_hi_id: u32,
1145    c_type: u32,
1146    c_hi_id: u32,
1147    uniform: u32,
1148});
1149impl_const_new_zero!(BaseRRRR {
1150    opcode: u32,
1151    a_type: u32,
1152    a_hi_id: u32,
1153    b_type: u32,
1154    b_hi_id: u32,
1155    c_type: u32,
1156    c_hi_id: u32,
1157    d_type: u32,
1158    d_hi_id: u32,
1159    uniform: u32,
1160});
1161impl_const_new_zero!(BaseRRII {
1162    opcode: u32,
1163    a_type: u32,
1164    a_hi_id: u32,
1165    b_type: u32,
1166    b_hi_id: u32,
1167    a_imm_size: u32,
1168    a_imm_discard_lsb: u32,
1169    a_imm_offset: u32,
1170    b_imm_size: u32,
1171    b_imm_discard_lsb: u32,
1172    b_imm_offset: u32,
1173});
1174impl_const_new_zero!(BaseAtDcIcTlbi {
1175    imm_verify_mask: u32,
1176    imm_verify_data: u32,
1177    mandatory_reg: u32,
1178});
1179impl_const_new_zero!(BaseAdcSbc { opcode: u32 });
1180impl_const_new_zero!(BaseMinMax {
1181    register_op: u32,
1182    immediate_op: u32
1183});
1184impl_const_new_zero!(BaseAddSub {
1185    shifted_op: u32,
1186    extended_op: u32,
1187    immediate_op: u32
1188});
1189impl_const_new_zero!(BaseAdr {
1190    opcode: u32,
1191    offset_type: u8
1192});
1193impl_const_new_zero!(BaseBfm { opcode: u32 });
1194impl_const_new_zero!(BaseCmpCmn {
1195    shifted_op: u32,
1196    extended_op: u32,
1197    immediate_op: u32
1198});
1199impl_const_new_zero!(BaseExtend {
1200    opcode: u32,
1201    reg_type: u32,
1202    u: u32
1203});
1204impl_const_new_zero!(BaseLogical {
1205    shifted_op: u32,
1206    immediate_op: u32,
1207    negate_imm: u32
1208});
1209impl_const_new_zero!(BaseMvnNeg { opcode: u32 });
1210impl_const_new_zero!(BaseShift {
1211    register_op: u32,
1212    immediate_op: u32,
1213    ror: u32
1214});
1215impl_const_new_zero!(BaseTst {
1216    shifted_op: u32,
1217    immediate_op: u32
1218});
1219impl_const_new_zero!(BaseRMNoImm {
1220    opcode: u32,
1221    reg_type: u32,
1222    reg_hi_id: u32,
1223    x_offset: u32
1224});
1225impl_const_new_zero!(BaseRMSImm9 {
1226    offset_op: u32,
1227    pre_post_op: u32,
1228    reg_type: u32,
1229    reg_hi_id: u32,
1230    x_offset: u32,
1231    imm_shift: u32,
1232});
1233impl_const_new_zero!(BaseRMSImm10 {
1234    opcode: u32,
1235    reg_type: u32,
1236    reg_hi_id: u32,
1237    x_offset: u32,
1238    imm_shift: u32,
1239});
1240impl_const_new_zero!(BasePrfm {
1241    register_op: u32,
1242    s_offset_op: u32,
1243    u_offset_op: u32,
1244    literal_op: u32
1245});
1246impl_const_new_zero!(BaseLdSt {
1247    u_offset_op: u32,
1248    pre_post_op: u32,
1249    register_op: u32,
1250    literal_op: u32,
1251    reg_type: u32,
1252    x_offset: u32,
1253    u_offset_shift: u32,
1254    u_alt_inst_id: u32,
1255});
1256impl_const_new_zero!(BaseLdpStp {
1257    offset_op: u32,
1258    pre_post_op: u32,
1259    reg_type: u32,
1260    x_offset: u32,
1261    offset_shift: u32,
1262});
1263impl_const_new_zero!(BaseStx {
1264    opcode: u32,
1265    reg_type: u32,
1266    x_offset: u32
1267});
1268impl_const_new_zero!(BaseLdxp {
1269    opcode: u32,
1270    reg_type: u32,
1271    x_offset: u32
1272});
1273impl_const_new_zero!(BaseStxp {
1274    opcode: u32,
1275    reg_type: u32,
1276    x_offset: u32
1277});
1278impl_const_new_zero!(BaseAtomicOp {
1279    opcode: u32,
1280    reg_type: u32,
1281    x_offset: u32,
1282    zr_reg: u32
1283});
1284impl_const_new_zero!(BaseAtomicSt {
1285    opcode: u32,
1286    reg_type: u32,
1287    x_offset: u32
1288});
1289impl_const_new_zero!(BaseAtomicCasp {
1290    opcode: u32,
1291    reg_type: u32,
1292    x_offset: u32
1293});
1294
1295impl_const_new_zero!(FSimdGeneric {
1296    scalar_op: u32,
1297    scalar_hf: u32,
1298    vector_op: u32,
1299    vector_hf: u32
1300});
1301impl_const_new_zero!(FSimdSV { opcode: u32 });
1302impl_const_new_zero!(FSimdVVVe {
1303    scalar_op: u32,
1304    scalar_hf: u32,
1305    vector_op: u32,
1306    element_op: u32
1307});
1308impl_const_new_zero!(SimdFcadd { opcode: u32 });
1309impl_const_new_zero!(SimdFcmla {
1310    regular_op: u32,
1311    element_op: u32
1312});
1313impl_const_new_zero!(SimdFccmpFccmpe { opcode: u32 });
1314impl_const_new_zero!(SimdFcm {
1315    register_op: u32,
1316    register_hf: u32,
1317    zero_op: u32
1318});
1319impl_const_new_zero!(SimdFcmpFcmpe { opcode: u32 });
1320impl_const_new_zero!(SimdFcvtLN {
1321    opcode: u32,
1322    is_cvtxn: u32,
1323    has_scalar: u32
1324});
1325impl_const_new_zero!(SimdFcvtSV {
1326    vector_int_op: u32,
1327    vector_fp_op: u32,
1328    general_op: u32,
1329    is_float_to_int: u32,
1330});
1331impl_const_new_zero!(SimdFmlal {
1332    vector_op: u32,
1333    element_op: u32,
1334    optional_q: u8,
1335    ta: u8,
1336    tb: u8,
1337    t_element: u8,
1338});
1339impl_const_new_zero!(FSimdPair {
1340    scalar_op: u32,
1341    vector_op: u32
1342});
1343
1344impl_const_new_zero!(ISimdVV {
1345    opcode: u32,
1346    vec_op_type: u32
1347});
1348impl_const_new_zero!(ISimdVVx {
1349    opcode: u32,
1350    op0_signature: u32,
1351    op1_signature: u32
1352});
1353impl_const_new_zero!(ISimdSV {
1354    opcode: u32,
1355    vec_op_type: u32
1356});
1357impl_const_new_zero!(ISimdVVV {
1358    opcode: u32,
1359    vec_op_type: u32
1360});
1361impl_const_new_zero!(ISimdVVVx {
1362    opcode: u32,
1363    op0_signature: u32,
1364    op1_signature: u32,
1365    op2_signature: u32,
1366});
1367impl_const_new_zero!(ISimdWWV {
1368    opcode: u32,
1369    vec_op_type: u32
1370});
1371impl_const_new_zero!(ISimdVVVe {
1372    regular_op: u32,
1373    regular_vec_type: u32,
1374    element_op: u32,
1375    element_vec_type: u32,
1376});
1377impl_const_new_zero!(ISimdVVVI {
1378    opcode: u32,
1379    vec_op_type: u32,
1380    imm_size: u32,
1381    imm_shift: u32,
1382    imm64_has_one_bit_less: u32,
1383});
1384impl_const_new_zero!(ISimdVVVV {
1385    opcode: u32,
1386    vec_op_type: u32
1387});
1388impl_const_new_zero!(ISimdVVVVx {
1389    opcode: u32,
1390    op0_signature: u32,
1391    op1_signature: u32,
1392    op2_signature: u32,
1393    op3_signature: u32,
1394});
1395impl_const_new_zero!(SimdBicOrr {
1396    register_op: u32,
1397    immediate_op: u32
1398});
1399impl_const_new_zero!(SimdCmp {
1400    register_op: u32,
1401    zero_op: u32,
1402    vec_op_type: u32
1403});
1404impl_const_new_zero!(SimdDot {
1405    vector_op: u32,
1406    element_op: u32,
1407    ta: u8,
1408    tb: u8,
1409    t_element: u8
1410});
1411impl_const_new_zero!(SimdMoviMvni {
1412    opcode: u32,
1413    inverted: u32
1414});
1415impl_const_new_zero!(SimdLdSt {
1416    u_offset_op: u32,
1417    pre_post_op: u32,
1418    register_op: u32,
1419    literal_op: u32,
1420    u_alt_inst_id: u32,
1421});
1422impl_const_new_zero!(SimdLdNStN {
1423    single_op: u32,
1424    multiple_op: u32,
1425    n: u32,
1426    replicate: u32
1427});
1428impl_const_new_zero!(SimdLdpStp {
1429    offset_op: u32,
1430    pre_post_op: u32
1431});
1432impl_const_new_zero!(SimdLdurStur { opcode: u32 });
1433impl_const_new_zero!(ISimdPair {
1434    opcode2: u32,
1435    opcode3: u32,
1436    op_type3: u32
1437});
1438impl_const_new_zero!(SimdShift {
1439    register_op: u32,
1440    immediate_op: u32,
1441    inverted_imm: u32,
1442    vec_op_type: u32
1443});
1444impl_const_new_zero!(SimdShiftES {
1445    opcode: u32,
1446    vec_op_type: u32
1447});
1448impl_const_new_zero!(SimdSm3tt { opcode: u32 });
1449impl_const_new_zero!(SimdSmovUmov {
1450    opcode: u32,
1451    vec_op_type: u32,
1452    is_signed: u32
1453});
1454impl_const_new_zero!(SimdSxtlUxtl {
1455    opcode: u32,
1456    vec_op_type: u32
1457});
1458impl_const_new_zero!(SimdTblTbx { opcode: u32 });
1459
1460#[derive(Debug, Clone, Copy)]
1461pub struct InstInfo {
1462    pub encoding: u8,
1463    pub encoding_data_index: u8,
1464    pub reserved: u16,
1465    pub rw_info_index: u16,
1466    pub flags: u16,
1467}
1468
1469impl InstInfo {
1470    pub const fn new(
1471        encoding: u8,
1472        encoding_data_index: u8,
1473        reserved: u16,
1474        rw_info_index: u16,
1475        flags: u16,
1476    ) -> Self {
1477        Self {
1478            encoding,
1479            encoding_data_index,
1480            reserved,
1481            rw_info_index,
1482            flags,
1483        }
1484    }
1485}
1486
1487#[derive(Debug, Clone, Copy)]
1488pub enum InstFlag {
1489    Cond = 0x00000001,
1490    Pair = 0x00000002,
1491    Long = 0x00000004,
1492    Narrow = 0x00000008,
1493    VH0_15 = 0x00000010,
1494    Consecutive = 0x00000080,
1495}
1496
1497macro_rules! F {
1498    ($name: ident) => {
1499        InstFlag::$name as u16
1500    };
1501}
1502
1503macro_rules! INST {
1504    ($id: ident, $opcode_encoding: ident, $opcode_data: expr, $rw_info_index: expr, $flags: expr, $opcode_data_index: expr) => {
1505        InstInfo::new(
1506            Encoding::$opcode_encoding as u8,
1507            $opcode_data_index as u8,
1508            0,
1509            $rw_info_index,
1510            $flags,
1511        )
1512    };
1513}
1514
1515macro_rules! TABLE {
1516    ($name: ident = {
1517        $(INST(
1518            $id: ident,
1519            $opcode_encoding: ident,
1520            $opcode_data: expr,
1521            $rw_info_index: expr,
1522            $flags: expr,
1523            $opcode_data_index: expr
1524        ),)*
1525    }) => {
1526        pub static $name: &[InstInfo] = &[
1527            $(
1528                INST!(
1529                    $id,
1530                    $opcode_encoding,
1531                    $opcode_data,
1532                    $rw_info_index,
1533                    $flags,
1534                    $opcode_data_index)
1535            ),*
1536        ];
1537    };
1538}
1539
1540TABLE!(INST_INFO_TABLE
1541
1542  = {
1543// +------------------+---------------------+--------------------------------------------------------------------------------------+-----------+---------------------------+----+
1544// | Instruction Id   | Encoding            | Opcode Data                                                                          | RW Info   | Instruction Flags         |DatX|
1545// +------------------+---------------------+--------------------------------------------------------------------------------------+-----------+---------------------------+----+
1546// ${InstInfo:Begin}
1547INST(None, None, (_), 0, 0, 0), // #0
1548INST(Abs, BaseRR, (0b01011010110000000010000000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 0), // #1
1549INST(Adc, BaseRRR, (0b0001101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 0), // #2
1550INST(Adcs, BaseRRR, (0b0011101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 1), // #3
1551INST(Add, BaseAddSub, (0b0001011000, 0b0001011001, 0b0010001), RWI_W, 0, 0), // #4
1552INST(Addg, BaseRRII, (0b1001000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10), RWI_W, 0, 0), // #5
1553INST(Adds, BaseAddSub, (0b0101011000, 0b0101011001, 0b0110001), RWI_W, 0, 1), // #6
1554INST(Adr, BaseAdr, (0b0001000000000000000000, OffsetType::kAArch64_ADR), RWI_W, 0, 0), // #7
1555INST(Adrp, BaseAdr, (0b1001000000000000000000, OffsetType::kAArch64_ADRP), RWI_W, 0, 1), // #8
1556INST(And, BaseLogical, (0b0001010000, 0b00100100, 0), RWI_W, 0, 0), // #9
1557INST(Ands, BaseLogical, (0b1101010000, 0b11100100, 0), RWI_W, 0, 1), // #10
1558INST(Asr, BaseShift, (0b0001101011000000001010, 0b0001001100000000011111, 0), RWI_W, 0, 0), // #11
1559INST(Asrv, BaseShift, (0b0001101011000000001010, 0b0000000000000000000000, 0), RWI_W, 0, 1), // #12
1560INST(At, BaseAtDcIcTlbi, (0b00011111110000, 0b00001111000000, true), RWI_RX, 0, 0), // #13
1561INST(Autda, BaseRR, (0b11011010110000010001100000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 1), // #14
1562INST(Autdza, BaseR, (0b11011010110000010011101111100000, kX, kZR, 0), RWI_X, 0, 0), // #15
1563INST(Autdb, BaseRR, (0b11011010110000010001110000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 2), // #16
1564INST(Autdzb, BaseR, (0b11011010110000010011111111100000, kX, kZR, 0), RWI_X, 0, 1), // #17
1565INST(Autia, BaseRR, (0b11011010110000010001000000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 3), // #18
1566INST(Autia1716, BaseOp, (0b11010101000000110010000110011111), 0, 0, 0), // #19
1567INST(Autiasp, BaseOp, (0b11010101000000110010001110111111), 0, 0, 1), // #20
1568INST(Autiaz, BaseOp, (0b11010101000000110010001110011111), 0, 0, 2), // #21
1569INST(Autib, BaseRR, (0b11011010110000010001010000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 4), // #22
1570INST(Autib1716, BaseOp, (0b11010101000000110010000111011111), 0, 0, 3), // #23
1571INST(Autibsp, BaseOp, (0b11010101000000110010001111111111), 0, 0, 4), // #24
1572INST(Autibz, BaseOp, (0b11010101000000110010001111011111), 0, 0, 5), // #25
1573INST(Autiza, BaseR, (0b11011010110000010011001111100000, kX, kZR, 0), RWI_X, 0, 2), // #26
1574INST(Autizb, BaseR, (0b11011010110000010011011111100000, kX, kZR, 0), RWI_X, 0, 3), // #27
1575INST(Axflag, BaseOp, (0b11010101000000000100000001011111), 0, 0, 6), // #28
1576INST(B, BaseBranchRel, (0b00010100000000000000000000000000), 0, F!(Cond), 0), // #29
1577INST(Bc, BaseBranchRel, (0b00010100000000000000000000010000), 0, F!(Cond), 1), // #30
1578INST(Bfc, BaseBfc, (0b00110011000000000000001111100000), RWI_X, 0, 0), // #31
1579INST(Bfi, BaseBfi, (0b00110011000000000000000000000000), RWI_X, 0, 0), // #32
1580INST(Bfm, BaseBfm, (0b00110011000000000000000000000000), RWI_X, 0, 0), // #33
1581INST(Bfxil, BaseBfx, (0b00110011000000000000000000000000), RWI_X, 0, 0), // #34
1582INST(Bic, BaseLogical, (0b0001010001, 0b00100100, 1), RWI_W, 0, 2), // #35
1583INST(Bics, BaseLogical, (0b1101010001, 0b11100100, 1), RWI_W, 0, 3), // #36
1584INST(Bl, BaseBranchRel, (0b10010100000000000000000000000000), 0, 0, 2), // #37
1585INST(Blr, BaseBranchReg, (0b11010110001111110000000000000000), RWI_R, 0, 0), // #38
1586INST(Br, BaseBranchReg, (0b11010110000111110000000000000000), RWI_R, 0, 1), // #39
1587INST(Brk, BaseOpImm, (0b11010100001000000000000000000000, 16, 5), 0, 0, 0), // #40
1588INST(Bti, BaseOpImm, (0b11010101000000110010010000011111, 2, 6), 0, 0, 1), // #41
1589INST(Cas, BaseAtomicOp, (0b1000100010100000011111, kWX, 30, 0), RWI_XRX, 0, 0), // #42
1590INST(Casa, BaseAtomicOp, (0b1000100011100000011111, kWX, 30, 1), RWI_XRX, 0, 1), // #43
1591INST(Casab, BaseAtomicOp, (0b0000100011100000011111, kW , 0 , 1), RWI_XRX, 0, 2), // #44
1592INST(Casah, BaseAtomicOp, (0b0100100011100000011111, kW , 0 , 1), RWI_XRX, 0, 3), // #45
1593INST(Casal, BaseAtomicOp, (0b1000100011100000111111, kWX, 30, 1), RWI_XRX, 0, 4), // #46
1594INST(Casalb, BaseAtomicOp, (0b0000100011100000111111, kW , 0 , 1), RWI_XRX, 0, 5), // #47
1595INST(Casalh, BaseAtomicOp, (0b0100100011100000111111, kW , 0 , 1), RWI_XRX, 0, 6), // #48
1596INST(Casb, BaseAtomicOp, (0b0000100010100000011111, kW , 0 , 0), RWI_XRX, 0, 7), // #49
1597INST(Cash, BaseAtomicOp, (0b0100100010100000011111, kW , 0 , 0), RWI_XRX, 0, 8), // #50
1598INST(Casl, BaseAtomicOp, (0b1000100010100000111111, kWX, 30, 0), RWI_XRX, 0, 9), // #51
1599INST(Caslb, BaseAtomicOp, (0b0000100010100000111111, kW , 0 , 0), RWI_XRX, 0, 10), // #52
1600INST(Caslh, BaseAtomicOp, (0b0100100010100000111111, kW , 0 , 0), RWI_XRX, 0, 11), // #53
1601INST(Casp, BaseAtomicCasp, (0b0000100000100000011111, kWX, 30), RWI_XXRRX, F!(Consecutive), 0), // #54
1602INST(Caspa, BaseAtomicCasp, (0b0000100001100000011111, kWX, 30), RWI_XXRRX, F!(Consecutive), 1), // #55
1603INST(Caspal, BaseAtomicCasp, (0b0000100001100000111111, kWX, 30), RWI_XXRRX, F!(Consecutive), 2), // #56
1604INST(Caspl, BaseAtomicCasp, (0b0000100000100000111111, kWX, 30), RWI_XXRRX, F!(Consecutive), 3), // #57
1605INST(Cbnz, BaseBranchCmp, (0b00110101000000000000000000000000), RWI_R, 0, 0), // #58
1606INST(Cbz, BaseBranchCmp, (0b00110100000000000000000000000000), RWI_R, 0, 1), // #59
1607INST(Ccmn, BaseCCmp, (0b00111010010000000000000000000000), RWI_R, 0, 0), // #60
1608INST(Ccmp, BaseCCmp, (0b01111010010000000000000000000000), RWI_R, 0, 1), // #61
1609INST(Cfinv, BaseOp, (0b11010101000000000100000000011111), 0, 0, 7), // #62
1610INST(Chkfeat, BaseOpX16, (0b11010101000000110010010100011111), 0, 0, 0), // #63
1611INST(Cinc, BaseCInc, (0b00011010100000000000010000000000), RWI_W, 0, 0), // #64
1612INST(Cinv, BaseCInc, (0b01011010100000000000000000000000), RWI_W, 0, 1), // #65
1613INST(Clrbhb, BaseOp, (0b11010101000000110010001011011111), 0, 0, 8), // #66
1614INST(Clrex, BaseOpImm, (0b11010101000000110011000001011111, 4, 8), 0, 0, 2), // #67
1615INST(Cls, BaseRR, (0b01011010110000000001010000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 5), // #68
1616INST(Clz, BaseRR, (0b01011010110000000001000000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 6), // #69
1617INST(Cmn, BaseCmpCmn, (0b0101011000, 0b0101011001, 0b0110001), RWI_R, 0, 0), // #70
1618INST(Cmp, BaseCmpCmn, (0b1101011000, 0b1101011001, 0b1110001), RWI_R, 0, 1), // #71
1619INST(Cmpp, BaseRR, (0b10111010110000000000000000011111, kX, kSP, 5, kX, kSP, 16, true), RWI_R, 0, 7), // #72
1620INST(Cneg, BaseCInc, (0b01011010100000000000010000000000), RWI_W, 0, 2), // #73
1621INST(Cnt, BaseRR, (0b01011010110000000001110000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 8), // #74
1622INST(Crc32b, BaseRRR, (0b0001101011000000010000, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 2), // #75
1623INST(Crc32cb, BaseRRR, (0b0001101011000000010100, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 3), // #76
1624INST(Crc32ch, BaseRRR, (0b0001101011000000010101, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 4), // #77
1625INST(Crc32cw, BaseRRR, (0b0001101011000000010110, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 5), // #78
1626INST(Crc32cx, BaseRRR, (0b1001101011000000010111, kW, kZR, kW, kZR, kX, kZR, false), RWI_W, 0, 6), // #79
1627INST(Crc32h, BaseRRR, (0b0001101011000000010001, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 7), // #80
1628INST(Crc32w, BaseRRR, (0b0001101011000000010010, kW, kZR, kW, kZR, kW, kZR, false), RWI_W, 0, 8), // #81
1629INST(Crc32x, BaseRRR, (0b1001101011000000010011, kW, kZR, kW, kZR, kX, kZR, false), RWI_W, 0, 9), // #82
1630INST(Csdb, BaseOp, (0b11010101000000110010001010011111), 0, 0, 9), // #83
1631INST(Csel, BaseCSel, (0b00011010100000000000000000000000), RWI_W, 0, 0), // #84
1632INST(Cset, BaseCSet, (0b00011010100111110000011111100000), RWI_W, 0, 0), // #85
1633INST(Csetm, BaseCSet, (0b01011010100111110000001111100000), RWI_W, 0, 1), // #86
1634INST(Csinc, BaseCSel, (0b00011010100000000000010000000000), RWI_W, 0, 1), // #87
1635INST(Csinv, BaseCSel, (0b01011010100000000000000000000000), RWI_W, 0, 2), // #88
1636INST(Csneg, BaseCSel, (0b01011010100000000000010000000000), RWI_W, 0, 3), // #89
1637INST(Ctz, BaseRR, (0b01011010110000000001100000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 9), // #90
1638INST(Dc, BaseAtDcIcTlbi, (0b00011110000000, 0b00001110000000, true), RWI_RX, 0, 1), // #91
1639INST(Dcps1, BaseOpImm, (0b11010100101000000000000000000001, 16, 5), 0, 0, 3), // #92
1640INST(Dcps2, BaseOpImm, (0b11010100101000000000000000000010, 16, 5), 0, 0, 4), // #93
1641INST(Dcps3, BaseOpImm, (0b11010100101000000000000000000011, 16, 5), 0, 0, 5), // #94
1642INST(Dgh, BaseOp, (0b11010101000000110010000011011111), 0, 0, 10), // #95
1643INST(Dmb, BaseOpImm, (0b11010101000000110011000010111111, 4, 8), 0, 0, 6), // #96
1644INST(Drps, BaseOp, (0b11010110101111110000001111100000), 0, 0, 11), // #97
1645INST(Dsb, BaseOpImm, (0b11010101000000110011000010011111, 4, 8), 0, 0, 7), // #98
1646INST(Eon, BaseLogical, (0b1001010001, 0b10100100, 1), RWI_W, 0, 4), // #99
1647INST(Eor, BaseLogical, (0b1001010000, 0b10100100, 0), RWI_W, 0, 5), // #100
1648INST(Esb, BaseOp, (0b11010101000000110010001000011111), 0, 0, 12), // #101
1649INST(Extr, BaseExtract, (0b00010011100000000000000000000000), RWI_W, 0, 0), // #102
1650INST(Eret, BaseOp, (0b11010110100111110000001111100000), 0, 0, 13), // #103
1651INST(Gmi, BaseRRR, (0b1001101011000000000101, kX , kZR, kX , kSP, kX , kZR, true), RWI_W, 0, 10), // #104
1652INST(Hint, BaseOpImm, (0b11010101000000110010000000011111, 7, 5), 0, 0, 8), // #105
1653INST(Hlt, BaseOpImm, (0b11010100010000000000000000000000, 16, 5), 0, 0, 9), // #106
1654INST(Hvc, BaseOpImm, (0b11010100000000000000000000000010, 16, 5), 0, 0, 10), // #107
1655INST(Ic, BaseAtDcIcTlbi, (0b00011110000000, 0b00001110000000, false), RWI_RX, 0, 2), // #108
1656INST(Isb, BaseOpImm, (0b11010101000000110011000011011111, 4, 8), 0, 0, 11), // #109
1657INST(Ldadd, BaseAtomicOp, (0b1011100000100000000000, kWX, 30, 0), RWI_WRX, 0, 12), // #110
1658INST(Ldadda, BaseAtomicOp, (0b1011100010100000000000, kWX, 30, 1), RWI_WRX, 0, 13), // #111
1659INST(Ldaddab, BaseAtomicOp, (0b0011100010100000000000, kW , 0 , 1), RWI_WRX, 0, 14), // #112
1660INST(Ldaddah, BaseAtomicOp, (0b0111100010100000000000, kW , 0 , 1), RWI_WRX, 0, 15), // #113
1661INST(Ldaddal, BaseAtomicOp, (0b1011100011100000000000, kWX, 30, 1), RWI_WRX, 0, 16), // #114
1662INST(Ldaddalb, BaseAtomicOp, (0b0011100011100000000000, kW , 0 , 1), RWI_WRX, 0, 17), // #115
1663INST(Ldaddalh, BaseAtomicOp, (0b0111100011100000000000, kW , 0 , 1), RWI_WRX, 0, 18), // #116
1664INST(Ldaddb, BaseAtomicOp, (0b0011100000100000000000, kW , 0 , 0), RWI_WRX, 0, 19), // #117
1665INST(Ldaddh, BaseAtomicOp, (0b0111100000100000000000, kW , 0 , 0), RWI_WRX, 0, 20), // #118
1666INST(Ldaddl, BaseAtomicOp, (0b1011100001100000000000, kWX, 30, 0), RWI_WRX, 0, 21), // #119
1667INST(Ldaddlb, BaseAtomicOp, (0b0011100001100000000000, kW , 0 , 0), RWI_WRX, 0, 22), // #120
1668INST(Ldaddlh, BaseAtomicOp, (0b0111100001100000000000, kW , 0 , 0), RWI_WRX, 0, 23), // #121
1669INST(Ldar, BaseRMNoImm, (0b1000100011011111111111, kWX, kZR, 30), RWI_W, 0, 0), // #122
1670INST(Ldarb, BaseRMNoImm, (0b0000100011011111111111, kW , kZR, 0 ), RWI_W, 0, 1), // #123
1671INST(Ldarh, BaseRMNoImm, (0b0100100011011111111111, kW , kZR, 0 ), RWI_W, 0, 2), // #124
1672INST(Ldaxp, BaseLdxp, (0b1000100001111111100000, kWX, 30), RWI_WW, 0, 0), // #125
1673INST(Ldaxr, BaseRMNoImm, (0b1000100001011111111111, kWX, kZR, 30), RWI_W, 0, 3), // #126
1674INST(Ldaxrb, BaseRMNoImm, (0b0000100001011111111111, kW , kZR, 0 ), RWI_W, 0, 4), // #127
1675INST(Ldaxrh, BaseRMNoImm, (0b0100100001011111111111, kW , kZR, 0 ), RWI_W, 0, 5), // #128
1676INST(Ldclr, BaseAtomicOp, (0b1011100000100000000100, kWX, 30, 0), RWI_WRX, 0, 24), // #129
1677INST(Ldclra, BaseAtomicOp, (0b1011100010100000000100, kWX, 30, 1), RWI_WRX, 0, 25), // #130
1678INST(Ldclrab, BaseAtomicOp, (0b0011100010100000000100, kW , 0 , 1), RWI_WRX, 0, 26), // #131
1679INST(Ldclrah, BaseAtomicOp, (0b0111100010100000000100, kW , 0 , 1), RWI_WRX, 0, 27), // #132
1680INST(Ldclral, BaseAtomicOp, (0b1011100011100000000100, kWX, 30, 1), RWI_WRX, 0, 28), // #133
1681INST(Ldclralb, BaseAtomicOp, (0b0011100011100000000100, kW , 0 , 1), RWI_WRX, 0, 29), // #134
1682INST(Ldclralh, BaseAtomicOp, (0b0111100011100000000100, kW , 0 , 1), RWI_WRX, 0, 30), // #135
1683INST(Ldclrb, BaseAtomicOp, (0b0011100000100000000100, kW , 0 , 0), RWI_WRX, 0, 31), // #136
1684INST(Ldclrh, BaseAtomicOp, (0b0111100000100000000100, kW , 0 , 0), RWI_WRX, 0, 32), // #137
1685INST(Ldclrl, BaseAtomicOp, (0b1011100001100000000100, kWX, 30, 0), RWI_WRX, 0, 33), // #138
1686INST(Ldclrlb, BaseAtomicOp, (0b0011100001100000000100, kW , 0 , 0), RWI_WRX, 0, 34), // #139
1687INST(Ldclrlh, BaseAtomicOp, (0b0111100001100000000100, kW , 0 , 0), RWI_WRX, 0, 35), // #140
1688INST(Ldeor, BaseAtomicOp, (0b1011100000100000001000, kWX, 30, 0), RWI_WRX, 0, 36), // #141
1689INST(Ldeora, BaseAtomicOp, (0b1011100010100000001000, kWX, 30, 1), RWI_WRX, 0, 37), // #142
1690INST(Ldeorab, BaseAtomicOp, (0b0011100010100000001000, kW , 0 , 1), RWI_WRX, 0, 38), // #143
1691INST(Ldeorah, BaseAtomicOp, (0b0111100010100000001000, kW , 0 , 1), RWI_WRX, 0, 39), // #144
1692INST(Ldeoral, BaseAtomicOp, (0b1011100011100000001000, kWX, 30, 1), RWI_WRX, 0, 40), // #145
1693INST(Ldeoralb, BaseAtomicOp, (0b0011100011100000001000, kW , 0 , 1), RWI_WRX, 0, 41), // #146
1694INST(Ldeoralh, BaseAtomicOp, (0b0111100011100000001000, kW , 0 , 1), RWI_WRX, 0, 42), // #147
1695INST(Ldeorb, BaseAtomicOp, (0b0011100000100000001000, kW , 0 , 0), RWI_WRX, 0, 43), // #148
1696INST(Ldeorh, BaseAtomicOp, (0b0111100000100000001000, kW , 0 , 0), RWI_WRX, 0, 44), // #149
1697INST(Ldeorl, BaseAtomicOp, (0b1011100001100000001000, kWX, 30, 0), RWI_WRX, 0, 45), // #150
1698INST(Ldeorlb, BaseAtomicOp, (0b0011100001100000001000, kW , 0 , 0), RWI_WRX, 0, 46), // #151
1699INST(Ldeorlh, BaseAtomicOp, (0b0111100001100000001000, kW , 0 , 0), RWI_WRX, 0, 47), // #152
1700INST(Ldg, BaseRMSImm9, (0b1101100101100000000000, 0b0000000000000000000000, kX , kZR, 0, 4), RWI_W, 0, 0), // #153
1701INST(Ldgm, BaseRMNoImm, (0b1101100111100000000000, kX , kZR, 0 ), RWI_W, 0, 6), // #154
1702INST(Ldlar, BaseRMNoImm, (0b1000100011011111011111, kWX, kZR, 30), RWI_W, 0, 7), // #155
1703INST(Ldlarb, BaseRMNoImm, (0b0000100011011111011111, kW , kZR, 0 ), RWI_W, 0, 8), // #156
1704INST(Ldlarh, BaseRMNoImm, (0b0100100011011111011111, kW , kZR, 0 ), RWI_W, 0, 9), // #157
1705INST(Ldnp, BaseLdpStp, (0b0010100001, 0           , kWX, 31, 2), RWI_WW, 0, 0), // #158
1706INST(Ldp, BaseLdpStp, (0b0010100101, 0b0010100011, kWX, 31, 2), RWI_WW, 0, 1), // #159
1707INST(Ldpsw, BaseLdpStp, (0b0110100101, 0b0110100011, kX , 0 , 2), RWI_WW, 0, 2), // #160
1708INST(Ldr, BaseLdSt, (0b1011100101, 0b10111000010, 0b10111000011, 0b00011000, kWX, 30, 2, InstId::Ldur), RWI_W, 0, 0), // #161
1709INST(Ldraa, BaseRMSImm10, (0b1111100000100000000001, kX , kZR, 0, 3), RWI_W, 0, 0), // #162
1710INST(Ldrab, BaseRMSImm10, (0b1111100010100000000001, kX , kZR, 0, 3), RWI_W, 0, 1), // #163
1711INST(Ldrb, BaseLdSt, (0b0011100101, 0b00111000010, 0b00111000011, 0         , kW , 0 , 0, InstId::Ldurb), RWI_W, 0, 1), // #164
1712INST(Ldrh, BaseLdSt, (0b0111100101, 0b01111000010, 0b01111000011, 0         , kW , 0 , 1, InstId::Ldurh), RWI_W, 0, 2), // #165
1713INST(Ldrsb, BaseLdSt, (0b0011100111, 0b00111000100, 0b00111000111, 0         , kWX, 22, 0, InstId::Ldursb), RWI_W, 0, 3), // #166
1714INST(Ldrsh, BaseLdSt, (0b0111100111, 0b01111000100, 0b01111000111, 0         , kWX, 22, 1, InstId::Ldursh), RWI_W, 0, 4), // #167
1715INST(Ldrsw, BaseLdSt, (0b1011100110, 0b10111000100, 0b10111000101, 0b10011000, kX , 0 , 2, InstId::Ldursw), RWI_W, 0, 5), // #168
1716INST(Ldset, BaseAtomicOp, (0b1011100000100000001100, kWX, 30, 0), RWI_WRX, 0, 48), // #169
1717INST(Ldseta, BaseAtomicOp, (0b1011100010100000001100, kWX, 30, 1), RWI_WRX, 0, 49), // #170
1718INST(Ldsetab, BaseAtomicOp, (0b0011100010100000001100, kW , 0 , 1), RWI_WRX, 0, 50), // #171
1719INST(Ldsetah, BaseAtomicOp, (0b0111100010100000001100, kW , 0 , 1), RWI_WRX, 0, 51), // #172
1720INST(Ldsetal, BaseAtomicOp, (0b1011100011100000001100, kWX, 30, 1), RWI_WRX, 0, 52), // #173
1721INST(Ldsetalb, BaseAtomicOp, (0b0011100011100000001100, kW , 0 , 1), RWI_WRX, 0, 53), // #174
1722INST(Ldsetalh, BaseAtomicOp, (0b0111100011100000001100, kW , 0 , 1), RWI_WRX, 0, 54), // #175
1723INST(Ldsetb, BaseAtomicOp, (0b0011100000100000001100, kW , 0 , 0), RWI_WRX, 0, 55), // #176
1724INST(Ldseth, BaseAtomicOp, (0b0111100000100000001100, kW , 0 , 0), RWI_WRX, 0, 56), // #177
1725INST(Ldsetl, BaseAtomicOp, (0b1011100001100000001100, kWX, 30, 0), RWI_WRX, 0, 57), // #178
1726INST(Ldsetlb, BaseAtomicOp, (0b0011100001100000001100, kW , 0 , 0), RWI_WRX, 0, 58), // #179
1727INST(Ldsetlh, BaseAtomicOp, (0b0111100001100000001100, kW , 0 , 0), RWI_WRX, 0, 59), // #180
1728INST(Ldsmax, BaseAtomicOp, (0b1011100000100000010000, kWX, 30, 0), RWI_WRX, 0, 60), // #181
1729INST(Ldsmaxa, BaseAtomicOp, (0b1011100010100000010000, kWX, 30, 1), RWI_WRX, 0, 61), // #182
1730INST(Ldsmaxab, BaseAtomicOp, (0b0011100010100000010000, kW , 0 , 1), RWI_WRX, 0, 62), // #183
1731INST(Ldsmaxah, BaseAtomicOp, (0b0111100010100000010000, kW , 0 , 1), RWI_WRX, 0, 63), // #184
1732INST(Ldsmaxal, BaseAtomicOp, (0b1011100011100000010000, kWX, 30, 1), RWI_WRX, 0, 64), // #185
1733INST(Ldsmaxalb, BaseAtomicOp, (0b0011100011100000010000, kW , 0 , 1), RWI_WRX, 0, 65), // #186
1734INST(Ldsmaxalh, BaseAtomicOp, (0b0111100011100000010000, kW , 0 , 1), RWI_WRX, 0, 66), // #187
1735INST(Ldsmaxb, BaseAtomicOp, (0b0011100000100000010000, kW , 0 , 0), RWI_WRX, 0, 67), // #188
1736INST(Ldsmaxh, BaseAtomicOp, (0b0111100000100000010000, kW , 0 , 0), RWI_WRX, 0, 68), // #189
1737INST(Ldsmaxl, BaseAtomicOp, (0b1011100001100000010000, kWX, 30, 0), RWI_WRX, 0, 69), // #190
1738INST(Ldsmaxlb, BaseAtomicOp, (0b0011100001100000010000, kW , 0 , 0), RWI_WRX, 0, 70), // #191
1739INST(Ldsmaxlh, BaseAtomicOp, (0b0111100001100000010000, kW , 0 , 0), RWI_WRX, 0, 71), // #192
1740INST(Ldsmin, BaseAtomicOp, (0b1011100000100000010100, kWX, 30, 0), RWI_WRX, 0, 72), // #193
1741INST(Ldsmina, BaseAtomicOp, (0b1011100010100000010100, kWX, 30, 1), RWI_WRX, 0, 73), // #194
1742INST(Ldsminab, BaseAtomicOp, (0b0011100010100000010100, kW , 0 , 1), RWI_WRX, 0, 74), // #195
1743INST(Ldsminah, BaseAtomicOp, (0b0111100010100000010100, kW , 0 , 1), RWI_WRX, 0, 75), // #196
1744INST(Ldsminal, BaseAtomicOp, (0b1011100011100000010100, kWX, 30, 1), RWI_WRX, 0, 76), // #197
1745INST(Ldsminalb, BaseAtomicOp, (0b0011100011100000010100, kW , 0 , 1), RWI_WRX, 0, 77), // #198
1746INST(Ldsminalh, BaseAtomicOp, (0b0111100011100000010100, kW , 0 , 1), RWI_WRX, 0, 78), // #199
1747INST(Ldsminb, BaseAtomicOp, (0b0011100000100000010100, kW , 0 , 0), RWI_WRX, 0, 79), // #200
1748INST(Ldsminh, BaseAtomicOp, (0b0111100000100000010100, kW , 0 , 0), RWI_WRX, 0, 80), // #201
1749INST(Ldsminl, BaseAtomicOp, (0b1011100001100000010100, kWX, 30, 0), RWI_WRX, 0, 81), // #202
1750INST(Ldsminlb, BaseAtomicOp, (0b0011100001100000010100, kW , 0 , 0), RWI_WRX, 0, 82), // #203
1751INST(Ldsminlh, BaseAtomicOp, (0b0111100001100000010100, kW , 0 , 0), RWI_WRX, 0, 83), // #204
1752INST(Ldtr, BaseRMSImm9, (0b1011100001000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0), RWI_W, 0, 1), // #205
1753INST(Ldtrb, BaseRMSImm9, (0b0011100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_W, 0, 2), // #206
1754INST(Ldtrh, BaseRMSImm9, (0b0111100001000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_W, 0, 3), // #207
1755INST(Ldtrsb, BaseRMSImm9, (0b0011100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0), RWI_W, 0, 4), // #208
1756INST(Ldtrsh, BaseRMSImm9, (0b0111100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0), RWI_W, 0, 5), // #209
1757INST(Ldtrsw, BaseRMSImm9, (0b1011100010000000000010, 0b0000000000000000000000, kX , kZR, 0 , 0), RWI_W, 0, 6), // #210
1758INST(Ldumax, BaseAtomicOp, (0b1011100000100000011000, kWX, 30, 0), RWI_WRX, 0, 84), // #211
1759INST(Ldumaxa, BaseAtomicOp, (0b1011100010100000011000, kWX, 30, 1), RWI_WRX, 0, 85), // #212
1760INST(Ldumaxab, BaseAtomicOp, (0b0011100010100000011000, kW , 0 , 1), RWI_WRX, 0, 86), // #213
1761INST(Ldumaxah, BaseAtomicOp, (0b0111100010100000011000, kW , 0 , 1), RWI_WRX, 0, 87), // #214
1762INST(Ldumaxal, BaseAtomicOp, (0b1011100011100000011000, kWX, 30, 1), RWI_WRX, 0, 88), // #215
1763INST(Ldumaxalb, BaseAtomicOp, (0b0011100011100000011000, kW , 0 , 1), RWI_WRX, 0, 89), // #216
1764INST(Ldumaxalh, BaseAtomicOp, (0b0111100011100000011000, kW , 0 , 1), RWI_WRX, 0, 90), // #217
1765INST(Ldumaxb, BaseAtomicOp, (0b0011100000100000011000, kW , 0 , 0), RWI_WRX, 0, 91), // #218
1766INST(Ldumaxh, BaseAtomicOp, (0b0111100000100000011000, kW , 0 , 0), RWI_WRX, 0, 92), // #219
1767INST(Ldumaxl, BaseAtomicOp, (0b1011100001100000011000, kWX, 30, 0), RWI_WRX, 0, 93), // #220
1768INST(Ldumaxlb, BaseAtomicOp, (0b0011100001100000011000, kW , 0 , 0), RWI_WRX, 0, 94), // #221
1769INST(Ldumaxlh, BaseAtomicOp, (0b0111100001100000011000, kW , 0 , 0), RWI_WRX, 0, 95), // #222
1770INST(Ldumin, BaseAtomicOp, (0b1011100000100000011100, kWX, 30, 0), RWI_WRX, 0, 96), // #223
1771INST(Ldumina, BaseAtomicOp, (0b1011100010100000011100, kWX, 30, 1), RWI_WRX, 0, 97), // #224
1772INST(Lduminab, BaseAtomicOp, (0b0011100010100000011100, kW , 0 , 1), RWI_WRX, 0, 98), // #225
1773INST(Lduminah, BaseAtomicOp, (0b0111100010100000011100, kW , 0 , 1), RWI_WRX, 0, 99), // #226
1774INST(Lduminal, BaseAtomicOp, (0b1011100011100000011100, kWX, 30, 1), RWI_WRX, 0, 100), // #227
1775INST(Lduminalb, BaseAtomicOp, (0b0011100011100000011100, kW , 0 , 1), RWI_WRX, 0, 101), // #228
1776INST(Lduminalh, BaseAtomicOp, (0b0111100011100000011100, kW , 0 , 1), RWI_WRX, 0, 102), // #229
1777INST(Lduminb, BaseAtomicOp, (0b0011100000100000011100, kW , 0 , 0), RWI_WRX, 0, 103), // #230
1778INST(Lduminh, BaseAtomicOp, (0b0111100000100000011100, kW , 0 , 0), RWI_WRX, 0, 104), // #231
1779INST(Lduminl, BaseAtomicOp, (0b1011100001100000011100, kWX, 30, 0), RWI_WRX, 0, 105), // #232
1780INST(Lduminlb, BaseAtomicOp, (0b0011100001100000011100, kW , 0 , 0), RWI_WRX, 0, 106), // #233
1781INST(Lduminlh, BaseAtomicOp, (0b0111100001100000011100, kW , 0 , 0), RWI_WRX, 0, 107), // #234
1782INST(Ldur, BaseRMSImm9, (0b1011100001000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0), RWI_W, 0, 7), // #235
1783INST(Ldurb, BaseRMSImm9, (0b0011100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_W, 0, 8), // #236
1784INST(Ldurh, BaseRMSImm9, (0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_W, 0, 9), // #237
1785INST(Ldursb, BaseRMSImm9, (0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0), RWI_W, 0, 10), // #238
1786INST(Ldursh, BaseRMSImm9, (0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0), RWI_W, 0, 11), // #239
1787INST(Ldursw, BaseRMSImm9, (0b1011100010000000000000, 0b0000000000000000000000, kX , kZR, 0 , 0), RWI_W, 0, 12), // #240
1788INST(Ldxp, BaseLdxp, (0b1000100001111111000000, kWX, 30), RWI_WW, 0, 1), // #241
1789INST(Ldxr, BaseRMNoImm, (0b1000100001011111011111, kWX, kZR, 30), RWI_W, 0, 10), // #242
1790INST(Ldxrb, BaseRMNoImm, (0b0000100001011111011111, kW , kZR, 0 ), RWI_W, 0, 11), // #243
1791INST(Ldxrh, BaseRMNoImm, (0b0100100001011111011111, kW , kZR, 0 ), RWI_W, 0, 12), // #244
1792INST(Lsl, BaseShift, (0b0001101011000000001000, 0b0101001100000000000000, 0), RWI_W, 0, 2), // #245
1793INST(Lslv, BaseShift, (0b0001101011000000001000, 0b0000000000000000000000, 0), RWI_W, 0, 3), // #246
1794INST(Lsr, BaseShift, (0b0001101011000000001001, 0b0101001100000000011111, 0), RWI_W, 0, 4), // #247
1795INST(Lsrv, BaseShift, (0b0001101011000000001001, 0b0000000000000000000000, 0), RWI_W, 0, 5), // #248
1796INST(Madd, BaseRRRR, (0b0001101100000000000000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 0), // #249
1797INST(Mneg, BaseRRR, (0b0001101100000000111111, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 11), // #250
1798INST(Mov, BaseMov, (_), RWI_W, 0, 0), // #251
1799INST(Movk, BaseMovKNZ, (0b01110010100000000000000000000000), RWI_X, 0, 0), // #252
1800INST(Movn, BaseMovKNZ, (0b00010010100000000000000000000000), RWI_W, 0, 1), // #253
1801INST(Movz, BaseMovKNZ, (0b01010010100000000000000000000000), RWI_W, 0, 2), // #254
1802INST(Mrs, BaseMrs, (_), RWI_W, 0, 0), // #255
1803INST(Msr, BaseMsr, (_), RWI_W, 0, 0), // #256
1804INST(Msub, BaseRRRR, (0b0001101100000000100000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 1), // #257
1805INST(Mul, BaseRRR, (0b0001101100000000011111, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 12), // #258
1806INST(Mvn, BaseMvnNeg, (0b00101010001000000000001111100000), RWI_W, 0, 0), // #259
1807INST(Neg, BaseMvnNeg, (0b01001011000000000000001111100000), RWI_W, 0, 1), // #260
1808INST(Negs, BaseMvnNeg, (0b01101011000000000000001111100000), RWI_W, 0, 2), // #261
1809INST(Ngc, BaseRR, (0b01011010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true), RWI_W, 0, 10), // #262
1810INST(Ngcs, BaseRR, (0b01111010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true), RWI_W, 0, 11), // #263
1811INST(Nop, BaseOp, (0b11010101000000110010000000011111), 0, 0, 14), // #264
1812INST(Orn, BaseLogical, (0b0101010001, 0b01100100, 1), RWI_W, 0, 6), // #265
1813INST(Orr, BaseLogical, (0b0101010000, 0b01100100, 0), RWI_W, 0, 7), // #266
1814INST(Pacda, BaseRR, (0b11011010110000010000100000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 12), // #267
1815INST(Pacdb, BaseRR, (0b11011010110000010000110000000000, kX, kZR, 0, kX, kSP, 5, true), RWI_X, 0, 13), // #268
1816INST(Pacdza, BaseR, (0b11011010110000010010101111100000, kX, kZR, 0), RWI_X, 0, 4), // #269
1817INST(Pacdzb, BaseR, (0b11011010110000010010111111100000, kX, kZR, 0), RWI_X, 0, 5), // #270
1818INST(Pacga, BaseRRR, (0b1001101011000000001100, kX, kZR, kX, kZR, kX, kSP, false), RWI_W, 0, 13), // #271
1819INST(Prfm, BasePrfm, (0b11111000101, 0b1111100110, 0b11111000100, 0b11011000), RWI_R, 0, 0), // #272
1820INST(Pssbb, BaseOp, (0b11010101000000110011010010011111), 0, 0, 15), // #273
1821INST(Rbit, BaseRR, (0b01011010110000000000000000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 14), // #274
1822INST(Ret, BaseBranchReg, (0b11010110010111110000000000000000), RWI_R, 0, 2), // #275
1823INST(Rev, BaseRev, (_), RWI_W, 0, 0), // #276
1824INST(Rev16, BaseRR, (0b01011010110000000000010000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 15), // #277
1825INST(Rev32, BaseRR, (0b11011010110000000000100000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 16), // #278
1826INST(Rev64, BaseRR, (0b11011010110000000000110000000000, kWX, kZR, 0, kWX, kZR, 5, true), RWI_W, 0, 17), // #279
1827INST(Ror, BaseShift, (0b0001101011000000001011, 0b0001001110000000000000, 1), RWI_W, 0, 6), // #280
1828INST(Rorv, BaseShift, (0b0001101011000000001011, 0b0000000000000000000000, 1), RWI_W, 0, 7), // #281
1829INST(Sbc, BaseRRR, (0b0101101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 14), // #282
1830INST(Sbcs, BaseRRR, (0b0111101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 15), // #283
1831INST(Sbfiz, BaseBfi, (0b00010011000000000000000000000000), RWI_W, 0, 1), // #284
1832INST(Sbfm, BaseBfm, (0b00010011000000000000000000000000), RWI_W, 0, 1), // #285
1833INST(Sbfx, BaseBfx, (0b00010011000000000000000000000000), RWI_W, 0, 1), // #286
1834INST(Sdiv, BaseRRR, (0b0001101011000000000011, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 16), // #287
1835INST(Setf8, BaseR, (0b00111010000000000000100000001101, kW, kZR, 5), 0, 0, 6), // #288
1836INST(Setf16, BaseR, (0b00111010000000000100100000001101, kW, kZR, 5), 0, 0, 7), // #289
1837INST(Sev, BaseOp, (0b11010101000000110010000010011111), 0, 0, 16), // #290
1838INST(Sevl, BaseOp, (0b11010101000000110010000010111111), 0, 0, 17), // #291
1839INST(Smaddl, BaseRRRR, (0b1001101100100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false), RWI_W, 0, 2), // #292
1840INST(Smax, BaseMinMax, (0b00011010110000000110000000000000, 0b00010001110000000000000000000000), RWI_W, 0, 0), // #293
1841INST(Smc, BaseOpImm, (0b11010100000000000000000000000011, 16, 5), 0, 0, 12), // #294
1842INST(Smin, BaseMinMax, (0b00011010110000000110100000000000, 0b00010001110010000000000000000000), RWI_W, 0, 1), // #295
1843INST(Smnegl, BaseRRR, (0b1001101100100000111111, kX , kZR, kW , kZR, kW , kZR, false), RWI_W, 0, 17), // #296
1844INST(Smsubl, BaseRRRR, (0b1001101100100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false), RWI_W, 0, 3), // #297
1845INST(Smulh, BaseRRR, (0b1001101101000000011111, kX , kZR, kX , kZR, kX , kZR, true), RWI_W, 0, 18), // #298
1846INST(Smull, BaseRRR, (0b1001101100100000011111, kX , kZR, kW , kZR, kW , kZR, false), RWI_W, 0, 19), // #299
1847INST(Ssbb, BaseOp, (0b11010101000000110011000010011111), 0, 0, 18), // #300
1848INST(St2g, BaseRMSImm9, (0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4), RWI_RW, 0, 13), // #301
1849INST(Stadd, BaseAtomicSt, (0b1011100000100000000000, kWX, 30), RWI_RX, 0, 0), // #302
1850INST(Staddl, BaseAtomicSt, (0b1011100001100000000000, kWX, 30), RWI_RX, 0, 1), // #303
1851INST(Staddb, BaseAtomicSt, (0b0011100000100000000000, kW , 0 ), RWI_RX, 0, 2), // #304
1852INST(Staddlb, BaseAtomicSt, (0b0011100001100000000000, kW , 0 ), RWI_RX, 0, 3), // #305
1853INST(Staddh, BaseAtomicSt, (0b0111100000100000000000, kW , 0 ), RWI_RX, 0, 4), // #306
1854INST(Staddlh, BaseAtomicSt, (0b0111100001100000000000, kW , 0 ), RWI_RX, 0, 5), // #307
1855INST(Stclr, BaseAtomicSt, (0b1011100000100000000100, kWX, 30), RWI_RX, 0, 6), // #308
1856INST(Stclrl, BaseAtomicSt, (0b1011100001100000000100, kWX, 30), RWI_RX, 0, 7), // #309
1857INST(Stclrb, BaseAtomicSt, (0b0011100000100000000100, kW , 0 ), RWI_RX, 0, 8), // #310
1858INST(Stclrlb, BaseAtomicSt, (0b0011100001100000000100, kW , 0 ), RWI_RX, 0, 9), // #311
1859INST(Stclrh, BaseAtomicSt, (0b0111100000100000000100, kW , 0 ), RWI_RX, 0, 10), // #312
1860INST(Stclrlh, BaseAtomicSt, (0b0111100001100000000100, kW , 0 ), RWI_RX, 0, 11), // #313
1861INST(Steor, BaseAtomicSt, (0b1011100000100000001000, kWX, 30), RWI_RX, 0, 12), // #314
1862INST(Steorl, BaseAtomicSt, (0b1011100001100000001000, kWX, 30), RWI_RX, 0, 13), // #315
1863INST(Steorb, BaseAtomicSt, (0b0011100000100000001000, kW , 0 ), RWI_RX, 0, 14), // #316
1864INST(Steorlb, BaseAtomicSt, (0b0011100001100000001000, kW , 0 ), RWI_RX, 0, 15), // #317
1865INST(Steorh, BaseAtomicSt, (0b0111100000100000001000, kW , 0 ), RWI_RX, 0, 16), // #318
1866INST(Steorlh, BaseAtomicSt, (0b0111100001100000001000, kW , 0 ), RWI_RX, 0, 17), // #319
1867INST(Stg, BaseRMSImm9, (0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4), RWI_RW, 0, 14), // #320
1868INST(Stgm, BaseRMNoImm, (0b1101100110100000000000, kX , kZR, 0 ), RWI_RW, 0, 13), // #321
1869INST(Stgp, BaseLdpStp, (0b0110100100, 0b0110100010, kX, 0, 4), RWI_RRW, 0, 3), // #322
1870INST(Stllr, BaseRMNoImm, (0b1000100010011111011111, kWX, kZR, 30), RWI_RW, 0, 14), // #323
1871INST(Stllrb, BaseRMNoImm, (0b0000100010011111011111, kW , kZR, 0 ), RWI_RW, 0, 15), // #324
1872INST(Stllrh, BaseRMNoImm, (0b0100100010011111011111, kW , kZR, 0 ), RWI_RW, 0, 16), // #325
1873INST(Stlr, BaseRMNoImm, (0b1000100010011111111111, kWX, kZR, 30), RWI_RW, 0, 17), // #326
1874INST(Stlrb, BaseRMNoImm, (0b0000100010011111111111, kW , kZR, 0 ), RWI_RW, 0, 18), // #327
1875INST(Stlrh, BaseRMNoImm, (0b0100100010011111111111, kW , kZR, 0 ), RWI_RW, 0, 19), // #328
1876INST(Stlxp, BaseStxp, (0b1000100000100000100000, kWX, 30), RWI_WRRX, 0, 0), // #329
1877INST(Stlxr, BaseAtomicOp, (0b1000100000000000111111, kWX, 30, 1), RWI_WRX, 0, 108), // #330
1878INST(Stlxrb, BaseAtomicOp, (0b0000100000000000111111, kW , 0 , 1), RWI_WRX, 0, 109), // #331
1879INST(Stlxrh, BaseAtomicOp, (0b0100100000000000111111, kW , 0 , 1), RWI_WRX, 0, 110), // #332
1880INST(Stnp, BaseLdpStp, (0b0010100000, 0           , kWX, 31, 2), RWI_RRW, 0, 4), // #333
1881INST(Stp, BaseLdpStp, (0b0010100100, 0b0010100010, kWX, 31, 2), RWI_RRW, 0, 5), // #334
1882INST(Str, BaseLdSt, (0b1011100100, 0b10111000000, 0b10111000001, 0         , kWX, 30, 2, InstId::Stur), RWI_RW, 0, 6), // #335
1883INST(Strb, BaseLdSt, (0b0011100100, 0b00111000000, 0b00111000001, 0         , kW , 30, 0, InstId::Sturb), RWI_RW, 0, 7), // #336
1884INST(Strh, BaseLdSt, (0b0111100100, 0b01111000000, 0b01111000001, 0         , kWX, 30, 1, InstId::Sturh), RWI_RW, 0, 8), // #337
1885INST(Stset, BaseAtomicSt, (0b1011100000100000001100, kWX, 30), RWI_RX, 0, 18), // #338
1886INST(Stsetl, BaseAtomicSt, (0b1011100001100000001100, kWX, 30), RWI_RX, 0, 19), // #339
1887INST(Stsetb, BaseAtomicSt, (0b0011100000100000001100, kW , 0 ), RWI_RX, 0, 20), // #340
1888INST(Stsetlb, BaseAtomicSt, (0b0011100001100000001100, kW , 0 ), RWI_RX, 0, 21), // #341
1889INST(Stseth, BaseAtomicSt, (0b0111100000100000001100, kW , 0 ), RWI_RX, 0, 22), // #342
1890INST(Stsetlh, BaseAtomicSt, (0b0111100001100000001100, kW , 0 ), RWI_RX, 0, 23), // #343
1891INST(Stsmax, BaseAtomicSt, (0b1011100000100000010000, kWX, 30), RWI_RX, 0, 24), // #344
1892INST(Stsmaxl, BaseAtomicSt, (0b1011100001100000010000, kWX, 30), RWI_RX, 0, 25), // #345
1893INST(Stsmaxb, BaseAtomicSt, (0b0011100000100000010000, kW , 0 ), RWI_RX, 0, 26), // #346
1894INST(Stsmaxlb, BaseAtomicSt, (0b0011100001100000010000, kW , 0 ), RWI_RX, 0, 27), // #347
1895INST(Stsmaxh, BaseAtomicSt, (0b0111100000100000010000, kW , 0 ), RWI_RX, 0, 28), // #348
1896INST(Stsmaxlh, BaseAtomicSt, (0b0111100001100000010000, kW , 0 ), RWI_RX, 0, 29), // #349
1897INST(Stsmin, BaseAtomicSt, (0b1011100000100000010100, kWX, 30), RWI_RX, 0, 30), // #350
1898INST(Stsminl, BaseAtomicSt, (0b1011100001100000010100, kWX, 30), RWI_RX, 0, 31), // #351
1899INST(Stsminb, BaseAtomicSt, (0b0011100000100000010100, kW , 0 ), RWI_RX, 0, 32), // #352
1900INST(Stsminlb, BaseAtomicSt, (0b0011100001100000010100, kW , 0 ), RWI_RX, 0, 33), // #353
1901INST(Stsminh, BaseAtomicSt, (0b0111100000100000010100, kW , 0 ), RWI_RX, 0, 34), // #354
1902INST(Stsminlh, BaseAtomicSt, (0b0111100001100000010100, kW , 0 ), RWI_RX, 0, 35), // #355
1903INST(Sttr, BaseRMSImm9, (0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0), RWI_RW, 0, 15), // #356
1904INST(Sttrb, BaseRMSImm9, (0b0011100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_RW, 0, 16), // #357
1905INST(Sttrh, BaseRMSImm9, (0b0111100000000000000010, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_RW, 0, 17), // #358
1906INST(Stumax, BaseAtomicSt, (0b1011100000100000011000, kWX, 30), RWI_RX, 0, 36), // #359
1907INST(Stumaxl, BaseAtomicSt, (0b1011100001100000011000, kWX, 30), RWI_RX, 0, 37), // #360
1908INST(Stumaxb, BaseAtomicSt, (0b0011100000100000011000, kW , 0 ), RWI_RX, 0, 38), // #361
1909INST(Stumaxlb, BaseAtomicSt, (0b0011100001100000011000, kW , 0 ), RWI_RX, 0, 39), // #362
1910INST(Stumaxh, BaseAtomicSt, (0b0111100000100000011000, kW , 0 ), RWI_RX, 0, 40), // #363
1911INST(Stumaxlh, BaseAtomicSt, (0b0111100001100000011000, kW , 0 ), RWI_RX, 0, 41), // #364
1912INST(Stumin, BaseAtomicSt, (0b1011100000100000011100, kWX, 30), RWI_RX, 0, 42), // #365
1913INST(Stuminl, BaseAtomicSt, (0b1011100001100000011100, kWX, 30), RWI_RX, 0, 43), // #366
1914INST(Stuminb, BaseAtomicSt, (0b0011100000100000011100, kW , 0 ), RWI_RX, 0, 44), // #367
1915INST(Stuminlb, BaseAtomicSt, (0b0011100001100000011100, kW , 0 ), RWI_RX, 0, 45), // #368
1916INST(Stuminh, BaseAtomicSt, (0b0111100000100000011100, kW , 0 ), RWI_RX, 0, 46), // #369
1917INST(Stuminlh, BaseAtomicSt, (0b0111100001100000011100, kW , 0 ), RWI_RX, 0, 47), // #370
1918INST(Stur, BaseRMSImm9, (0b1011100000000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0), RWI_RW, 0, 18), // #371
1919INST(Sturb, BaseRMSImm9, (0b0011100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_RW, 0, 19), // #372
1920INST(Sturh, BaseRMSImm9, (0b0111100000000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0), RWI_RW, 0, 20), // #373
1921INST(Stxp, BaseStxp, (0b1000100000100000000000, kWX, 30), RWI_WRRW, 0, 1), // #374
1922INST(Stxr, BaseStx, (0b1000100000000000011111, kWX, 30), RWI_WRW, 0, 0), // #375
1923INST(Stxrb, BaseStx, (0b0000100000000000011111, kW , 0 ), RWI_WRW, 0, 1), // #376
1924INST(Stxrh, BaseStx, (0b0100100000000000011111, kW , 0 ), RWI_WRW, 0, 2), // #377
1925INST(Stz2g, BaseRMSImm9, (0b1101100111100000000010, 0b1101100111100000000001, kX , kSP, 0, 4), RWI_RW, 0, 21), // #378
1926INST(Stzg, BaseRMSImm9, (0b1101100101100000000010, 0b1101100101100000000001, kX , kSP, 0, 4), RWI_RW, 0, 22), // #379
1927INST(Stzgm, BaseRMNoImm, (0b1101100100100000000000, kX , kZR, 0), RWI_RW, 0, 20), // #380
1928INST(Sub, BaseAddSub, (0b1001011000, 0b1001011001, 0b1010001), RWI_W, 0, 2), // #381
1929INST(Subg, BaseRRII, (0b1101000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10), RWI_W, 0, 1), // #382
1930INST(Subp, BaseRRR, (0b1001101011000000000000, kX, kZR, kX, kSP, kX, kSP, false), RWI_W, 0, 20), // #383
1931INST(Subps, BaseRRR, (0b1011101011000000000000, kX, kZR, kX, kSP, kX, kSP, false), RWI_W, 0, 21), // #384
1932INST(Subs, BaseAddSub, (0b1101011000, 0b1101011001, 0b1110001), RWI_W, 0, 3), // #385
1933INST(Svc, BaseOpImm, (0b11010100000000000000000000000001, 16, 5), 0, 0, 13), // #386
1934INST(Swp, BaseAtomicOp, (0b1011100000100000100000, kWX, 30, 1), RWI_RWX, 0, 111), // #387
1935INST(Swpa, BaseAtomicOp, (0b1011100010100000100000, kWX, 30, 1), RWI_RWX, 0, 112), // #388
1936INST(Swpab, BaseAtomicOp, (0b0011100010100000100000, kW , 0 , 1), RWI_RWX, 0, 113), // #389
1937INST(Swpah, BaseAtomicOp, (0b0111100010100000100000, kW , 0 , 1), RWI_RWX, 0, 114), // #390
1938INST(Swpal, BaseAtomicOp, (0b1011100011100000100000, kWX, 30, 1), RWI_RWX, 0, 115), // #391
1939INST(Swpalb, BaseAtomicOp, (0b0011100011100000100000, kW , 0 , 1), RWI_RWX, 0, 116), // #392
1940INST(Swpalh, BaseAtomicOp, (0b0111100011100000100000, kW , 0 , 1), RWI_RWX, 0, 117), // #393
1941INST(Swpb, BaseAtomicOp, (0b0011100000100000100000, kW , 0 , 1), RWI_RWX, 0, 118), // #394
1942INST(Swph, BaseAtomicOp, (0b0111100000100000100000, kW , 0 , 1), RWI_RWX, 0, 119), // #395
1943INST(Swpl, BaseAtomicOp, (0b1011100001100000100000, kWX, 30, 1), RWI_RWX, 0, 120), // #396
1944INST(Swplb, BaseAtomicOp, (0b0011100001100000100000, kW , 0 , 1), RWI_RWX, 0, 121), // #397
1945INST(Swplh, BaseAtomicOp, (0b0111100001100000100000, kW , 0 , 1), RWI_RWX, 0, 122), // #398
1946INST(Sxtb, BaseExtend, (0b0001001100000000000111, kWX, 0), RWI_W, 0, 0), // #399
1947INST(Sxth, BaseExtend, (0b0001001100000000001111, kWX, 0), RWI_W, 0, 1), // #400
1948INST(Sxtw, BaseExtend, (0b1001001101000000011111, kX , 0), RWI_W, 0, 2), // #401
1949INST(Sys, BaseSys, (_), RWI_W, 0, 0), // #402
1950INST(Tlbi, BaseAtDcIcTlbi, (0b00011110000000, 0b00010000000000, false), RWI_RX, 0, 3), // #403
1951INST(Tst, BaseTst, (0b1101010000, 0b111001000), RWI_R, 0, 0), // #404
1952INST(Tbnz, BaseBranchTst, (0b00110111000000000000000000000000), RWI_R, 0, 0), // #405
1953INST(Tbz, BaseBranchTst, (0b00110110000000000000000000000000), RWI_R, 0, 1), // #406
1954INST(Ubfiz, BaseBfi, (0b01010011000000000000000000000000), RWI_W, 0, 2), // #407
1955INST(Ubfm, BaseBfm, (0b01010011000000000000000000000000), RWI_W, 0, 2), // #408
1956INST(Ubfx, BaseBfx, (0b01010011000000000000000000000000), RWI_W, 0, 2), // #409
1957INST(Udf, BaseOpImm, (0b00000000000000000000000000000000, 16, 0), 0, 0, 14), // #410
1958INST(Udiv, BaseRRR, (0b0001101011000000000010, kWX, kZR, kWX, kZR, kWX, kZR, true), RWI_W, 0, 22), // #411
1959INST(Umaddl, BaseRRRR, (0b1001101110100000000000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false), RWI_W, 0, 4), // #412
1960INST(Umax, BaseMinMax, (0b00011010110000000110010000000000, 0b00010001110001000000000000000000), RWI_W, 0, 2), // #413
1961INST(Umin, BaseMinMax, (0b00011010110000000110110000000000, 0b00010001110011000000000000000000), RWI_W, 0, 3), // #414
1962INST(Umnegl, BaseRRR, (0b1001101110100000111111, kX , kZR, kW , kZR, kW , kZR, false), RWI_W, 0, 23), // #415
1963INST(Umull, BaseRRR, (0b1001101110100000011111, kX , kZR, kW , kZR, kW , kZR, false), RWI_W, 0, 24), // #416
1964INST(Umulh, BaseRRR, (0b1001101111000000011111, kX , kZR, kX , kZR, kX , kZR, false), RWI_W, 0, 25), // #417
1965INST(Umsubl, BaseRRRR, (0b1001101110100000100000, kX , kZR, kW , kZR, kW , kZR, kX , kZR, false), RWI_W, 0, 5), // #418
1966INST(Uxtb, BaseExtend, (0b0101001100000000000111, kW, 1), RWI_W, 0, 3), // #419
1967INST(Uxth, BaseExtend, (0b0101001100000000001111, kW, 1), RWI_W, 0, 4), // #420
1968INST(Wfe, BaseOp, (0b11010101000000110010000001011111), 0, 0, 19), // #421
1969INST(Wfi, BaseOp, (0b11010101000000110010000001111111), 0, 0, 20), // #422
1970INST(Xaflag, BaseOp, (0b11010101000000000100000000111111), 0, 0, 21), // #423
1971INST(Xpacd, BaseR, (0b11011010110000010100011111100000, kX, kZR, 0), RWI_X, 0, 8), // #424
1972INST(Xpaci, BaseR, (0b11011010110000010100001111100000, kX, kZR, 0), RWI_X, 0, 9), // #425
1973INST(Xpaclri, BaseOp, (0b11010101000000110010000011111111), RWI_X, 0, 22), // #426
1974INST(Yield, BaseOp, (0b11010101000000110010000000111111), 0, 0, 23), // #427
1975INST(Abs_v, ISimdVV, (0b0000111000100000101110, kVO_V_Any), RWI_W, 0, 0), // #428
1976INST(Add_v, ISimdVVV, (0b0000111000100000100001, kVO_V_Any), RWI_W, 0, 0), // #429
1977INST(Addhn_v, ISimdVVV, (0b0000111000100000010000, kVO_V_B8H4S2), RWI_W, F!(Narrow), 1), // #430
1978INST(Addhn2_v, ISimdVVV, (0b0100111000100000010000, kVO_V_B16H8S4), RWI_W, F!(Narrow), 2), // #431
1979INST(Addp_v, ISimdPair, (0b0101111000110001101110, 0b0000111000100000101111, kVO_V_Any), RWI_W, F!(Pair), 0), // #432
1980INST(Addv_v, ISimdSV, (0b0000111000110001101110, kVO_V_BH_4S), RWI_W, 0, 0), // #433
1981INST(Aesd_v, ISimdVVx, (0b0100111000101000010110, kOp_V16B, kOp_V16B), RWI_X, 0, 0), // #434
1982INST(Aese_v, ISimdVVx, (0b0100111000101000010010, kOp_V16B, kOp_V16B), RWI_X, 0, 1), // #435
1983INST(Aesimc_v, ISimdVVx, (0b0100111000101000011110, kOp_V16B, kOp_V16B), RWI_W, 0, 2), // #436
1984INST(Aesmc_v, ISimdVVx, (0b0100111000101000011010, kOp_V16B, kOp_V16B), RWI_W, 0, 3), // #437
1985INST(And_v, ISimdVVV, (0b0000111000100000000111, kVO_V_B), RWI_W, 0, 3), // #438
1986INST(Bcax_v, ISimdVVVV, (0b1100111000100000000000, kVO_V_B16), RWI_W, 0, 0), // #439
1987INST(Bfcvt_v, ISimdVVx, (0b0001111001100011010000, kOp_H, kOp_S), RWI_W, 0, 4), // #440
1988INST(Bfcvtn_v, ISimdVVx, (0b0000111010100001011010, kOp_V4H, kOp_V4S), RWI_W, F!(Narrow), 5), // #441
1989INST(Bfcvtn2_v, ISimdVVx, (0b0100111010100001011010, kOp_V8H, kOp_V4S), RWI_W, F!(Narrow), 6), // #442
1990INST(Bfdot_v, SimdDot, (0b0010111001000000111111, 0b0000111101000000111100, kET_S, kET_H, kET_2H), RWI_X, 0, 0), // #443
1991INST(Bfmlalb_v, SimdFmlal, (0b0010111011000000111111, 0b0000111111000000111100, 0, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 0), // #444
1992INST(Bfmlalt_v, SimdFmlal, (0b0110111011000000111111, 0b0100111111000000111100, 0, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 1), // #445
1993INST(Bfmmla_v, ISimdVVVx, (0b0110111001000000111011, kOp_V4S, kOp_V8H, kOp_V8H), RWI_X, F!(Long), 0), // #446
1994INST(Bic_v, SimdBicOrr, (0b0000111001100000000111, 0b0010111100000000000001), RWI_W, 0, 0), // #447
1995INST(Bif_v, ISimdVVV, (0b0010111011100000000111, kVO_V_B), RWI_X, 0, 4), // #448
1996INST(Bit_v, ISimdVVV, (0b0010111010100000000111, kVO_V_B), RWI_X, 0, 5), // #449
1997INST(Bsl_v, ISimdVVV, (0b0010111001100000000111, kVO_V_B), RWI_X, 0, 6), // #450
1998INST(Cls_v, ISimdVV, (0b0000111000100000010010, kVO_V_BHS), RWI_W, 0, 1), // #451
1999INST(Clz_v, ISimdVV, (0b0010111000100000010010, kVO_V_BHS), RWI_W, 0, 2), // #452
2000INST(Cmeq_v, SimdCmp, (0b0010111000100000100011, 0b0000111000100000100110, kVO_V_Any), RWI_W, 0, 0), // #453
2001INST(Cmge_v, SimdCmp, (0b0000111000100000001111, 0b0010111000100000100010, kVO_V_Any), RWI_W, 0, 1), // #454
2002INST(Cmgt_v, SimdCmp, (0b0000111000100000001101, 0b0000111000100000100010, kVO_V_Any), RWI_W, 0, 2), // #455
2003INST(Cmhi_v, SimdCmp, (0b0010111000100000001101, 0b0000000000000000000000, kVO_V_Any), RWI_W, 0, 3), // #456
2004INST(Cmhs_v, SimdCmp, (0b0010111000100000001111, 0b0000000000000000000000, kVO_V_Any), RWI_W, 0, 4), // #457
2005INST(Cmle_v, SimdCmp, (0b0000000000000000000000, 0b0010111000100000100110, kVO_V_Any), RWI_W, 0, 5), // #458
2006INST(Cmlt_v, SimdCmp, (0b0000000000000000000000, 0b0000111000100000101010, kVO_V_Any), RWI_W, 0, 6), // #459
2007INST(Cmtst_v, ISimdVVV, (0b0000111000100000100011, kVO_V_Any), RWI_W, 0, 7), // #460
2008INST(Cnt_v, ISimdVV, (0b0000111000100000010110, kVO_V_B), RWI_W, 0, 3), // #461
2009INST(Dup_v, SimdDup, (_), RWI_W, 0, 0), // #462
2010INST(Eor_v, ISimdVVV, (0b0010111000100000000111, kVO_V_B), RWI_W, 0, 8), // #463
2011INST(Eor3_v, ISimdVVVV, (0b1100111000000000000000, kVO_V_B16), RWI_W, 0, 1), // #464
2012INST(Ext_v, ISimdVVVI, (0b0010111000000000000000, kVO_V_B, 4, 11, 1), RWI_W, 0, 0), // #465
2013INST(Fabd_v, FSimdVVV, (0b0111111010100000110101, kHF_C, 0b0010111010100000110101, kHF_C), RWI_W, 0, 0), // #466
2014INST(Fabs_v, FSimdVV, (0b0001111000100000110000, kHF_A, 0b0000111010100000111110, kHF_B), RWI_W, 0, 0), // #467
2015INST(Facge_v, FSimdVVV, (0b0111111000100000111011, kHF_C, 0b0010111000100000111011, kHF_C), RWI_W, 0, 1), // #468
2016INST(Facgt_v, FSimdVVV, (0b0111111010100000111011, kHF_C, 0b0010111010100000111011, kHF_C), RWI_W, 0, 2), // #469
2017INST(Fadd_v, FSimdVVV, (0b0001111000100000001010, kHF_A, 0b0000111000100000110101, kHF_C), RWI_W, 0, 3), // #470
2018INST(Faddp_v, FSimdPair, (0b0111111000110000110110, 0b0010111000100000110101), RWI_W, 0, 0), // #471
2019INST(Fcadd_v, SimdFcadd, (0b0010111000000000111001), RWI_W, 0, 0), // #472
2020INST(Fccmp_v, SimdFccmpFccmpe, (0b00011110001000000000010000000000), RWI_R, 0, 0), // #473
2021INST(Fccmpe_v, SimdFccmpFccmpe, (0b00011110001000000000010000010000), RWI_R, 0, 1), // #474
2022INST(Fcmeq_v, SimdFcm, (0b0000111000100000111001, kHF_C, 0b0000111010100000110110), RWI_W, 0, 0), // #475
2023INST(Fcmge_v, SimdFcm, (0b0010111000100000111001, kHF_C, 0b0010111010100000110010), RWI_W, 0, 1), // #476
2024INST(Fcmgt_v, SimdFcm, (0b0010111010100000111001, kHF_C, 0b0000111010100000110010), RWI_W, 0, 2), // #477
2025INST(Fcmla_v, SimdFcmla, (0b0010111000000000110001, 0b0010111100000000000100), RWI_X, 0, 0), // #478
2026INST(Fcmle_v, SimdFcm, (0b0000000000000000000000, kHF_C, 0b0010111010100000110110), RWI_W, 0, 3), // #479
2027INST(Fcmlt_v, SimdFcm, (0b0000000000000000000000, kHF_C, 0b0000111010100000111010), RWI_W, 0, 4), // #480
2028INST(Fcmp_v, SimdFcmpFcmpe, (0b00011110001000000010000000000000), RWI_R, 0, 0), // #481
2029INST(Fcmpe_v, SimdFcmpFcmpe, (0b00011110001000000010000000010000), RWI_R, 0, 1), // #482
2030INST(Fcsel_v, SimdFcsel, (_), RWI_W, 0, 0), // #483
2031INST(Fcvt_v, SimdFcvt, (_), RWI_W, 0, 0), // #484
2032INST(Fcvtas_v, SimdFcvtSV, (0b0000111000100001110010, 0b0000000000000000000000, 0b0001111000100100000000, 1), RWI_W, 0, 0), // #485
2033INST(Fcvtau_v, SimdFcvtSV, (0b0010111000100001110010, 0b0000000000000000000000, 0b0001111000100101000000, 1), RWI_W, 0, 1), // #486
2034INST(Fcvtl_v, SimdFcvtLN, (0b0000111000100001011110, 0, 0), RWI_W, F!(Long), 0), // #487
2035INST(Fcvtl2_v, SimdFcvtLN, (0b0100111000100001011110, 0, 0), RWI_W, F!(Long), 1), // #488
2036INST(Fcvtms_v, SimdFcvtSV, (0b0000111000100001101110, 0b0000000000000000000000, 0b0001111000110000000000, 1), RWI_W, 0, 2), // #489
2037INST(Fcvtmu_v, SimdFcvtSV, (0b0010111000100001101110, 0b0000000000000000000000, 0b0001111000110001000000, 1), RWI_W, 0, 3), // #490
2038INST(Fcvtn_v, SimdFcvtLN, (0b0000111000100001011010, 0, 0), RWI_W, F!(Narrow), 2), // #491
2039INST(Fcvtn2_v, SimdFcvtLN, (0b0100111000100001011010, 0, 0), RWI_X, F!(Narrow), 3), // #492
2040INST(Fcvtns_v, SimdFcvtSV, (0b0000111000100001101010, 0b0000000000000000000000, 0b0001111000100000000000, 1), RWI_W, 0, 4), // #493
2041INST(Fcvtnu_v, SimdFcvtSV, (0b0010111000100001101010, 0b0000000000000000000000, 0b0001111000100001000000, 1), RWI_W, 0, 5), // #494
2042INST(Fcvtps_v, SimdFcvtSV, (0b0000111010100001101010, 0b0000000000000000000000, 0b0001111000101000000000, 1), RWI_W, 0, 6), // #495
2043INST(Fcvtpu_v, SimdFcvtSV, (0b0010111010100001101010, 0b0000000000000000000000, 0b0001111000101001000000, 1), RWI_W, 0, 7), // #496
2044INST(Fcvtxn_v, SimdFcvtLN, (0b0010111000100001011010, 1, 1), RWI_W, F!(Narrow), 4), // #497
2045INST(Fcvtxn2_v, SimdFcvtLN, (0b0110111000100001011010, 1, 0), RWI_X, F!(Narrow), 5), // #498
2046INST(Fcvtzs_v, SimdFcvtSV, (0b0000111010100001101110, 0b0000111100000000111111, 0b0001111000111000000000, 1), RWI_W, 0, 8), // #499
2047INST(Fcvtzu_v, SimdFcvtSV, (0b0010111010100001101110, 0b0010111100000000111111, 0b0001111000111001000000, 1), RWI_W, 0, 9), // #500
2048INST(Fdiv_v, FSimdVVV, (0b0001111000100000000110, kHF_A, 0b0010111000100000111111, kHF_C), RWI_W, 0, 4), // #501
2049INST(Fjcvtzs_v, ISimdVVx, (0b0001111001111110000000, kOp_GpW, kOp_D), RWI_W, 0, 7), // #502
2050INST(Fmadd_v, FSimdVVVV, (0b0001111100000000000000, kHF_A, 0b0000000000000000000000, kHF_N), RWI_W, 0, 0), // #503
2051INST(Fmax_v, FSimdVVV, (0b0001111000100000010010, kHF_A, 0b0000111000100000111101, kHF_C), RWI_W, 0, 5), // #504
2052INST(Fmaxnm_v, FSimdVVV, (0b0001111000100000011010, kHF_A, 0b0000111000100000110001, kHF_C), RWI_W, 0, 6), // #505
2053INST(Fmaxnmp_v, FSimdPair, (0b0111111000110000110010, 0b0010111000100000110001), RWI_W, 0, 1), // #506
2054INST(Fmaxnmv_v, FSimdSV, (0b0010111000110000110010), RWI_W, 0, 0), // #507
2055INST(Fmaxp_v, FSimdPair, (0b0111111000110000111110, 0b0010111000100000111101), RWI_W, 0, 2), // #508
2056INST(Fmaxv_v, FSimdSV, (0b0010111000110000111110), RWI_W, 0, 1), // #509
2057INST(Fmin_v, FSimdVVV, (0b0001111000100000010110, kHF_A, 0b0000111010100000111101, kHF_C), RWI_W, 0, 7), // #510
2058INST(Fminnm_v, FSimdVVV, (0b0001111000100000011110, kHF_A, 0b0000111010100000110001, kHF_C), RWI_W, 0, 8), // #511
2059INST(Fminnmp_v, FSimdPair, (0b0111111010110000110010, 0b0010111010100000110001), RWI_W, 0, 3), // #512
2060INST(Fminnmv_v, FSimdSV, (0b0010111010110000110010), RWI_W, 0, 2), // #513
2061INST(Fminp_v, FSimdPair, (0b0111111010110000111110, 0b0010111010100000111101), RWI_W, 0, 4), // #514
2062INST(Fminv_v, FSimdSV, (0b0010111010110000111110), RWI_W, 0, 3), // #515
2063INST(Fmla_v, FSimdVVVe, (0b0000000000000000000000, kHF_N, 0b0000111000100000110011, 0b0000111110000000000100), RWI_X, F!(VH0_15), 0), // #516
2064INST(Fmlal_v, SimdFmlal, (0b0000111000100000111011, 0b0000111110000000000000, 1, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 2), // #517
2065INST(Fmlal2_v, SimdFmlal, (0b0010111000100000110011, 0b0010111110000000100000, 1, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 3), // #518
2066INST(Fmls_v, FSimdVVVe, (0b0000000000000000000000, kHF_N, 0b0000111010100000110011, 0b0000111110000000010100), RWI_X, F!(VH0_15), 1), // #519
2067INST(Fmlsl_v, SimdFmlal, (0b0000111010100000111011, 0b0000111110000000010000, 1, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 4), // #520
2068INST(Fmlsl2_v, SimdFmlal, (0b0010111010100000110011, 0b0010111110000000110000, 1, kET_S, kET_H, kET_H), RWI_X, F!(VH0_15), 5), // #521
2069INST(Fmov_v, SimdFmov, (_), RWI_W, 0, 0), // #522
2070INST(Fmsub_v, FSimdVVVV, (0b0001111100000000100000, kHF_A, 0b0000000000000000000000, kHF_N), RWI_W, 0, 1), // #523
2071INST(Fmul_v, FSimdVVVe, (0b0001111000100000000010, kHF_A, 0b0010111000100000110111, 0b0000111110000000100100), RWI_W, F!(VH0_15), 2), // #524
2072INST(Fmulx_v, FSimdVVVe, (0b0101111000100000110111, kHF_C, 0b0000111000100000110111, 0b0010111110000000100100), RWI_W, F!(VH0_15), 3), // #525
2073INST(Fneg_v, FSimdVV, (0b0001111000100001010000, kHF_A, 0b0010111010100000111110, kHF_B), RWI_W, 0, 1), // #526
2074INST(Fnmadd_v, FSimdVVVV, (0b0001111100100000000000, kHF_A, 0b0000000000000000000000, kHF_N), RWI_W, 0, 2), // #527
2075INST(Fnmsub_v, FSimdVVVV, (0b0001111100100000100000, kHF_A, 0b0000000000000000000000, kHF_N), RWI_W, 0, 3), // #528
2076INST(Fnmul_v, FSimdVVV, (0b0001111000100000100010, kHF_A, 0b0000000000000000000000, kHF_N), RWI_W, 0, 9), // #529
2077INST(Frecpe_v, FSimdVV, (0b0101111010100001110110, kHF_B, 0b0000111010100001110110, kHF_B), RWI_W, 0, 2), // #530
2078INST(Frecps_v, FSimdVVV, (0b0101111000100000111111, kHF_C, 0b0000111000100000111111, kHF_C), RWI_W, 0, 10), // #531
2079INST(Frecpx_v, FSimdVV, (0b0101111010100001111110, kHF_B, 0b0000000000000000000000, kHF_N), RWI_W, 0, 3), // #532
2080INST(Frint32x_v, FSimdVV, (0b0001111000101000110000, kHF_N, 0b0010111000100001111010, kHF_N), RWI_W, 0, 4), // #533
2081INST(Frint32z_v, FSimdVV, (0b0001111000101000010000, kHF_N, 0b0000111000100001111010, kHF_N), RWI_W, 0, 5), // #534
2082INST(Frint64x_v, FSimdVV, (0b0001111000101001110000, kHF_N, 0b0010111000100001111110, kHF_N), RWI_W, 0, 6), // #535
2083INST(Frint64z_v, FSimdVV, (0b0001111000101001010000, kHF_N, 0b0000111000100001111110, kHF_N), RWI_W, 0, 7), // #536
2084INST(Frinta_v, FSimdVV, (0b0001111000100110010000, kHF_A, 0b0010111000100001100010, kHF_B), RWI_W, 0, 8), // #537
2085INST(Frinti_v, FSimdVV, (0b0001111000100111110000, kHF_A, 0b0010111010100001100110, kHF_B), RWI_W, 0, 9), // #538
2086INST(Frintm_v, FSimdVV, (0b0001111000100101010000, kHF_A, 0b0000111000100001100110, kHF_B), RWI_W, 0, 10), // #539
2087INST(Frintn_v, FSimdVV, (0b0001111000100100010000, kHF_A, 0b0000111000100001100010, kHF_B), RWI_W, 0, 11), // #540
2088INST(Frintp_v, FSimdVV, (0b0001111000100100110000, kHF_A, 0b0000111010100001100010, kHF_B), RWI_W, 0, 12), // #541
2089INST(Frintx_v, FSimdVV, (0b0001111000100111010000, kHF_A, 0b0010111000100001100110, kHF_B), RWI_W, 0, 13), // #542
2090INST(Frintz_v, FSimdVV, (0b0001111000100101110000, kHF_A, 0b0000111010100001100110, kHF_B), RWI_W, 0, 14), // #543
2091INST(Frsqrte_v, FSimdVV, (0b0111111010100001110110, kHF_B, 0b0010111010100001110110, kHF_B), RWI_W, 0, 15), // #544
2092INST(Frsqrts_v, FSimdVVV, (0b0101111010100000111111, kHF_C, 0b0000111010100000111111, kHF_C), RWI_W, 0, 11), // #545
2093INST(Fsqrt_v, FSimdVV, (0b0001111000100001110000, kHF_A, 0b0010111010100001111110, kHF_B), RWI_W, 0, 16), // #546
2094INST(Fsub_v, FSimdVVV, (0b0001111000100000001110, kHF_A, 0b0000111010100000110101, kHF_C), RWI_W, 0, 12), // #547
2095INST(Ins_v, SimdIns, (_), RWI_X, 0, 0), // #548
2096INST(Ld1_v, SimdLdNStN, (0b0000110101000000000000, 0b0000110001000000001000, 1, 0), RWI_LDN, F!(Consecutive), 0), // #549
2097INST(Ld1r_v, SimdLdNStN, (0b0000110101000000110000, 0b0000000000000000000000, 1, 1), RWI_LDN, F!(Consecutive), 1), // #550
2098INST(Ld2_v, SimdLdNStN, (0b0000110101100000000000, 0b0000110001000000100000, 2, 0), RWI_LDN, F!(Consecutive), 2), // #551
2099INST(Ld2r_v, SimdLdNStN, (0b0000110101100000110000, 0b0000000000000000000000, 2, 1), RWI_LDN, F!(Consecutive), 3), // #552
2100INST(Ld3_v, SimdLdNStN, (0b0000110101000000001000, 0b0000110001000000010000, 3, 0), RWI_LDN, F!(Consecutive), 4), // #553
2101INST(Ld3r_v, SimdLdNStN, (0b0000110101000000111000, 0b0000000000000000000000, 3, 1), RWI_LDN, F!(Consecutive), 5), // #554
2102INST(Ld4_v, SimdLdNStN, (0b0000110101100000001000, 0b0000110001000000000000, 4, 0), RWI_LDN, F!(Consecutive), 6), // #555
2103INST(Ld4r_v, SimdLdNStN, (0b0000110101100000111000, 0b0000000000000000000000, 4, 1), RWI_LDN, F!(Consecutive), 7), // #556
2104INST(Ldnp_v, SimdLdpStp, (0b0010110001, 0b0000000000), RWI_WW, 0, 0), // #557
2105INST(Ldp_v, SimdLdpStp, (0b0010110101, 0b0010110011), RWI_WW, 0, 1), // #558
2106INST(Ldr_v, SimdLdSt, (0b0011110101, 0b00111100010, 0b00111100011, 0b00011100, InstId::Ldur_v), RWI_W, 0, 0), // #559
2107INST(Ldur_v, SimdLdurStur, (0b0011110001000000000000), RWI_W, 0, 0), // #560
2108INST(Mla_v, ISimdVVVe, (0b0000111000100000100101, kVO_V_BHS, 0b0010111100000000000000, kVO_V_HS), RWI_X, F!(VH0_15), 0), // #561
2109INST(Mls_v, ISimdVVVe, (0b0010111000100000100101, kVO_V_BHS, 0b0010111100000000010000, kVO_V_HS), RWI_X, F!(VH0_15), 1), // #562
2110INST(Mov_v, SimdMov, (_), RWI_W, 0, 0), // #563
2111INST(Movi_v, SimdMoviMvni, (0b0000111100000000000001, 0), RWI_W, 0, 0), // #564
2112INST(Mul_v, ISimdVVVe, (0b0000111000100000100111, kVO_V_BHS, 0b0000111100000000100000, kVO_V_HS), RWI_W, F!(VH0_15), 2), // #565
2113INST(Mvn_v, ISimdVV, (0b0010111000100000010110, kVO_V_B), RWI_W, 0, 4), // #566
2114INST(Mvni_v, SimdMoviMvni, (0b0000111100000000000001, 1), RWI_W, 0, 1), // #567
2115INST(Neg_v, ISimdVV, (0b0010111000100000101110, kVO_V_Any), RWI_W, 0, 5), // #568
2116INST(Not_v, ISimdVV, (0b0010111000100000010110, kVO_V_B), RWI_W, 0, 6), // #569
2117INST(Orn_v, ISimdVVV, (0b0000111011100000000111, kVO_V_B), RWI_W, 0, 9), // #570
2118INST(Orr_v, SimdBicOrr, (0b0000111010100000000111, 0b0000111100000000000001), RWI_W, 0, 1), // #571
2119INST(Pmul_v, ISimdVVV, (0b0010111000100000100111, kVO_V_B), RWI_W, 0, 10), // #572
2120INST(Pmull_v, ISimdVVV, (0b0000111000100000111000, kVO_V_B8D1), RWI_W, F!(Long), 11), // #573
2121INST(Pmull2_v, ISimdVVV, (0b0100111000100000111000, kVO_V_B16D2), RWI_W, F!(Long), 12), // #574
2122INST(Raddhn_v, ISimdVVV, (0b0010111000100000010000, kVO_V_B8H4S2), RWI_W, F!(Narrow), 13), // #575
2123INST(Raddhn2_v, ISimdVVV, (0b0110111000100000010000, kVO_V_B16H8S4), RWI_X, F!(Narrow), 14), // #576
2124INST(Rax1_v, ISimdVVV, (0b1100111001100000100011, kVO_V_D2), RWI_W, 0, 15), // #577
2125INST(Rbit_v, ISimdVV, (0b0010111001100000010110, kVO_V_B), RWI_W, 0, 7), // #578
2126INST(Rev16_v, ISimdVV, (0b0000111000100000000110, kVO_V_B), RWI_W, 0, 8), // #579
2127INST(Rev32_v, ISimdVV, (0b0010111000100000000010, kVO_V_BH), RWI_W, 0, 9), // #580
2128INST(Rev64_v, ISimdVV, (0b0000111000100000000010, kVO_V_BHS), RWI_W, 0, 10), // #581
2129INST(Rshrn_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000100011, 1, kVO_V_B8H4S2), RWI_W, F!(Narrow), 0), // #582
2130INST(Rshrn2_v, SimdShift, (0b0000000000000000000000, 0b0100111100000000100011, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 1), // #583
2131INST(Rsubhn_v, ISimdVVV, (0b0010111000100000011000, kVO_V_B8H4S2), RWI_W, F!(Narrow), 16), // #584
2132INST(Rsubhn2_v, ISimdVVV, (0b0110111000100000011000, kVO_V_B16H8S4), RWI_X, F!(Narrow), 17), // #585
2133INST(Saba_v, ISimdVVV, (0b0000111000100000011111, kVO_V_BHS), RWI_X, 0, 18), // #586
2134INST(Sabal_v, ISimdVVV, (0b0000111000100000010100, kVO_V_B8H4S2), RWI_X, F!(Long), 19), // #587
2135INST(Sabal2_v, ISimdVVV, (0b0100111000100000010100, kVO_V_B16H8S4), RWI_X, F!(Long), 20), // #588
2136INST(Sabd_v, ISimdVVV, (0b0000111000100000011101, kVO_V_BHS), RWI_W, 0, 21), // #589
2137INST(Sabdl_v, ISimdVVV, (0b0000111000100000011100, kVO_V_B8H4S2), RWI_W, F!(Long), 22), // #590
2138INST(Sabdl2_v, ISimdVVV, (0b0100111000100000011100, kVO_V_B16H8S4), RWI_W, F!(Long), 23), // #591
2139INST(Sadalp_v, ISimdVV, (0b0000111000100000011010, kVO_V_BHS), RWI_X, F!(Long) | F!(Pair), 11), // #592
2140INST(Saddl_v, ISimdVVV, (0b0000111000100000000000, kVO_V_B8H4S2), RWI_W, F!(Long), 24), // #593
2141INST(Saddl2_v, ISimdVVV, (0b0100111000100000000000, kVO_V_B16H8S4), RWI_W, F!(Long), 25), // #594
2142INST(Saddlp_v, ISimdVV, (0b0000111000100000001010, kVO_V_BHS), RWI_W, F!(Long) | F!(Pair), 12), // #595
2143INST(Saddlv_v, ISimdSV, (0b0000111000110000001110, kVO_V_BH_4S), RWI_W, F!(Long), 1), // #596
2144INST(Saddw_v, ISimdWWV, (0b0000111000100000000100, kVO_V_B8H4S2), RWI_W, 0, 0), // #597
2145INST(Saddw2_v, ISimdWWV, (0b0000111000100000000100, kVO_V_B16H8S4), RWI_W, 0, 1), // #598
2146INST(Scvtf_v, SimdFcvtSV, (0b0000111000100001110110, 0b0000111100000000111001, 0b0001111000100010000000, 0), RWI_W, 0, 10), // #599
2147INST(Sdot_v, SimdDot, (0b0000111010000000100101, 0b0000111110000000111000, kET_S, kET_B, kET_4B), RWI_X, 0, 1), // #600
2148INST(Sha1c_v, ISimdVVVx, (0b0101111000000000000000, kOp_Q, kOp_S, kOp_V4S), RWI_X, 0, 1), // #601
2149INST(Sha1h_v, ISimdVVx, (0b0101111000101000000010, kOp_S, kOp_S), RWI_W, 0, 8), // #602
2150INST(Sha1m_v, ISimdVVVx, (0b0101111000000000001000, kOp_Q, kOp_S, kOp_V4S), RWI_X, 0, 2), // #603
2151INST(Sha1p_v, ISimdVVVx, (0b0101111000000000000100, kOp_Q, kOp_S, kOp_V4S), RWI_X, 0, 3), // #604
2152INST(Sha1su0_v, ISimdVVVx, (0b0101111000000000001100, kOp_V4S, kOp_V4S, kOp_V4S), RWI_X, 0, 4), // #605
2153INST(Sha1su1_v, ISimdVVx, (0b0101111000101000000110, kOp_V4S, kOp_V4S), RWI_X, 0, 9), // #606
2154INST(Sha256h_v, ISimdVVVx, (0b0101111000000000010000, kOp_Q, kOp_Q, kOp_V4S), RWI_X, 0, 5), // #607
2155INST(Sha256h2_v, ISimdVVVx, (0b0101111000000000010100, kOp_Q, kOp_Q, kOp_V4S), RWI_X, 0, 6), // #608
2156INST(Sha256su0_v, ISimdVVx, (0b0101111000101000001010, kOp_V4S, kOp_V4S), RWI_X, 0, 10), // #609
2157INST(Sha256su1_v, ISimdVVVx, (0b0101111000000000011000, kOp_V4S, kOp_V4S, kOp_V4S), RWI_X, 0, 7), // #610
2158INST(Sha512h_v, ISimdVVVx, (0b1100111001100000100000, kOp_Q, kOp_Q, kOp_V2D), RWI_X, 0, 8), // #611
2159INST(Sha512h2_v, ISimdVVVx, (0b1100111001100000100001, kOp_Q, kOp_Q, kOp_V2D), RWI_X, 0, 9), // #612
2160INST(Sha512su0_v, ISimdVVx, (0b1100111011000000100000, kOp_V2D, kOp_V2D), RWI_X, 0, 11), // #613
2161INST(Sha512su1_v, ISimdVVVx, (0b1100111001100000100010, kOp_V2D, kOp_V2D, kOp_V2D), RWI_X, 0, 10), // #614
2162INST(Shadd_v, ISimdVVV, (0b0000111000100000000001, kVO_V_BHS), RWI_W, 0, 26), // #615
2163INST(Shl_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000010101, 0, kVO_V_Any), RWI_W, 0, 2), // #616
2164INST(Shll_v, SimdShiftES, (0b0010111000100001001110, kVO_V_B8H4S2), RWI_W, F!(Long), 0), // #617
2165INST(Shll2_v, SimdShiftES, (0b0110111000100001001110, kVO_V_B16H8S4), RWI_W, F!(Long), 1), // #618
2166INST(Shrn_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000100001, 1, kVO_V_B8H4S2), RWI_W, F!(Narrow), 3), // #619
2167INST(Shrn2_v, SimdShift, (0b0000000000000000000000, 0b0100111100000000100001, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 4), // #620
2168INST(Shsub_v, ISimdVVV, (0b0000111000100000001001, kVO_V_BHS), RWI_W, 0, 27), // #621
2169INST(Sli_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000010101, 0, kVO_V_Any), RWI_X, 0, 5), // #622
2170INST(Sm3partw1_v, ISimdVVVx, (0b1100111001100000110000, kOp_V4S, kOp_V4S, kOp_V4S), RWI_X, 0, 11), // #623
2171INST(Sm3partw2_v, ISimdVVVx, (0b1100111001100000110001, kOp_V4S, kOp_V4S, kOp_V4S), RWI_X, 0, 12), // #624
2172INST(Sm3ss1_v, ISimdVVVVx, (0b1100111001000000000000, kOp_V4S, kOp_V4S, kOp_V4S, kOp_V4S), RWI_W, 0, 0), // #625
2173INST(Sm3tt1a_v, SimdSm3tt, (0b1100111001000000100000), RWI_X, 0, 0), // #626
2174INST(Sm3tt1b_v, SimdSm3tt, (0b1100111001000000100001), RWI_X, 0, 1), // #627
2175INST(Sm3tt2a_v, SimdSm3tt, (0b1100111001000000100010), RWI_X, 0, 2), // #628
2176INST(Sm3tt2b_v, SimdSm3tt, (0b1100111001000000100011), RWI_X, 0, 3), // #629
2177INST(Sm4e_v, ISimdVVx, (0b1100111011000000100001, kOp_V4S, kOp_V4S), RWI_X, 0, 12), // #630
2178INST(Sm4ekey_v, ISimdVVVx, (0b1100111001100000110010, kOp_V4S, kOp_V4S, kOp_V4S), RWI_X, 0, 13), // #631
2179INST(Smax_v, ISimdVVV, (0b0000111000100000011001, kVO_V_BHS), RWI_W, 0, 28), // #632
2180INST(Smaxp_v, ISimdVVV, (0b0000111000100000101001, kVO_V_BHS), RWI_W, 0, 29), // #633
2181INST(Smaxv_v, ISimdSV, (0b0000111000110000101010, kVO_V_BH_4S), RWI_W, 0, 2), // #634
2182INST(Smin_v, ISimdVVV, (0b0000111000100000011011, kVO_V_BHS), RWI_W, 0, 30), // #635
2183INST(Sminp_v, ISimdVVV, (0b0000111000100000101011, kVO_V_BHS), RWI_W, 0, 31), // #636
2184INST(Sminv_v, ISimdSV, (0b0000111000110001101010, kVO_V_BH_4S), RWI_W, 0, 3), // #637
2185INST(Smlal_v, ISimdVVVe, (0b0000111000100000100000, kVO_V_B8H4S2, 0b0000111100000000001000, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 3), // #638
2186INST(Smlal2_v, ISimdVVVe, (0b0100111000100000100000, kVO_V_B16H8S4, 0b0100111100000000001000, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 4), // #639
2187INST(Smlsl_v, ISimdVVVe, (0b0000111000100000101000, kVO_V_B8H4S2, 0b0000111100000000011000, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 5), // #640
2188INST(Smlsl2_v, ISimdVVVe, (0b0100111000100000101000, kVO_V_B16H8S4, 0b0100111100000000011000, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 6), // #641
2189INST(Smmla_v, ISimdVVVx, (0b0100111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B), RWI_X, 0, 14), // #642
2190INST(Smov_v, SimdSmovUmov, (0b0000111000000000001011, kVO_V_BHS, 1), RWI_W, 0, 0), // #643
2191INST(Smull_v, ISimdVVVe, (0b0000111000100000110000, kVO_V_B8H4S2, 0b0000111100000000101000, kVO_V_H4S2), RWI_W, F!(Long) | F!(VH0_15), 7), // #644
2192INST(Smull2_v, ISimdVVVe, (0b0100111000100000110000, kVO_V_B16H8S4, 0b0100111100000000101000, kVO_V_H8S4), RWI_W, F!(Long) | F!(VH0_15), 8), // #645
2193INST(Sqabs_v, ISimdVV, (0b0000111000100000011110, kVO_SV_Any), RWI_W, 0, 13), // #646
2194INST(Sqadd_v, ISimdVVV, (0b0000111000100000000011, kVO_SV_Any), RWI_W, 0, 32), // #647
2195INST(Sqdmlal_v, ISimdVVVe, (0b0000111000100000100100, kVO_SV_BHS, 0b0000111100000000001100, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 9), // #648
2196INST(Sqdmlal2_v, ISimdVVVe, (0b0100111000100000100100, kVO_V_B16H8S4, 0b0100111100000000001100, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 10), // #649
2197INST(Sqdmlsl_v, ISimdVVVe, (0b0000111000100000101100, kVO_SV_BHS, 0b0000111100000000011100, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 11), // #650
2198INST(Sqdmlsl2_v, ISimdVVVe, (0b0100111000100000101100, kVO_V_B16H8S4, 0b0100111100000000011100, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 12), // #651
2199INST(Sqdmulh_v, ISimdVVVe, (0b0000111000100000101101, kVO_SV_HS, 0b0000111100000000110000, kVO_SV_HS), RWI_W, F!(VH0_15), 13), // #652
2200INST(Sqdmull_v, ISimdVVVe, (0b0000111000100000110100, kVO_SV_BHS, 0b0000111100000000101100, kVO_V_H4S2), RWI_W, F!(Long) | F!(VH0_15), 14), // #653
2201INST(Sqdmull2_v, ISimdVVVe, (0b0100111000100000110100, kVO_V_B16H8S4, 0b0100111100000000101100, kVO_V_H8S4), RWI_W, F!(Long) | F!(VH0_15), 15), // #654
2202INST(Sqneg_v, ISimdVV, (0b0010111000100000011110, kVO_SV_Any), RWI_W, 0, 14), // #655
2203INST(Sqrdmlah_v, ISimdVVVe, (0b0010111000000000100001, kVO_SV_HS, 0b0010111100000000110100, kVO_SV_HS), RWI_X, F!(VH0_15), 16), // #656
2204INST(Sqrdmlsh_v, ISimdVVVe, (0b0010111000000000100011, kVO_SV_HS, 0b0010111100000000111100, kVO_SV_HS), RWI_X, F!(VH0_15), 17), // #657
2205INST(Sqrdmulh_v, ISimdVVVe, (0b0010111000100000101101, kVO_SV_HS, 0b0000111100000000110100, kVO_SV_HS), RWI_W, F!(VH0_15), 18), // #658
2206INST(Sqrshl_v, SimdShift, (0b0000111000100000010111, 0b0000000000000000000000, 1, kVO_SV_Any), RWI_W, 0, 6), // #659
2207INST(Sqrshrn_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000100111, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 7), // #660
2208INST(Sqrshrn2_v, SimdShift, (0b0000000000000000000000, 0b0100111100000000100111, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 8), // #661
2209INST(Sqrshrun_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000100011, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 9), // #662
2210INST(Sqrshrun2_v, SimdShift, (0b0000000000000000000000, 0b0110111100000000100011, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 10), // #663
2211INST(Sqshl_v, SimdShift, (0b0000111000100000010011, 0b0000111100000000011101, 0, kVO_SV_Any), RWI_W, 0, 11), // #664
2212INST(Sqshlu_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000011001, 0, kVO_SV_Any), RWI_W, 0, 12), // #665
2213INST(Sqshrn_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000100101, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 13), // #666
2214INST(Sqshrn2_v, SimdShift, (0b0000000000000000000000, 0b0100111100000000100101, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 14), // #667
2215INST(Sqshrun_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000100001, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 15), // #668
2216INST(Sqshrun2_v, SimdShift, (0b0000000000000000000000, 0b0110111100000000100001, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 16), // #669
2217INST(Sqsub_v, ISimdVVV, (0b0000111000100000001011, kVO_SV_Any), RWI_W, 0, 33), // #670
2218INST(Sqxtn_v, ISimdVV, (0b0000111000100001010010, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 15), // #671
2219INST(Sqxtn2_v, ISimdVV, (0b0100111000100001010010, kVO_V_B16H8S4), RWI_X, F!(Narrow), 16), // #672
2220INST(Sqxtun_v, ISimdVV, (0b0010111000100001001010, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 17), // #673
2221INST(Sqxtun2_v, ISimdVV, (0b0110111000100001001010, kVO_V_B16H8S4), RWI_X, F!(Narrow), 18), // #674
2222INST(Srhadd_v, ISimdVVV, (0b0000111000100000000101, kVO_V_BHS), RWI_W, 0, 34), // #675
2223INST(Sri_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000010001, 1, kVO_V_Any), RWI_W, 0, 17), // #676
2224INST(Srshl_v, SimdShift, (0b0000111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any), RWI_W, 0, 18), // #677
2225INST(Srshr_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000001001, 1, kVO_V_Any), RWI_W, 0, 19), // #678
2226INST(Srsra_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000001101, 1, kVO_V_Any), RWI_X, 0, 20), // #679
2227INST(Sshl_v, SimdShift, (0b0000111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any), RWI_W, 0, 21), // #680
2228INST(Sshll_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000101001, 0, kVO_V_B8H4S2), RWI_W, F!(Long), 22), // #681
2229INST(Sshll2_v, SimdShift, (0b0000000000000000000000, 0b0100111100000000101001, 0, kVO_V_B16H8S4), RWI_W, F!(Long), 23), // #682
2230INST(Sshr_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000000001, 1, kVO_V_Any), RWI_W, 0, 24), // #683
2231INST(Ssra_v, SimdShift, (0b0000000000000000000000, 0b0000111100000000000101, 1, kVO_V_Any), RWI_X, 0, 25), // #684
2232INST(Ssubl_v, ISimdVVV, (0b0000111000100000001000, kVO_V_B8H4S2), RWI_W, F!(Long), 35), // #685
2233INST(Ssubl2_v, ISimdVVV, (0b0100111000100000001000, kVO_V_B16H8S4), RWI_W, F!(Long), 36), // #686
2234INST(Ssubw_v, ISimdWWV, (0b0000111000100000001100, kVO_V_B8H4S2), RWI_W, 0, 2), // #687
2235INST(Ssubw2_v, ISimdWWV, (0b0000111000100000001100, kVO_V_B16H8S4), RWI_X, 0, 3), // #688
2236INST(St1_v, SimdLdNStN, (0b0000110100000000000000, 0b0000110000000000001000, 1, 0), RWI_STN, F!(Consecutive), 8), // #689
2237INST(St2_v, SimdLdNStN, (0b0000110100100000000000, 0b0000110000000000100000, 2, 0), RWI_STN, F!(Consecutive), 9), // #690
2238INST(St3_v, SimdLdNStN, (0b0000110100000000001000, 0b0000110000000000010000, 3, 0), RWI_STN, F!(Consecutive), 10), // #691
2239INST(St4_v, SimdLdNStN, (0b0000110100100000001000, 0b0000110000000000000000, 4, 0), RWI_STN, F!(Consecutive), 11), // #692
2240INST(Stnp_v, SimdLdpStp, (0b0010110000, 0b0000000000), RWI_RRW, 0, 2), // #693
2241INST(Stp_v, SimdLdpStp, (0b0010110100, 0b0010110010), RWI_RRW, 0, 3), // #694
2242INST(Str_v, SimdLdSt, (0b0011110100, 0b00111100000, 0b00111100001, 0b00000000, InstId::Stur_v), RWI_RW, 0, 1), // #695
2243INST(Stur_v, SimdLdurStur, (0b0011110000000000000000), RWI_RW, 0, 1), // #696
2244INST(Sub_v, ISimdVVV, (0b0010111000100000100001, kVO_V_Any), RWI_W, 0, 37), // #697
2245INST(Subhn_v, ISimdVVV, (0b0000111000100000011000, kVO_V_B8H4S2), RWI_W, F!(Narrow), 38), // #698
2246INST(Subhn2_v, ISimdVVV, (0b0000111000100000011000, kVO_V_B16H8S4), RWI_X, F!(Narrow), 39), // #699
2247INST(Sudot_v, SimdDot, (0b0000000000000000000000, 0b0000111100000000111100, kET_S, kET_B, kET_4B), RWI_X, 0, 2), // #700
2248INST(Suqadd_v, ISimdVV, (0b0000111000100000001110, kVO_SV_Any), RWI_X, 0, 19), // #701
2249INST(Sxtl_v, SimdSxtlUxtl, (0b0000111100000000101001, kVO_V_B8H4S2), RWI_W, F!(Long), 0), // #702
2250INST(Sxtl2_v, SimdSxtlUxtl, (0b0100111100000000101001, kVO_V_B16H8S4), RWI_W, F!(Long), 1), // #703
2251INST(Tbl_v, SimdTblTbx, (0b0000111000000000000000), RWI_W, 0, 0), // #704
2252INST(Tbx_v, SimdTblTbx, (0b0000111000000000000100), RWI_W, 0, 1), // #705
2253INST(Trn1_v, ISimdVVV, (0b0000111000000000001010, kVO_V_BHS_D2), RWI_W, 0, 40), // #706
2254INST(Trn2_v, ISimdVVV, (0b0000111000000000011010, kVO_V_BHS_D2), RWI_W, 0, 41), // #707
2255INST(Uaba_v, ISimdVVV, (0b0010111000100000011111, kVO_V_BHS), RWI_X, 0, 42), // #708
2256INST(Uabal_v, ISimdVVV, (0b0010111000100000010100, kVO_V_B8H4S2), RWI_X, F!(Long), 43), // #709
2257INST(Uabal2_v, ISimdVVV, (0b0110111000100000010100, kVO_V_B16H8S4), RWI_X, F!(Long), 44), // #710
2258INST(Uabd_v, ISimdVVV, (0b0010111000100000011101, kVO_V_BHS), RWI_W, 0, 45), // #711
2259INST(Uabdl_v, ISimdVVV, (0b0010111000100000011100, kVO_V_B8H4S2), RWI_W, F!(Long), 46), // #712
2260INST(Uabdl2_v, ISimdVVV, (0b0110111000100000011100, kVO_V_B16H8S4), RWI_W, F!(Long), 47), // #713
2261INST(Uadalp_v, ISimdVV, (0b0010111000100000011010, kVO_V_BHS), RWI_X, F!(Long) | F!(Pair), 20), // #714
2262INST(Uaddl_v, ISimdVVV, (0b0010111000100000000000, kVO_V_B8H4S2), RWI_W, F!(Long), 48), // #715
2263INST(Uaddl2_v, ISimdVVV, (0b0110111000100000000000, kVO_V_B16H8S4), RWI_W, F!(Long), 49), // #716
2264INST(Uaddlp_v, ISimdVV, (0b0010111000100000001010, kVO_V_BHS), RWI_W, F!(Long) | F!(Pair), 21), // #717
2265INST(Uaddlv_v, ISimdSV, (0b0010111000110000001110, kVO_V_BH_4S), RWI_W, F!(Long), 4), // #718
2266INST(Uaddw_v, ISimdWWV, (0b0010111000100000000100, kVO_V_B8H4S2), RWI_W, 0, 4), // #719
2267INST(Uaddw2_v, ISimdWWV, (0b0010111000100000000100, kVO_V_B16H8S4), RWI_W, 0, 5), // #720
2268INST(Ucvtf_v, SimdFcvtSV, (0b0010111000100001110110, 0b0010111100000000111001, 0b0001111000100011000000, 0), RWI_W, 0, 11), // #721
2269INST(Udot_v, SimdDot, (0b0010111010000000100101, 0b0010111110000000111000, kET_S, kET_B, kET_4B), RWI_X, 0, 3), // #722
2270INST(Uhadd_v, ISimdVVV, (0b0010111000100000000001, kVO_V_BHS), RWI_W, 0, 50), // #723
2271INST(Uhsub_v, ISimdVVV, (0b0010111000100000001001, kVO_V_BHS), RWI_W, 0, 51), // #724
2272INST(Umax_v, ISimdVVV, (0b0010111000100000011001, kVO_V_BHS), RWI_W, 0, 52), // #725
2273INST(Umaxp_v, ISimdVVV, (0b0010111000100000101001, kVO_V_BHS), RWI_W, 0, 53), // #726
2274INST(Umaxv_v, ISimdSV, (0b0010111000110000101010, kVO_V_BH_4S), RWI_W, 0, 5), // #727
2275INST(Umin_v, ISimdVVV, (0b0010111000100000011011, kVO_V_BHS), RWI_W, 0, 54), // #728
2276INST(Uminp_v, ISimdVVV, (0b0010111000100000101011, kVO_V_BHS), RWI_W, 0, 55), // #729
2277INST(Uminv_v, ISimdSV, (0b0010111000110001101010, kVO_V_BH_4S), RWI_W, 0, 6), // #730
2278INST(Umlal_v, ISimdVVVe, (0b0010111000100000100000, kVO_V_B8H4S2, 0b0010111100000000001000, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 19), // #731
2279INST(Umlal2_v, ISimdVVVe, (0b0110111000100000100000, kVO_V_B16H8S4, 0b0010111100000000001000, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 20), // #732
2280INST(Umlsl_v, ISimdVVVe, (0b0010111000100000101000, kVO_V_B8H4S2, 0b0010111100000000011000, kVO_V_H4S2), RWI_X, F!(Long) | F!(VH0_15), 21), // #733
2281INST(Umlsl2_v, ISimdVVVe, (0b0110111000100000101000, kVO_V_B16H8S4, 0b0110111100000000011000, kVO_V_H8S4), RWI_X, F!(Long) | F!(VH0_15), 22), // #734
2282INST(Ummla_v, ISimdVVVx, (0b0110111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B), RWI_X, 0, 15), // #735
2283INST(Umov_v, SimdSmovUmov, (0b0000111000000000001111, kVO_V_Any, 0), RWI_W, 0, 1), // #736
2284INST(Umull_v, ISimdVVVe, (0b0010111000100000110000, kVO_V_B8H4S2, 0b0010111100000000101000, kVO_V_H4S2), RWI_W, F!(Long) | F!(VH0_15), 23), // #737
2285INST(Umull2_v, ISimdVVVe, (0b0110111000100000110000, kVO_V_B16H8S4, 0b0110111100000000101000, kVO_V_H8S4), RWI_W, F!(Long) | F!(VH0_15), 24), // #738
2286INST(Uqadd_v, ISimdVVV, (0b0010111000100000000011, kVO_SV_Any), RWI_W, 0, 56), // #739
2287INST(Uqrshl_v, SimdShift, (0b0010111000100000010111, 0b0000000000000000000000, 0, kVO_SV_Any), RWI_W, 0, 26), // #740
2288INST(Uqrshrn_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000100111, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 27), // #741
2289INST(Uqrshrn2_v, SimdShift, (0b0000000000000000000000, 0b0110111100000000100111, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 28), // #742
2290INST(Uqshl_v, SimdShift, (0b0010111000100000010011, 0b0010111100000000011101, 0, kVO_SV_Any), RWI_W, 0, 29), // #743
2291INST(Uqshrn_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000100101, 1, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 30), // #744
2292INST(Uqshrn2_v, SimdShift, (0b0000000000000000000000, 0b0110111100000000100101, 1, kVO_V_B16H8S4), RWI_X, F!(Narrow), 31), // #745
2293INST(Uqsub_v, ISimdVVV, (0b0010111000100000001011, kVO_SV_Any), RWI_W, 0, 57), // #746
2294INST(Uqxtn_v, ISimdVV, (0b0010111000100001010010, kVO_SV_B8H4S2), RWI_W, F!(Narrow), 22), // #747
2295INST(Uqxtn2_v, ISimdVV, (0b0110111000100001010010, kVO_V_B16H8S4), RWI_X, F!(Narrow), 23), // #748
2296INST(Urecpe_v, ISimdVV, (0b0000111010100001110010, kVO_V_S), RWI_W, 0, 24), // #749
2297INST(Urhadd_v, ISimdVVV, (0b0010111000100000000101, kVO_V_BHS), RWI_W, 0, 58), // #750
2298INST(Urshl_v, SimdShift, (0b0010111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any), RWI_W, 0, 32), // #751
2299INST(Urshr_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000001001, 1, kVO_V_Any), RWI_W, 0, 33), // #752
2300INST(Ursqrte_v, ISimdVV, (0b0010111010100001110010, kVO_V_S), RWI_W, 0, 25), // #753
2301INST(Ursra_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000001101, 1, kVO_V_Any), RWI_X, 0, 34), // #754
2302INST(Usdot_v, SimdDot, (0b0000111010000000100111, 0b0000111110000000111100, kET_S, kET_B, kET_4B), RWI_X, 0, 4), // #755
2303INST(Ushl_v, SimdShift, (0b0010111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any), RWI_W, 0, 35), // #756
2304INST(Ushll_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000101001, 0, kVO_V_B8H4S2), RWI_W, F!(Long), 36), // #757
2305INST(Ushll2_v, SimdShift, (0b0000000000000000000000, 0b0110111100000000101001, 0, kVO_V_B16H8S4), RWI_W, F!(Long), 37), // #758
2306INST(Ushr_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000000001, 1, kVO_V_Any), RWI_W, 0, 38), // #759
2307INST(Usmmla_v, ISimdVVVx, (0b0100111010000000101011, kOp_V4S, kOp_V16B, kOp_V16B), RWI_X, 0, 16), // #760
2308INST(Usqadd_v, ISimdVV, (0b0010111000100000001110, kVO_SV_Any), RWI_X, 0, 26), // #761
2309INST(Usra_v, SimdShift, (0b0000000000000000000000, 0b0010111100000000000101, 1, kVO_V_Any), RWI_X, 0, 39), // #762
2310INST(Usubl_v, ISimdVVV, (0b0010111000100000001000, kVO_V_B8H4S2), RWI_W, F!(Long), 59), // #763
2311INST(Usubl2_v, ISimdVVV, (0b0110111000100000001000, kVO_V_B16H8S4), RWI_W, F!(Long), 60), // #764
2312INST(Usubw_v, ISimdWWV, (0b0010111000100000001100, kVO_V_B8H4S2), RWI_W, 0, 6), // #765
2313INST(Usubw2_v, ISimdWWV, (0b0010111000100000001100, kVO_V_B16H8S4), RWI_W, 0, 7), // #766
2314INST(Uxtl_v, SimdSxtlUxtl, (0b0010111100000000101001, kVO_V_B8H4S2), RWI_W, F!(Long), 2), // #767
2315INST(Uxtl2_v, SimdSxtlUxtl, (0b0110111100000000101001, kVO_V_B16H8S4), RWI_W, F!(Long), 3), // #768
2316INST(Uzp1_v, ISimdVVV, (0b0000111000000000000110, kVO_V_BHS_D2), RWI_W, 0, 61), // #769
2317INST(Uzp2_v, ISimdVVV, (0b0000111000000000010110, kVO_V_BHS_D2), RWI_W, 0, 62), // #770
2318INST(Xar_v, ISimdVVVI, (0b1100111001100000100011, kVO_V_D2, 6, 10, 0), RWI_W, 0, 1), // #771
2319INST(Xtn_v, ISimdVV, (0b0000111000100001001010, kVO_V_B8H4S2), RWI_W, F!(Narrow), 27), // #772
2320INST(Xtn2_v, ISimdVV, (0b0100111000100001001010, kVO_V_B16H8S4), RWI_X, F!(Narrow), 28), // #773
2321INST(Zip1_v, ISimdVVV, (0b0000111000000000001110, kVO_V_BHS_D2), RWI_W, 0, 63), // #774
2322INST(Zip2_v, ISimdVVV, (0b0000111000000000011110, kVO_V_BHS_D2), RWI_W, 0, 64), // #775
2323
2324  });
2325
2326pub const BASE_ADD_SUB: [BaseAddSub; 4] = [
2327    BaseAddSub::new(0b0001011000, 0b0001011001, 0b0010001), // add
2328    BaseAddSub::new(0b0101011000, 0b0101011001, 0b0110001), // adds
2329    BaseAddSub::new(0b1001011000, 0b1001011001, 0b1010001), // sub
2330    BaseAddSub::new(0b1101011000, 0b1101011001, 0b1110001), // subs
2331];
2332
2333macro_rules! table_new {
2334        ($ty:ident, { $({ $($e:expr),* $(,)? }),* $(,)? }) => {
2335                [$( $ty::new($($e as u64 as _),*) ),*]
2336        };
2337}
2338
2339const kW: u32 = W;
2340const kX: u32 = X;
2341const kWX: u32 = WX;
2342const kZR: u32 = ZR;
2343const kSP: u32 = SP;
2344
2345const kHF_N: u32 = HFConv::N as u32;
2346const kHF_A: u32 = HFConv::A as u32;
2347const kHF_B: u32 = HFConv::B as u32;
2348const kHF_C: u32 = HFConv::C as u32;
2349
2350const kET_B: u8 = InstElementType::B as u8;
2351const kET_H: u8 = InstElementType::H as u8;
2352const kET_S: u8 = InstElementType::S as u8;
2353const kET_2H: u8 = InstElementType::_2H as u8;
2354const kET_4B: u8 = InstElementType::_4B as u8;
2355
2356const kOp_GpW: u32 = OpSignature::GpW as u32;
2357const kOp_H: u32 = OpSignature::H as u32;
2358const kOp_S: u32 = OpSignature::S as u32;
2359const kOp_D: u32 = OpSignature::D as u32;
2360const kOp_Q: u32 = OpSignature::Q as u32;
2361const kOp_V4H: u32 = OpSignature::V4H as u32;
2362const kOp_V8H: u32 = OpSignature::V8H as u32;
2363const kOp_V4S: u32 = OpSignature::V4S as u32;
2364const kOp_V2D: u32 = OpSignature::V2D as u32;
2365const kOp_V16B: u32 = OpSignature::V16B as u32;
2366
2367const kVO_V_B: u32 = VOType::VB as u32;
2368const kVO_V_BH: u32 = VOType::VBH as u32;
2369const kVO_V_BH_4S: u32 = VOType::VBH4S as u32;
2370const kVO_V_BHS: u32 = VOType::VBHS as u32;
2371const kVO_V_BHS_D2: u32 = VOType::VBHSD2 as u32;
2372const kVO_V_HS: u32 = VOType::VHS as u32;
2373const kVO_V_S: u32 = VOType::VS as u32;
2374const kVO_V_B8H4S2: u32 = VOType::VB8H4S2 as u32;
2375const kVO_V_B8D1: u32 = VOType::VB8D1 as u32;
2376const kVO_V_H4S2: u32 = VOType::VH4S2 as u32;
2377const kVO_V_B16: u32 = VOType::VB16 as u32;
2378const kVO_V_B16H8S4: u32 = VOType::VB16H8S4 as u32;
2379const kVO_V_B16D2: u32 = VOType::VB16D2 as u32;
2380const kVO_V_H8S4: u32 = VOType::VH8S4 as u32;
2381const kVO_V_D2: u32 = VOType::VD2 as u32;
2382const kVO_SV_BHS: u32 = VOType::SVBHS as u32;
2383const kVO_SV_B8H4S2: u32 = VOType::SVB8H4S2 as u32;
2384const kVO_SV_HS: u32 = VOType::SVHS as u32;
2385const kVO_V_Any: u32 = VOType::VAny as u32;
2386const kVO_SV_Any: u32 = VOType::SVAny as u32;
2387
2388pub const BASE_ADR: [BaseAdr; 2] = table_new!(BaseAdr, {
2389    { 0b0001000000000000000000, OffsetType::Adr as u8 }, // adr
2390    { 0b1001000000000000000000, OffsetType::Adrp as u8 }  // adrp
2391});
2392
2393pub const BASE_AT_DC_IC_TLBI: [BaseAtDcIcTlbi; 4] = table_new!(BaseAtDcIcTlbi, {
2394    { 0b00011111110000, 0b00001111000000, true }, // at
2395    { 0b00011110000000, 0b00001110000000, true }, // dc
2396    { 0b00011110000000, 0b00001110000000, false }, // ic
2397    { 0b00011110000000, 0b00010000000000, false }  // tlbi
2398});
2399
2400pub const BASE_ATOMIC_CASP: [BaseAtomicCasp; 4] = table_new!(BaseAtomicCasp, {
2401    { 0b0000100000100000011111, kWX, 30 }, // casp
2402    { 0b0000100001100000011111, kWX, 30 }, // caspa
2403    { 0b0000100001100000111111, kWX, 30 }, // caspal
2404    { 0b0000100000100000111111, kWX, 30 }  // caspl
2405});
2406
2407pub const BASE_ATOMIC_OP: [BaseAtomicOp; 123] = table_new!(BaseAtomicOp, {
2408    { 0b1000100010100000011111, kWX, 30, 0 }, // cas
2409    { 0b1000100011100000011111, kWX, 30, 1 }, // casa
2410    { 0b0000100011100000011111, kW, 0, 1 }, // casab
2411    { 0b0100100011100000011111, kW, 0, 1 }, // casah
2412    { 0b1000100011100000111111, kWX, 30, 1 }, // casal
2413    { 0b0000100011100000111111, kW, 0, 1 }, // casalb
2414    { 0b0100100011100000111111, kW, 0, 1 }, // casalh
2415    { 0b0000100010100000011111, kW, 0, 0 }, // casb
2416    { 0b0100100010100000011111, kW, 0, 0 }, // cash
2417    { 0b1000100010100000111111, kWX, 30, 0 }, // casl
2418    { 0b0000100010100000111111, kW, 0, 0 }, // caslb
2419    { 0b0100100010100000111111, kW, 0, 0 }, // caslh
2420    { 0b1011100000100000000000, kWX, 30, 0 }, // ldadd
2421    { 0b1011100010100000000000, kWX, 30, 1 }, // ldadda
2422    { 0b0011100010100000000000, kW, 0, 1 }, // ldaddab
2423    { 0b0111100010100000000000, kW, 0, 1 }, // ldaddah
2424    { 0b1011100011100000000000, kWX, 30, 1 }, // ldaddal
2425    { 0b0011100011100000000000, kW, 0, 1 }, // ldaddalb
2426    { 0b0111100011100000000000, kW, 0, 1 }, // ldaddalh
2427    { 0b0011100000100000000000, kW, 0, 0 }, // ldaddb
2428    { 0b0111100000100000000000, kW, 0, 0 }, // ldaddh
2429    { 0b1011100001100000000000, kWX, 30, 0 }, // ldaddl
2430    { 0b0011100001100000000000, kW, 0, 0 }, // ldaddlb
2431    { 0b0111100001100000000000, kW, 0, 0 }, // ldaddlh
2432    { 0b1011100000100000000100, kWX, 30, 0 }, // ldclr
2433    { 0b1011100010100000000100, kWX, 30, 1 }, // ldclra
2434    { 0b0011100010100000000100, kW, 0, 1 }, // ldclrab
2435    { 0b0111100010100000000100, kW, 0, 1 }, // ldclrah
2436    { 0b1011100011100000000100, kWX, 30, 1 }, // ldclral
2437    { 0b0011100011100000000100, kW, 0, 1 }, // ldclralb
2438    { 0b0111100011100000000100, kW, 0, 1 }, // ldclralh
2439    { 0b0011100000100000000100, kW, 0, 0 }, // ldclrb
2440    { 0b0111100000100000000100, kW, 0, 0 }, // ldclrh
2441    { 0b1011100001100000000100, kWX, 30, 0 }, // ldclrl
2442    { 0b0011100001100000000100, kW, 0, 0 }, // ldclrlb
2443    { 0b0111100001100000000100, kW, 0, 0 }, // ldclrlh
2444    { 0b1011100000100000001000, kWX, 30, 0 }, // ldeor
2445    { 0b1011100010100000001000, kWX, 30, 1 }, // ldeora
2446    { 0b0011100010100000001000, kW, 0, 1 }, // ldeorab
2447    { 0b0111100010100000001000, kW, 0, 1 }, // ldeorah
2448    { 0b1011100011100000001000, kWX, 30, 1 }, // ldeoral
2449    { 0b0011100011100000001000, kW, 0, 1 }, // ldeoralb
2450    { 0b0111100011100000001000, kW, 0, 1 }, // ldeoralh
2451    { 0b0011100000100000001000, kW, 0, 0 }, // ldeorb
2452    { 0b0111100000100000001000, kW, 0, 0 }, // ldeorh
2453    { 0b1011100001100000001000, kWX, 30, 0 }, // ldeorl
2454    { 0b0011100001100000001000, kW, 0, 0 }, // ldeorlb
2455    { 0b0111100001100000001000, kW, 0, 0 }, // ldeorlh
2456    { 0b1011100000100000001100, kWX, 30, 0 }, // ldset
2457    { 0b1011100010100000001100, kWX, 30, 1 }, // ldseta
2458    { 0b0011100010100000001100, kW, 0, 1 }, // ldsetab
2459    { 0b0111100010100000001100, kW, 0, 1 }, // ldsetah
2460    { 0b1011100011100000001100, kWX, 30, 1 }, // ldsetal
2461    { 0b0011100011100000001100, kW, 0, 1 }, // ldsetalb
2462    { 0b0111100011100000001100, kW, 0, 1 }, // ldsetalh
2463    { 0b0011100000100000001100, kW, 0, 0 }, // ldsetb
2464    { 0b0111100000100000001100, kW, 0, 0 }, // ldseth
2465    { 0b1011100001100000001100, kWX, 30, 0 }, // ldsetl
2466    { 0b0011100001100000001100, kW, 0, 0 }, // ldsetlb
2467    { 0b0111100001100000001100, kW, 0, 0 }, // ldsetlh
2468    { 0b1011100000100000010000, kWX, 30, 0 }, // ldsmax
2469    { 0b1011100010100000010000, kWX, 30, 1 }, // ldsmaxa
2470    { 0b0011100010100000010000, kW, 0, 1 }, // ldsmaxab
2471    { 0b0111100010100000010000, kW, 0, 1 }, // ldsmaxah
2472    { 0b1011100011100000010000, kWX, 30, 1 }, // ldsmaxal
2473    { 0b0011100011100000010000, kW, 0, 1 }, // ldsmaxalb
2474    { 0b0111100011100000010000, kW, 0, 1 }, // ldsmaxalh
2475    { 0b0011100000100000010000, kW, 0, 0 }, // ldsmaxb
2476    { 0b0111100000100000010000, kW, 0, 0 }, // ldsmaxh
2477    { 0b1011100001100000010000, kWX, 30, 0 }, // ldsmaxl
2478    { 0b0011100001100000010000, kW, 0, 0 }, // ldsmaxlb
2479    { 0b0111100001100000010000, kW, 0, 0 }, // ldsmaxlh
2480    { 0b1011100000100000010100, kWX, 30, 0 }, // ldsmin
2481    { 0b1011100010100000010100, kWX, 30, 1 }, // ldsmina
2482    { 0b0011100010100000010100, kW, 0, 1 }, // ldsminab
2483    { 0b0111100010100000010100, kW, 0, 1 }, // ldsminah
2484    { 0b1011100011100000010100, kWX, 30, 1 }, // ldsminal
2485    { 0b0011100011100000010100, kW, 0, 1 }, // ldsminalb
2486    { 0b0111100011100000010100, kW, 0, 1 }, // ldsminalh
2487    { 0b0011100000100000010100, kW, 0, 0 }, // ldsminb
2488    { 0b0111100000100000010100, kW, 0, 0 }, // ldsminh
2489    { 0b1011100001100000010100, kWX, 30, 0 }, // ldsminl
2490    { 0b0011100001100000010100, kW, 0, 0 }, // ldsminlb
2491    { 0b0111100001100000010100, kW, 0, 0 }, // ldsminlh
2492    { 0b1011100000100000011000, kWX, 30, 0 }, // ldumax
2493    { 0b1011100010100000011000, kWX, 30, 1 }, // ldumaxa
2494    { 0b0011100010100000011000, kW, 0, 1 }, // ldumaxab
2495    { 0b0111100010100000011000, kW, 0, 1 }, // ldumaxah
2496    { 0b1011100011100000011000, kWX, 30, 1 }, // ldumaxal
2497    { 0b0011100011100000011000, kW, 0, 1 }, // ldumaxalb
2498    { 0b0111100011100000011000, kW, 0, 1 }, // ldumaxalh
2499    { 0b0011100000100000011000, kW, 0, 0 }, // ldumaxb
2500    { 0b0111100000100000011000, kW, 0, 0 }, // ldumaxh
2501    { 0b1011100001100000011000, kWX, 30, 0 }, // ldumaxl
2502    { 0b0011100001100000011000, kW, 0, 0 }, // ldumaxlb
2503    { 0b0111100001100000011000, kW, 0, 0 }, // ldumaxlh
2504    { 0b1011100000100000011100, kWX, 30, 0 }, // ldumin
2505    { 0b1011100010100000011100, kWX, 30, 1 }, // ldumina
2506    { 0b0011100010100000011100, kW, 0, 1 }, // lduminab
2507    { 0b0111100010100000011100, kW, 0, 1 }, // lduminah
2508    { 0b1011100011100000011100, kWX, 30, 1 }, // lduminal
2509    { 0b0011100011100000011100, kW, 0, 1 }, // lduminalb
2510    { 0b0111100011100000011100, kW, 0, 1 }, // lduminalh
2511    { 0b0011100000100000011100, kW, 0, 0 }, // lduminb
2512    { 0b0111100000100000011100, kW, 0, 0 }, // lduminh
2513    { 0b1011100001100000011100, kWX, 30, 0 }, // lduminl
2514    { 0b0011100001100000011100, kW, 0, 0 }, // lduminlb
2515    { 0b0111100001100000011100, kW, 0, 0 }, // lduminlh
2516    { 0b1000100000000000111111, kWX, 30, 1 }, // stlxr
2517    { 0b0000100000000000111111, kW, 0, 1 }, // stlxrb
2518    { 0b0100100000000000111111, kW, 0, 1 }, // stlxrh
2519    { 0b1011100000100000100000, kWX, 30, 1 }, // swp
2520    { 0b1011100010100000100000, kWX, 30, 1 }, // swpa
2521    { 0b0011100010100000100000, kW, 0, 1 }, // swpab
2522    { 0b0111100010100000100000, kW, 0, 1 }, // swpah
2523    { 0b1011100011100000100000, kWX, 30, 1 }, // swpal
2524    { 0b0011100011100000100000, kW, 0, 1 }, // swpalb
2525    { 0b0111100011100000100000, kW, 0, 1 }, // swpalh
2526    { 0b0011100000100000100000, kW, 0, 1 }, // swpb
2527    { 0b0111100000100000100000, kW, 0, 1 }, // swph
2528    { 0b1011100001100000100000, kWX, 30, 1 }, // swpl
2529    { 0b0011100001100000100000, kW, 0, 1 }, // swplb
2530    { 0b0111100001100000100000, kW, 0, 1 }  // swplh
2531});
2532
2533pub const BASE_ATOMIC_ST: [BaseAtomicSt; 48] = table_new!(BaseAtomicSt, {
2534    { 0b1011100000100000000000, kWX, 30 }, // stadd
2535    { 0b1011100001100000000000, kWX, 30 }, // staddl
2536    { 0b0011100000100000000000, kW, 0 }, // staddb
2537    { 0b0011100001100000000000, kW, 0 }, // staddlb
2538    { 0b0111100000100000000000, kW, 0 }, // staddh
2539    { 0b0111100001100000000000, kW, 0 }, // staddlh
2540    { 0b1011100000100000000100, kWX, 30 }, // stclr
2541    { 0b1011100001100000000100, kWX, 30 }, // stclrl
2542    { 0b0011100000100000000100, kW, 0 }, // stclrb
2543    { 0b0011100001100000000100, kW, 0 }, // stclrlb
2544    { 0b0111100000100000000100, kW, 0 }, // stclrh
2545    { 0b0111100001100000000100, kW, 0 }, // stclrlh
2546    { 0b1011100000100000001000, kWX, 30 }, // steor
2547    { 0b1011100001100000001000, kWX, 30 }, // steorl
2548    { 0b0011100000100000001000, kW, 0 }, // steorb
2549    { 0b0011100001100000001000, kW, 0 }, // steorlb
2550    { 0b0111100000100000001000, kW, 0 }, // steorh
2551    { 0b0111100001100000001000, kW, 0 }, // steorlh
2552    { 0b1011100000100000001100, kWX, 30 }, // stset
2553    { 0b1011100001100000001100, kWX, 30 }, // stsetl
2554    { 0b0011100000100000001100, kW, 0 }, // stsetb
2555    { 0b0011100001100000001100, kW, 0 }, // stsetlb
2556    { 0b0111100000100000001100, kW, 0 }, // stseth
2557    { 0b0111100001100000001100, kW, 0 }, // stsetlh
2558    { 0b1011100000100000010000, kWX, 30 }, // stsmax
2559    { 0b1011100001100000010000, kWX, 30 }, // stsmaxl
2560    { 0b0011100000100000010000, kW, 0 }, // stsmaxb
2561    { 0b0011100001100000010000, kW, 0 }, // stsmaxlb
2562    { 0b0111100000100000010000, kW, 0 }, // stsmaxh
2563    { 0b0111100001100000010000, kW, 0 }, // stsmaxlh
2564    { 0b1011100000100000010100, kWX, 30 }, // stsmin
2565    { 0b1011100001100000010100, kWX, 30 }, // stsminl
2566    { 0b0011100000100000010100, kW, 0 }, // stsminb
2567    { 0b0011100001100000010100, kW, 0 }, // stsminlb
2568    { 0b0111100000100000010100, kW, 0 }, // stsminh
2569    { 0b0111100001100000010100, kW, 0 }, // stsminlh
2570    { 0b1011100000100000011000, kWX, 30 }, // stumax
2571    { 0b1011100001100000011000, kWX, 30 }, // stumaxl
2572    { 0b0011100000100000011000, kW, 0 }, // stumaxb
2573    { 0b0011100001100000011000, kW, 0 }, // stumaxlb
2574    { 0b0111100000100000011000, kW, 0 }, // stumaxh
2575    { 0b0111100001100000011000, kW, 0 }, // stumaxlh
2576    { 0b1011100000100000011100, kWX, 30 }, // stumin
2577    { 0b1011100001100000011100, kWX, 30 }, // stuminl
2578    { 0b0011100000100000011100, kW, 0 }, // stuminb
2579    { 0b0011100001100000011100, kW, 0 }, // stuminlb
2580    { 0b0111100000100000011100, kW, 0 }, // stuminh
2581    { 0b0111100001100000011100, kW, 0 }  // stuminlh
2582});
2583
2584pub const BASE_BFC: [BaseBfc; 1] = table_new!(BaseBfc, {
2585    { 0b00110011000000000000001111100000 } // bfc
2586});
2587
2588pub const BASE_BFI: [BaseBfi; 3] = table_new!(BaseBfi, {
2589    { 0b00110011000000000000000000000000 }, // bfi
2590    { 0b00010011000000000000000000000000 }, // sbfiz
2591    { 0b01010011000000000000000000000000 }  // ubfiz
2592});
2593
2594pub const BASE_BFM: [BaseBfm; 3] = table_new!(BaseBfm, {
2595    { 0b00110011000000000000000000000000 }, // bfm
2596    { 0b00010011000000000000000000000000 }, // sbfm
2597    { 0b01010011000000000000000000000000 }  // ubfm
2598});
2599
2600pub const BASE_BFX: [BaseBfx; 3] = table_new!(BaseBfx, {
2601    { 0b00110011000000000000000000000000 }, // bfxil
2602    { 0b00010011000000000000000000000000 }, // sbfx
2603    { 0b01010011000000000000000000000000 }  // ubfx
2604});
2605
2606pub const BASE_BRANCH_CMP: [BaseBranchCmp; 2] = table_new!(BaseBranchCmp, {
2607    { 0b00110101000000000000000000000000 }, // cbnz
2608    { 0b00110100000000000000000000000000 }  // cbz
2609});
2610
2611pub const BASE_BRANCH_REG: [BaseBranchReg; 3] = table_new!(BaseBranchReg, {
2612    { 0b11010110001111110000000000000000u32 as i32 }, // blr
2613    { 0b11010110000111110000000000000000u32 as i32 }, // br
2614    { 0b11010110010111110000000000000000u32 as i32 }  // ret
2615});
2616
2617pub const BASE_BRANCH_REL: [BaseBranchRel; 3] = table_new!(BaseBranchRel, {
2618    { 0b00010100000000000000000000000000 }, // b
2619    { 0b00010100000000000000000000010000 }, // bc
2620    { 0b10010100000000000000000000000000u32 as i32 }  // bl
2621});
2622
2623pub const BASE_BRANCH_TST: [BaseBranchTst; 2] = table_new!(BaseBranchTst, {
2624    { 0b00110111000000000000000000000000 }, // tbnz
2625    { 0b00110110000000000000000000000000 }  // tbz
2626});
2627
2628pub const BASE_C_CMP: [BaseCCmp; 2] = table_new!(BaseCCmp, {
2629    { 0b00111010010000000000000000000000 }, // ccmn
2630    { 0b01111010010000000000000000000000 }  // ccmp
2631});
2632
2633pub const BASE_C_INC: [BaseCInc; 3] = table_new!(BaseCInc, {
2634    { 0b00011010100000000000010000000000 }, // cinc
2635    { 0b01011010100000000000000000000000 }, // cinv
2636    { 0b01011010100000000000010000000000 }  // cneg
2637});
2638
2639pub const BASE_C_SEL: [BaseCSel; 4] = table_new!(BaseCSel, {
2640    { 0b00011010100000000000000000000000 }, // csel
2641    { 0b00011010100000000000010000000000 }, // csinc
2642    { 0b01011010100000000000000000000000 }, // csinv
2643    { 0b01011010100000000000010000000000 }  // csneg
2644});
2645
2646pub const BASE_C_SET: [BaseCSet; 2] = table_new!(BaseCSet, {
2647    { 0b00011010100111110000011111100000 }, // cset
2648    { 0b01011010100111110000001111100000 }  // csetm
2649});
2650
2651pub const BASE_CMP_CMN: [BaseCmpCmn; 2] = table_new!(BaseCmpCmn, {
2652    { 0b0101011000, 0b0101011001, 0b0110001 }, // cmn
2653    { 0b1101011000, 0b1101011001, 0b1110001 }  // cmp
2654});
2655
2656pub const BASE_EXTEND: [BaseExtend; 5] = table_new!(BaseExtend, {
2657    { 0b0001001100000000000111, kWX, 0 }, // sxtb
2658    { 0b0001001100000000001111, kWX, 0 }, // sxth
2659    { 0b1001001101000000011111, kX, 0 }, // sxtw
2660    { 0b0101001100000000000111, kW, 1 }, // uxtb
2661    { 0b0101001100000000001111, kW, 1 }  // uxth
2662});
2663
2664pub const BASE_EXTRACT: [BaseExtract; 1] = table_new!(BaseExtract, {
2665    { 0b00010011100000000000000000000000 } // extr
2666});
2667
2668pub const BASE_LD_ST: [BaseLdSt; 9] = table_new!(BaseLdSt, {
2669    { 0b1011100101, 0b10111000010, 0b10111000011, 0b00011000, kWX, 30, 2, InstId::Ldur }, // ldr
2670    { 0b0011100101, 0b00111000010, 0b00111000011, 0, kW, 0, 0, InstId::Ldurb }, // ldrb
2671    { 0b0111100101, 0b01111000010, 0b01111000011, 0, kW, 0, 1, InstId::Ldurh }, // ldrh
2672    { 0b0011100111, 0b00111000100, 0b00111000111, 0, kWX, 22, 0, InstId::Ldursb }, // ldrsb
2673    { 0b0111100111, 0b01111000100, 0b01111000111, 0, kWX, 22, 1, InstId::Ldursh }, // ldrsh
2674    { 0b1011100110, 0b10111000100, 0b10111000101, 0b10011000, kX, 0, 2, InstId::Ldursw }, // ldrsw
2675    { 0b1011100100, 0b10111000000, 0b10111000001, 0, kWX, 30, 2, InstId::Stur }, // str
2676    { 0b0011100100, 0b00111000000, 0b00111000001, 0, kW, 30, 0, InstId::Sturb }, // strb
2677    { 0b0111100100, 0b01111000000, 0b01111000001, 0, kWX, 30, 1, InstId::Sturh }  // strh
2678});
2679
2680pub const BASE_LDP_STP: [BaseLdpStp; 6] = table_new!(BaseLdpStp, {
2681    { 0b0010100001, 0, kWX, 31, 2 }, // ldnp
2682    { 0b0010100101, 0b0010100011, kWX, 31, 2 }, // ldp
2683    { 0b0110100101, 0b0110100011, kX, 0, 2 }, // ldpsw
2684    { 0b0110100100, 0b0110100010, kX, 0, 4 }, // stgp
2685    { 0b0010100000, 0, kWX, 31, 2 }, // stnp
2686    { 0b0010100100, 0b0010100010, kWX, 31, 2 }  // stp
2687});
2688
2689pub const BASE_LDXP: [BaseLdxp; 2] = table_new!(BaseLdxp, {
2690    { 0b1000100001111111100000, kWX, 30 }, // ldaxp
2691    { 0b1000100001111111000000, kWX, 30 }  // ldxp
2692});
2693
2694pub const BASE_LOGICAL: [BaseLogical; 8] = table_new!(BaseLogical, {
2695    { 0b0001010000, 0b00100100, 0 }, // and
2696    { 0b1101010000, 0b11100100, 0 }, // ands
2697    { 0b0001010001, 0b00100100, 1 }, // bic
2698    { 0b1101010001, 0b11100100, 1 }, // bics
2699    { 0b1001010001, 0b10100100, 1 }, // eon
2700    { 0b1001010000, 0b10100100, 0 }, // eor
2701    { 0b0101010001, 0b01100100, 1 }, // orn
2702    { 0b0101010000, 0b01100100, 0 }  // orr
2703});
2704
2705pub const BASE_MIN_MAX: [BaseMinMax; 4] = table_new!(BaseMinMax, {
2706    { 0b00011010110000000110000000000000, 0b00010001110000000000000000000000 }, // smax
2707    { 0b00011010110000000110100000000000, 0b00010001110010000000000000000000 }, // smin
2708    { 0b00011010110000000110010000000000, 0b00010001110001000000000000000000 }, // umax
2709    { 0b00011010110000000110110000000000, 0b00010001110011000000000000000000 }  // umin
2710});
2711
2712pub const BASE_MOV_KNZ: [BaseMovKNZ; 3] = table_new!(BaseMovKNZ, {
2713    { 0b01110010100000000000000000000000 }, // movk
2714    { 0b00010010100000000000000000000000 }, // movn
2715    { 0b01010010100000000000000000000000 }  // movz
2716});
2717
2718pub const BASE_MVN_NEG: [BaseMvnNeg; 3] = table_new!(BaseMvnNeg, {
2719    { 0b00101010001000000000001111100000 }, // mvn
2720    { 0b01001011000000000000001111100000 }, // neg
2721    { 0b01101011000000000000001111100000 }  // negs
2722});
2723
2724pub const BASE_OP: [BaseOp; 24] = table_new!(BaseOp, {
2725    { 0b11010101000000110010000110011111 }, // autia1716
2726    { 0b11010101000000110010001110111111 }, // autiasp
2727    { 0b11010101000000110010001110011111 }, // autiaz
2728    { 0b11010101000000110010000111011111 }, // autib1716
2729    { 0b11010101000000110010001111111111 }, // autibsp
2730    { 0b11010101000000110010001111011111 }, // autibz
2731    { 0b11010101000000000100000001011111 }, // axflag
2732    { 0b11010101000000000100000000011111 }, // cfinv
2733    { 0b11010101000000110010001011011111 }, // clrbhb
2734    { 0b11010101000000110010001010011111 }, // csdb
2735    { 0b11010101000000110010000011011111 }, // dgh
2736    { 0b11010110101111110000001111100000 }, // drps
2737    { 0b11010101000000110010001000011111 }, // esb
2738    { 0b11010110100111110000001111100000 }, // eret
2739    { 0b11010101000000110010000000011111 }, // nop
2740    { 0b11010101000000110011010010011111 }, // pssbb
2741    { 0b11010101000000110010000010011111 }, // sev
2742    { 0b11010101000000110010000010111111 }, // sevl
2743    { 0b11010101000000110011000010011111 }, // ssbb
2744    { 0b11010101000000110010000001011111 }, // wfe
2745    { 0b11010101000000110010000001111111 }, // wfi
2746    { 0b11010101000000000100000000111111 }, // xaflag
2747    { 0b11010101000000110010000011111111 }, // xpaclri
2748    { 0b11010101000000110010000000111111 }  // yield
2749});
2750
2751pub const BASE_OP_IMM: [BaseOpImm; 15] = table_new!(BaseOpImm, {
2752    { 0b11010100001000000000000000000000, 16, 5 }, // brk
2753    { 0b11010101000000110010010000011111, 2, 6 }, // bti
2754    { 0b11010101000000110011000001011111, 4, 8 }, // clrex
2755    { 0b11010100101000000000000000000001, 16, 5 }, // dcps1
2756    { 0b11010100101000000000000000000010, 16, 5 }, // dcps2
2757    { 0b11010100101000000000000000000011, 16, 5 }, // dcps3
2758    { 0b11010101000000110011000010111111, 4, 8 }, // dmb
2759    { 0b11010101000000110011000010011111, 4, 8 }, // dsb
2760    { 0b11010101000000110010000000011111, 7, 5 }, // hint
2761    { 0b11010100010000000000000000000000, 16, 5 }, // hlt
2762    { 0b11010100000000000000000000000010, 16, 5 }, // hvc
2763    { 0b11010101000000110011000011011111, 4, 8 }, // isb
2764    { 0b11010100000000000000000000000011, 16, 5 }, // smc
2765    { 0b11010100000000000000000000000001, 16, 5 }, // svc
2766    { 0b00000000000000000000000000000000, 16, 0 }  // udf
2767});
2768
2769pub const BASE_OP_X16: [BaseOpX16; 1] = table_new!(BaseOpX16, {
2770    { 0b11010101000000110010010100011111 } // chkfeat
2771});
2772
2773pub const BASE_PRFM: [BasePrfm; 1] = table_new!(BasePrfm, {
2774    { 0b11111000101, 0b1111100110, 0b11111000100, 0b11011000 }  // prfm
2775});
2776
2777pub const BASE_R: [BaseR; 10] = table_new!(BaseR, {
2778    { 0b11011010110000010011101111100000, kX, kZR, 0 }, // autdza
2779    { 0b11011010110000010011111111100000, kX, kZR, 0 }, // autdzb
2780    { 0b11011010110000010011001111100000, kX, kZR, 0 }, // autiza
2781    { 0b11011010110000010011011111100000, kX, kZR, 0 }, // autizb
2782    { 0b11011010110000010010101111100000, kX, kZR, 0 }, // pacdza
2783    { 0b11011010110000010010111111100000, kX, kZR, 0 }, // pacdzb
2784    { 0b00111010000000000000100000001101, kW, kZR, 5 }, // setf8
2785    { 0b00111010000000000100100000001101, kW, kZR, 5 }, // setf16
2786    { 0b11011010110000010100011111100000, kX, kZR, 0 }, // xpacd
2787    { 0b11011010110000010100001111100000, kX, kZR, 0 }  // xpaci
2788});
2789
2790pub const BASE_RM_NO_IMM: [BaseRMNoImm; 21] = table_new!(BaseRMNoImm, {
2791    { 0b1000100011011111111111, kWX, kZR, 30 }, // ldar
2792    { 0b0000100011011111111111, kW, kZR, 0 }, // ldarb
2793    { 0b0100100011011111111111, kW, kZR, 0 }, // ldarh
2794    { 0b1000100001011111111111, kWX, kZR, 30 }, // ldaxr
2795    { 0b0000100001011111111111, kW, kZR, 0 }, // ldaxrb
2796    { 0b0100100001011111111111, kW, kZR, 0 }, // ldaxrh
2797    { 0b1101100111100000000000, kX, kZR, 0 }, // ldgm
2798    { 0b1000100011011111011111, kWX, kZR, 30 }, // ldlar
2799    { 0b0000100011011111011111, kW, kZR, 0 }, // ldlarb
2800    { 0b0100100011011111011111, kW, kZR, 0 }, // ldlarh
2801    { 0b1000100001011111011111, kWX, kZR, 30 }, // ldxr
2802    { 0b0000100001011111011111, kW, kZR, 0 }, // ldxrb
2803    { 0b0100100001011111011111, kW, kZR, 0 }, // ldxrh
2804    { 0b1101100110100000000000, kX, kZR, 0 }, // stgm
2805    { 0b1000100010011111011111, kWX, kZR, 30 }, // stllr
2806    { 0b0000100010011111011111, kW, kZR, 0 }, // stllrb
2807    { 0b0100100010011111011111, kW, kZR, 0 }, // stllrh
2808    { 0b1000100010011111111111, kWX, kZR, 30 }, // stlr
2809    { 0b0000100010011111111111, kW, kZR, 0 }, // stlrb
2810    { 0b0100100010011111111111, kW, kZR, 0 }, // stlrh
2811    { 0b1101100100100000000000, kX, kZR, 0 }  // stzgm
2812});
2813
2814pub const BASE_RM_SIMM10: [BaseRMSImm10; 2] = table_new!(BaseRMSImm10, {
2815    { 0b1111100000100000000001, kX, kZR, 0, 3 }, // ldraa
2816    { 0b1111100010100000000001, kX, kZR, 0, 3 }  // ldrab
2817});
2818
2819pub const BASE_RM_SIMM9: [BaseRMSImm9; 23] = table_new!(BaseRMSImm9, {
2820    { 0b1101100101100000000000, 0b0000000000000000000000, kX, kZR, 0, 4 }, // ldg
2821    { 0b1011100001000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // ldtr
2822    { 0b0011100001000000000010, 0b0000000000000000000000, kW, kZR, 0, 0 }, // ldtrb
2823    { 0b0111100001000000000010, 0b0000000000000000000000, kW, kZR, 0, 0 }, // ldtrh
2824    { 0b0011100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldtrsb
2825    { 0b0111100011000000000010, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldtrsh
2826    { 0b1011100010000000000010, 0b0000000000000000000000, kX, kZR, 0, 0 }, // ldtrsw
2827    { 0b1011100001000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // ldur
2828    { 0b0011100001000000000000, 0b0000000000000000000000, kW, kZR, 0, 0 }, // ldurb
2829    { 0b0111100001000000000000, 0b0000000000000000000000, kW, kZR, 0, 0 }, // ldurh
2830    { 0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursb
2831    { 0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursh
2832    { 0b1011100010000000000000, 0b0000000000000000000000, kX, kZR, 0, 0 }, // ldursw
2833    { 0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4 }, // st2g
2834    { 0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4 }, // stg
2835    { 0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // sttr
2836    { 0b0011100000000000000010, 0b0000000000000000000000, kW, kZR, 0, 0 }, // sttrb
2837    { 0b0111100000000000000010, 0b0000000000000000000000, kW, kZR, 0, 0 }, // sttrh
2838    { 0b1011100000000000000000, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // stur
2839    { 0b0011100000000000000000, 0b0000000000000000000000, kW, kZR, 0, 0 }, // sturb
2840    { 0b0111100000000000000000, 0b0000000000000000000000, kW, kZR, 0, 0 }, // sturh
2841    { 0b1101100111100000000010, 0b1101100111100000000001, kX, kSP, 0, 4 }, // stz2g
2842    { 0b1101100101100000000010, 0b1101100101100000000001, kX, kSP, 0, 4 }  // stzg
2843});
2844
2845pub const BASE_RR: [BaseRR; 18] = table_new!(BaseRR, {
2846    { 0b01011010110000000010000000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // abs
2847    { 0b11011010110000010001100000000000, kX, kZR, 0, kX, kSP, 5, true }, // autda
2848    { 0b11011010110000010001110000000000, kX, kZR, 0, kX, kSP, 5, true }, // autdb
2849    { 0b11011010110000010001000000000000, kX, kZR, 0, kX, kSP, 5, true }, // autia
2850    { 0b11011010110000010001010000000000, kX, kZR, 0, kX, kSP, 5, true }, // autib
2851    { 0b01011010110000000001010000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // cls
2852    { 0b01011010110000000001000000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // clz
2853    { 0b10111010110000000000000000011111, kX, kSP, 5, kX, kSP, 16, true }, // cmpp
2854    { 0b01011010110000000001110000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // cnt
2855    { 0b01011010110000000001100000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // ctz
2856    { 0b01011010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true }, // ngc
2857    { 0b01111010000000000000001111100000, kWX, kZR, 0, kWX, kZR, 16, true }, // ngcs
2858    { 0b11011010110000010000100000000000, kX, kZR, 0, kX, kSP, 5, true }, // pacda
2859    { 0b11011010110000010000110000000000, kX, kZR, 0, kX, kSP, 5, true }, // pacdb
2860    { 0b01011010110000000000000000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rbit
2861    { 0b01011010110000000000010000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rev16
2862    { 0b11011010110000000000100000000000, kWX, kZR, 0, kWX, kZR, 5, true }, // rev32
2863    { 0b11011010110000000000110000000000, kWX, kZR, 0, kWX, kZR, 5, true }  // rev64
2864});
2865
2866pub const BASE_RRII: [BaseRRII; 2] = table_new!(BaseRRII, {
2867    { 0b1001000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10 }, // addg
2868    { 0b1101000110000000000000, kX, kSP, kX, kSP, 6, 4, 16, 4, 0, 10 }  // subg
2869});
2870
2871pub const BASE_RRR: [BaseRRR; 26] = table_new!(BaseRRR, {
2872    { 0b0001101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // adc
2873    { 0b0011101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // adcs
2874    { 0b0001101011000000010000, kW, kZR, kW, kZR, kW, kZR, false }, // crc32b
2875    { 0b0001101011000000010100, kW, kZR, kW, kZR, kW, kZR, false }, // crc32cb
2876    { 0b0001101011000000010101, kW, kZR, kW, kZR, kW, kZR, false }, // crc32ch
2877    { 0b0001101011000000010110, kW, kZR, kW, kZR, kW, kZR, false }, // crc32cw
2878    { 0b1001101011000000010111, kW, kZR, kW, kZR, kX, kZR, false }, // crc32cx
2879    { 0b0001101011000000010001, kW, kZR, kW, kZR, kW, kZR, false }, // crc32h
2880    { 0b0001101011000000010010, kW, kZR, kW, kZR, kW, kZR, false }, // crc32w
2881    { 0b1001101011000000010011, kW, kZR, kW, kZR, kX, kZR, false }, // crc32x
2882    { 0b1001101011000000000101, kX, kZR, kX, kSP, kX, kZR, true }, // gmi
2883    { 0b0001101100000000111111, kWX, kZR, kWX, kZR, kWX, kZR, true }, // mneg
2884    { 0b0001101100000000011111, kWX, kZR, kWX, kZR, kWX, kZR, true }, // mul
2885    { 0b1001101011000000001100, kX, kZR, kX, kZR, kX, kSP, false }, // pacga
2886    { 0b0101101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sbc
2887    { 0b0111101000000000000000, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sbcs
2888    { 0b0001101011000000000011, kWX, kZR, kWX, kZR, kWX, kZR, true }, // sdiv
2889    { 0b1001101100100000111111, kX, kZR, kW, kZR, kW, kZR, false }, // smnegl
2890    { 0b1001101101000000011111, kX, kZR, kX, kZR, kX, kZR, true }, // smulh
2891    { 0b1001101100100000011111, kX, kZR, kW, kZR, kW, kZR, false }, // smull
2892    { 0b1001101011000000000000, kX, kZR, kX, kSP, kX, kSP, false }, // subp
2893    { 0b1011101011000000000000, kX, kZR, kX, kSP, kX, kSP, false }, // subps
2894    { 0b0001101011000000000010, kWX, kZR, kWX, kZR, kWX, kZR, true }, // udiv
2895    { 0b1001101110100000111111, kX, kZR, kW, kZR, kW, kZR, false }, // umnegl
2896    { 0b1001101110100000011111, kX, kZR, kW, kZR, kW, kZR, false }, // umull
2897    { 0b1001101111000000011111, kX, kZR, kX, kZR, kX, kZR, false }  // umulh
2898});
2899
2900pub const BASE_RRRR: [BaseRRRR; 6] = table_new!(BaseRRRR, {
2901    { 0b0001101100000000000000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true }, // madd
2902    { 0b0001101100000000100000, kWX, kZR, kWX, kZR, kWX, kZR, kWX, kZR, true }, // msub
2903    { 0b1001101100100000000000, kX, kZR, kW, kZR, kW, kZR, kX, kZR, false }, // smaddl
2904    { 0b1001101100100000100000, kX, kZR, kW, kZR, kW, kZR, kX, kZR, false }, // smsubl
2905    { 0b1001101110100000000000, kX, kZR, kW, kZR, kW, kZR, kX, kZR, false }, // umaddl
2906    { 0b1001101110100000100000, kX, kZR, kW, kZR, kW, kZR, kX, kZR, false }  // umsubl
2907});
2908
2909pub const BASE_SHIFT: [BaseShift; 8] = table_new!(BaseShift, {
2910    { 0b0001101011000000001010, 0b0001001100000000011111, 0 }, // asr
2911    { 0b0001101011000000001010, 0b0000000000000000000000, 0 }, // asrv
2912    { 0b0001101011000000001000, 0b0101001100000000000000, 0 }, // lsl
2913    { 0b0001101011000000001000, 0b0000000000000000000000, 0 }, // lslv
2914    { 0b0001101011000000001001, 0b0101001100000000011111, 0 }, // lsr
2915    { 0b0001101011000000001001, 0b0000000000000000000000, 0 }, // lsrv
2916    { 0b0001101011000000001011, 0b0001001110000000000000, 1 }, // ror
2917    { 0b0001101011000000001011, 0b0000000000000000000000, 1 }  // rorv
2918});
2919
2920pub const BASE_STX: [BaseStx; 3] = table_new!(BaseStx, {
2921    { 0b1000100000000000011111, kWX, 30 }, // stxr
2922    { 0b0000100000000000011111, kW, 0 }, // stxrb
2923    { 0b0100100000000000011111, kW, 0 }  // stxrh
2924});
2925
2926pub const BASE_STXP: [BaseStxp; 2] = table_new!(BaseStxp, {
2927    { 0b1000100000100000100000, kWX, 30 }, // stlxp
2928    { 0b1000100000100000000000, kWX, 30 }  // stxp
2929});
2930
2931pub const BASE_TST: [BaseTst; 1] = table_new!(BaseTst, {
2932    { 0b1101010000, 0b111001000 }  // tst
2933});
2934
2935pub const F_SIMD_PAIR: [FSimdPair; 5] = table_new!(FSimdPair, {
2936    { 0b0111111000110000110110, 0b0010111000100000110101 }, // faddp_v
2937    { 0b0111111000110000110010, 0b0010111000100000110001 }, // fmaxnmp_v
2938    { 0b0111111000110000111110, 0b0010111000100000111101 }, // fmaxp_v
2939    { 0b0111111010110000110010, 0b0010111010100000110001 }, // fminnmp_v
2940    { 0b0111111010110000111110, 0b0010111010100000111101 }  // fminp_v
2941});
2942
2943pub const F_SIMD_SV: [FSimdSV; 4] = table_new!(FSimdSV, {
2944    { 0b0010111000110000110010 }, // fmaxnmv_v
2945    { 0b0010111000110000111110 }, // fmaxv_v
2946    { 0b0010111010110000110010 }, // fminnmv_v
2947    { 0b0010111010110000111110 }  // fminv_v
2948});
2949
2950pub const F_SIMD_VV: [FSimdVV; 17] = table_new!(FSimdVV, {
2951    { 0b0001111000100000110000, kHF_A, 0b0000111010100000111110, kHF_B }, // fabs_v
2952    { 0b0001111000100001010000, kHF_A, 0b0010111010100000111110, kHF_B }, // fneg_v
2953    { 0b0101111010100001110110, kHF_B, 0b0000111010100001110110, kHF_B }, // frecpe_v
2954    { 0b0101111010100001111110, kHF_B, 0b0000000000000000000000, kHF_N }, // frecpx_v
2955    { 0b0001111000101000110000, kHF_N, 0b0010111000100001111010, kHF_N }, // frint32x_v
2956    { 0b0001111000101000010000, kHF_N, 0b0000111000100001111010, kHF_N }, // frint32z_v
2957    { 0b0001111000101001110000, kHF_N, 0b0010111000100001111110, kHF_N }, // frint64x_v
2958    { 0b0001111000101001010000, kHF_N, 0b0000111000100001111110, kHF_N }, // frint64z_v
2959    { 0b0001111000100110010000, kHF_A, 0b0010111000100001100010, kHF_B }, // frinta_v
2960    { 0b0001111000100111110000, kHF_A, 0b0010111010100001100110, kHF_B }, // frinti_v
2961    { 0b0001111000100101010000, kHF_A, 0b0000111000100001100110, kHF_B }, // frintm_v
2962    { 0b0001111000100100010000, kHF_A, 0b0000111000100001100010, kHF_B }, // frintn_v
2963    { 0b0001111000100100110000, kHF_A, 0b0000111010100001100010, kHF_B }, // frintp_v
2964    { 0b0001111000100111010000, kHF_A, 0b0010111000100001100110, kHF_B }, // frintx_v
2965    { 0b0001111000100101110000, kHF_A, 0b0000111010100001100110, kHF_B }, // frintz_v
2966    { 0b0111111010100001110110, kHF_B, 0b0010111010100001110110, kHF_B }, // frsqrte_v
2967    { 0b0001111000100001110000, kHF_A, 0b0010111010100001111110, kHF_B }  // fsqrt_v
2968});
2969
2970pub const F_SIMD_VVV: [FSimdVVV; 13] = table_new!(FSimdVVV, {
2971    { 0b0111111010100000110101, kHF_C, 0b0010111010100000110101, kHF_C }, // fabd_v
2972    { 0b0111111000100000111011, kHF_C, 0b0010111000100000111011, kHF_C }, // facge_v
2973    { 0b0111111010100000111011, kHF_C, 0b0010111010100000111011, kHF_C }, // facgt_v
2974    { 0b0001111000100000001010, kHF_A, 0b0000111000100000110101, kHF_C }, // fadd_v
2975    { 0b0001111000100000000110, kHF_A, 0b0010111000100000111111, kHF_C }, // fdiv_v
2976    { 0b0001111000100000010010, kHF_A, 0b0000111000100000111101, kHF_C }, // fmax_v
2977    { 0b0001111000100000011010, kHF_A, 0b0000111000100000110001, kHF_C }, // fmaxnm_v
2978    { 0b0001111000100000010110, kHF_A, 0b0000111010100000111101, kHF_C }, // fmin_v
2979    { 0b0001111000100000011110, kHF_A, 0b0000111010100000110001, kHF_C }, // fminnm_v
2980    { 0b0001111000100000100010, kHF_A, 0b0000000000000000000000, kHF_N }, // fnmul_v
2981    { 0b0101111000100000111111, kHF_C, 0b0000111000100000111111, kHF_C }, // frecps_v
2982    { 0b0101111010100000111111, kHF_C, 0b0000111010100000111111, kHF_C }, // frsqrts_v
2983    { 0b0001111000100000001110, kHF_A, 0b0000111010100000110101, kHF_C }  // fsub_v
2984});
2985
2986pub const F_SIMD_VVVV: [FSimdVVVV; 4] = table_new!(FSimdVVVV, {
2987    { 0b0001111100000000000000, kHF_A, 0b0000000000000000000000, kHF_N }, // fmadd_v
2988    { 0b0001111100000000100000, kHF_A, 0b0000000000000000000000, kHF_N }, // fmsub_v
2989    { 0b0001111100100000000000, kHF_A, 0b0000000000000000000000, kHF_N }, // fnmadd_v
2990    { 0b0001111100100000100000, kHF_A, 0b0000000000000000000000, kHF_N }  // fnmsub_v
2991});
2992
2993pub const F_SIMD_VVVE: [FSimdVVVe; 4] = table_new!(FSimdVVVe, {
2994    { 0b0000000000000000000000, kHF_N, 0b0000111000100000110011, 0b0000111110000000000100 }, // fmla_v
2995    { 0b0000000000000000000000, kHF_N, 0b0000111010100000110011, 0b0000111110000000010100 }, // fmls_v
2996    { 0b0001111000100000000010, kHF_A, 0b0010111000100000110111, 0b0000111110000000100100 }, // fmul_v
2997    { 0b0101111000100000110111, kHF_C, 0b0000111000100000110111, 0b0010111110000000100100 }  // fmulx_v
2998});
2999
3000pub const I_SIMD_PAIR: [ISimdPair; 1] = table_new!(ISimdPair, {
3001    { 0b0101111000110001101110, 0b0000111000100000101111, kVO_V_Any }  // addp_v
3002});
3003
3004pub const I_SIMD_SV: [ISimdSV; 7] = table_new!(ISimdSV, {
3005    { 0b0000111000110001101110, kVO_V_BH_4S }, // addv_v
3006    { 0b0000111000110000001110, kVO_V_BH_4S }, // saddlv_v
3007    { 0b0000111000110000101010, kVO_V_BH_4S }, // smaxv_v
3008    { 0b0000111000110001101010, kVO_V_BH_4S }, // sminv_v
3009    { 0b0010111000110000001110, kVO_V_BH_4S }, // uaddlv_v
3010    { 0b0010111000110000101010, kVO_V_BH_4S }, // umaxv_v
3011    { 0b0010111000110001101010, kVO_V_BH_4S }  // uminv_v
3012});
3013
3014pub const I_SIMD_VV: [ISimdVV; 29] = table_new!(ISimdVV, {
3015    { 0b0000111000100000101110, kVO_V_Any }, // abs_v
3016    { 0b0000111000100000010010, kVO_V_BHS }, // cls_v
3017    { 0b0010111000100000010010, kVO_V_BHS }, // clz_v
3018    { 0b0000111000100000010110, kVO_V_B }, // cnt_v
3019    { 0b0010111000100000010110, kVO_V_B }, // mvn_v
3020    { 0b0010111000100000101110, kVO_V_Any }, // neg_v
3021    { 0b0010111000100000010110, kVO_V_B }, // not_v
3022    { 0b0010111001100000010110, kVO_V_B }, // rbit_v
3023    { 0b0000111000100000000110, kVO_V_B }, // rev16_v
3024    { 0b0010111000100000000010, kVO_V_BH }, // rev32_v
3025    { 0b0000111000100000000010, kVO_V_BHS }, // rev64_v
3026    { 0b0000111000100000011010, kVO_V_BHS }, // sadalp_v
3027    { 0b0000111000100000001010, kVO_V_BHS }, // saddlp_v
3028    { 0b0000111000100000011110, kVO_SV_Any }, // sqabs_v
3029    { 0b0010111000100000011110, kVO_SV_Any }, // sqneg_v
3030    { 0b0000111000100001010010, kVO_SV_B8H4S2 }, // sqxtn_v
3031    { 0b0100111000100001010010, kVO_V_B16H8S4 }, // sqxtn2_v
3032    { 0b0010111000100001001010, kVO_SV_B8H4S2 }, // sqxtun_v
3033    { 0b0110111000100001001010, kVO_V_B16H8S4 }, // sqxtun2_v
3034    { 0b0000111000100000001110, kVO_SV_Any }, // suqadd_v
3035    { 0b0010111000100000011010, kVO_V_BHS }, // uadalp_v
3036    { 0b0010111000100000001010, kVO_V_BHS }, // uaddlp_v
3037    { 0b0010111000100001010010, kVO_SV_B8H4S2 }, // uqxtn_v
3038    { 0b0110111000100001010010, kVO_V_B16H8S4 }, // uqxtn2_v
3039    { 0b0000111010100001110010, kVO_V_S }, // urecpe_v
3040    { 0b0010111010100001110010, kVO_V_S }, // ursqrte_v
3041    { 0b0010111000100000001110, kVO_SV_Any }, // usqadd_v
3042    { 0b0000111000100001001010, kVO_V_B8H4S2 }, // xtn_v
3043    { 0b0100111000100001001010, kVO_V_B16H8S4 }  // xtn2_v
3044});
3045
3046pub const I_SIMD_VVV: [ISimdVVV; 65] = table_new!(ISimdVVV, {
3047    { 0b0000111000100000100001, kVO_V_Any }, // add_v
3048    { 0b0000111000100000010000, kVO_V_B8H4S2 }, // addhn_v
3049    { 0b0100111000100000010000, kVO_V_B16H8S4 }, // addhn2_v
3050    { 0b0000111000100000000111, kVO_V_B }, // and_v
3051    { 0b0010111011100000000111, kVO_V_B }, // bif_v
3052    { 0b0010111010100000000111, kVO_V_B }, // bit_v
3053    { 0b0010111001100000000111, kVO_V_B }, // bsl_v
3054    { 0b0000111000100000100011, kVO_V_Any }, // cmtst_v
3055    { 0b0010111000100000000111, kVO_V_B }, // eor_v
3056    { 0b0000111011100000000111, kVO_V_B }, // orn_v
3057    { 0b0010111000100000100111, kVO_V_B }, // pmul_v
3058    { 0b0000111000100000111000, kVO_V_B8D1 }, // pmull_v
3059    { 0b0100111000100000111000, kVO_V_B16D2 }, // pmull2_v
3060    { 0b0010111000100000010000, kVO_V_B8H4S2 }, // raddhn_v
3061    { 0b0110111000100000010000, kVO_V_B16H8S4 }, // raddhn2_v
3062    { 0b1100111001100000100011, kVO_V_D2 }, // rax1_v
3063    { 0b0010111000100000011000, kVO_V_B8H4S2 }, // rsubhn_v
3064    { 0b0110111000100000011000, kVO_V_B16H8S4 }, // rsubhn2_v
3065    { 0b0000111000100000011111, kVO_V_BHS }, // saba_v
3066    { 0b0000111000100000010100, kVO_V_B8H4S2 }, // sabal_v
3067    { 0b0100111000100000010100, kVO_V_B16H8S4 }, // sabal2_v
3068    { 0b0000111000100000011101, kVO_V_BHS }, // sabd_v
3069    { 0b0000111000100000011100, kVO_V_B8H4S2 }, // sabdl_v
3070    { 0b0100111000100000011100, kVO_V_B16H8S4 }, // sabdl2_v
3071    { 0b0000111000100000000000, kVO_V_B8H4S2 }, // saddl_v
3072    { 0b0100111000100000000000, kVO_V_B16H8S4 }, // saddl2_v
3073    { 0b0000111000100000000001, kVO_V_BHS }, // shadd_v
3074    { 0b0000111000100000001001, kVO_V_BHS }, // shsub_v
3075    { 0b0000111000100000011001, kVO_V_BHS }, // smax_v
3076    { 0b0000111000100000101001, kVO_V_BHS }, // smaxp_v
3077    { 0b0000111000100000011011, kVO_V_BHS }, // smin_v
3078    { 0b0000111000100000101011, kVO_V_BHS }, // sminp_v
3079    { 0b0000111000100000000011, kVO_SV_Any }, // sqadd_v
3080    { 0b0000111000100000001011, kVO_SV_Any }, // sqsub_v
3081    { 0b0000111000100000000101, kVO_V_BHS }, // srhadd_v
3082    { 0b0000111000100000001000, kVO_V_B8H4S2 }, // ssubl_v
3083    { 0b0100111000100000001000, kVO_V_B16H8S4 }, // ssubl2_v
3084    { 0b0010111000100000100001, kVO_V_Any }, // sub_v
3085    { 0b0000111000100000011000, kVO_V_B8H4S2 }, // subhn_v
3086    { 0b0000111000100000011000, kVO_V_B16H8S4 }, // subhn2_v
3087    { 0b0000111000000000001010, kVO_V_BHS_D2 }, // trn1_v
3088    { 0b0000111000000000011010, kVO_V_BHS_D2 }, // trn2_v
3089    { 0b0010111000100000011111, kVO_V_BHS }, // uaba_v
3090    { 0b0010111000100000010100, kVO_V_B8H4S2 }, // uabal_v
3091    { 0b0110111000100000010100, kVO_V_B16H8S4 }, // uabal2_v
3092    { 0b0010111000100000011101, kVO_V_BHS }, // uabd_v
3093    { 0b0010111000100000011100, kVO_V_B8H4S2 }, // uabdl_v
3094    { 0b0110111000100000011100, kVO_V_B16H8S4 }, // uabdl2_v
3095    { 0b0010111000100000000000, kVO_V_B8H4S2 }, // uaddl_v
3096    { 0b0110111000100000000000, kVO_V_B16H8S4 }, // uaddl2_v
3097    { 0b0010111000100000000001, kVO_V_BHS }, // uhadd_v
3098    { 0b0010111000100000001001, kVO_V_BHS }, // uhsub_v
3099    { 0b0010111000100000011001, kVO_V_BHS }, // umax_v
3100    { 0b0010111000100000101001, kVO_V_BHS }, // umaxp_v
3101    { 0b0010111000100000011011, kVO_V_BHS }, // umin_v
3102    { 0b0010111000100000101011, kVO_V_BHS }, // uminp_v
3103    { 0b0010111000100000000011, kVO_SV_Any }, // uqadd_v
3104    { 0b0010111000100000001011, kVO_SV_Any }, // uqsub_v
3105    { 0b0010111000100000000101, kVO_V_BHS }, // urhadd_v
3106    { 0b0010111000100000001000, kVO_V_B8H4S2 }, // usubl_v
3107    { 0b0110111000100000001000, kVO_V_B16H8S4 }, // usubl2_v
3108    { 0b0000111000000000000110, kVO_V_BHS_D2 }, // uzp1_v
3109    { 0b0000111000000000010110, kVO_V_BHS_D2 }, // uzp2_v
3110    { 0b0000111000000000001110, kVO_V_BHS_D2 }, // zip1_v
3111    { 0b0000111000000000011110, kVO_V_BHS_D2 }  // zip2_v
3112});
3113
3114pub const I_SIMD_VVVI: [ISimdVVVI; 2] = table_new!(ISimdVVVI, {
3115    { 0b0010111000000000000000, kVO_V_B, 4, 11, 1 }, // ext_v
3116    { 0b1100111001100000100011, kVO_V_D2, 6, 10, 0 }  // xar_v
3117});
3118
3119pub const I_SIMD_VVVV: [ISimdVVVV; 2] = table_new!(ISimdVVVV, {
3120    { 0b1100111000100000000000, kVO_V_B16 }, // bcax_v
3121    { 0b1100111000000000000000, kVO_V_B16 }  // eor3_v
3122});
3123
3124pub const I_SIMD_VVVVX: [ISimdVVVVx; 1] = table_new!(ISimdVVVVx, {
3125    { 0b1100111001000000000000, kOp_V4S, kOp_V4S, kOp_V4S, kOp_V4S }  // sm3ss1_v
3126});
3127
3128pub const I_SIMD_VVVE: [ISimdVVVe; 25] = table_new!(ISimdVVVe, {
3129    { 0b0000111000100000100101, kVO_V_BHS, 0b0010111100000000000000, kVO_V_HS }, // mla_v
3130    { 0b0010111000100000100101, kVO_V_BHS, 0b0010111100000000010000, kVO_V_HS }, // mls_v
3131    { 0b0000111000100000100111, kVO_V_BHS, 0b0000111100000000100000, kVO_V_HS }, // mul_v
3132    { 0b0000111000100000100000, kVO_V_B8H4S2, 0b0000111100000000001000, kVO_V_H4S2 }, // smlal_v
3133    { 0b0100111000100000100000, kVO_V_B16H8S4, 0b0100111100000000001000, kVO_V_H8S4 }, // smlal2_v
3134    { 0b0000111000100000101000, kVO_V_B8H4S2, 0b0000111100000000011000, kVO_V_H4S2 }, // smlsl_v
3135    { 0b0100111000100000101000, kVO_V_B16H8S4, 0b0100111100000000011000, kVO_V_H8S4 }, // smlsl2_v
3136    { 0b0000111000100000110000, kVO_V_B8H4S2, 0b0000111100000000101000, kVO_V_H4S2 }, // smull_v
3137    { 0b0100111000100000110000, kVO_V_B16H8S4, 0b0100111100000000101000, kVO_V_H8S4 }, // smull2_v
3138    { 0b0000111000100000100100, kVO_SV_BHS, 0b0000111100000000001100, kVO_V_H4S2 }, // sqdmlal_v
3139    { 0b0100111000100000100100, kVO_V_B16H8S4, 0b0100111100000000001100, kVO_V_H8S4 }, // sqdmlal2_v
3140    { 0b0000111000100000101100, kVO_SV_BHS, 0b0000111100000000011100, kVO_V_H4S2 }, // sqdmlsl_v
3141    { 0b0100111000100000101100, kVO_V_B16H8S4, 0b0100111100000000011100, kVO_V_H8S4 }, // sqdmlsl2_v
3142    { 0b0000111000100000101101, kVO_SV_HS, 0b0000111100000000110000, kVO_SV_HS }, // sqdmulh_v
3143    { 0b0000111000100000110100, kVO_SV_BHS, 0b0000111100000000101100, kVO_V_H4S2 }, // sqdmull_v
3144    { 0b0100111000100000110100, kVO_V_B16H8S4, 0b0100111100000000101100, kVO_V_H8S4 }, // sqdmull2_v
3145    { 0b0010111000000000100001, kVO_SV_HS, 0b0010111100000000110100, kVO_SV_HS }, // sqrdmlah_v
3146    { 0b0010111000000000100011, kVO_SV_HS, 0b0010111100000000111100, kVO_SV_HS }, // sqrdmlsh_v
3147    { 0b0010111000100000101101, kVO_SV_HS, 0b0000111100000000110100, kVO_SV_HS }, // sqrdmulh_v
3148    { 0b0010111000100000100000, kVO_V_B8H4S2, 0b0010111100000000001000, kVO_V_H4S2 }, // umlal_v
3149    { 0b0110111000100000100000, kVO_V_B16H8S4, 0b0010111100000000001000, kVO_V_H8S4 }, // umlal2_v
3150    { 0b0010111000100000101000, kVO_V_B8H4S2, 0b0010111100000000011000, kVO_V_H4S2 }, // umlsl_v
3151    { 0b0110111000100000101000, kVO_V_B16H8S4, 0b0110111100000000011000, kVO_V_H8S4 }, // umlsl2_v
3152    { 0b0010111000100000110000, kVO_V_B8H4S2, 0b0010111100000000101000, kVO_V_H4S2 }, // umull_v
3153    { 0b0110111000100000110000, kVO_V_B16H8S4, 0b0110111100000000101000, kVO_V_H8S4 }  // umull2_v
3154});
3155
3156pub const I_SIMD_VVVX: [ISimdVVVx; 17] = table_new!(ISimdVVVx, {
3157    { 0b0110111001000000111011, kOp_V4S, kOp_V8H, kOp_V8H }, // bfmmla_v
3158    { 0b0101111000000000000000, kOp_Q, kOp_S, kOp_V4S }, // sha1c_v
3159    { 0b0101111000000000001000, kOp_Q, kOp_S, kOp_V4S }, // sha1m_v
3160    { 0b0101111000000000000100, kOp_Q, kOp_S, kOp_V4S }, // sha1p_v
3161    { 0b0101111000000000001100, kOp_V4S, kOp_V4S, kOp_V4S }, // sha1su0_v
3162    { 0b0101111000000000010000, kOp_Q, kOp_Q, kOp_V4S }, // sha256h_v
3163    { 0b0101111000000000010100, kOp_Q, kOp_Q, kOp_V4S }, // sha256h2_v
3164    { 0b0101111000000000011000, kOp_V4S, kOp_V4S, kOp_V4S }, // sha256su1_v
3165    { 0b1100111001100000100000, kOp_Q, kOp_Q, kOp_V2D }, // sha512h_v
3166    { 0b1100111001100000100001, kOp_Q, kOp_Q, kOp_V2D }, // sha512h2_v
3167    { 0b1100111001100000100010, kOp_V2D, kOp_V2D, kOp_V2D }, // sha512su1_v
3168    { 0b1100111001100000110000, kOp_V4S, kOp_V4S, kOp_V4S }, // sm3partw1_v
3169    { 0b1100111001100000110001, kOp_V4S, kOp_V4S, kOp_V4S }, // sm3partw2_v
3170    { 0b1100111001100000110010, kOp_V4S, kOp_V4S, kOp_V4S }, // sm4ekey_v
3171    { 0b0100111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B }, // smmla_v
3172    { 0b0110111010000000101001, kOp_V4S, kOp_V16B, kOp_V16B }, // ummla_v
3173    { 0b0100111010000000101011, kOp_V4S, kOp_V16B, kOp_V16B }  // usmmla_v
3174});
3175
3176pub const I_SIMD_VVX: [ISimdVVx; 13] = table_new!(ISimdVVx, {
3177    { 0b0100111000101000010110, kOp_V16B, kOp_V16B }, // aesd_v
3178    { 0b0100111000101000010010, kOp_V16B, kOp_V16B }, // aese_v
3179    { 0b0100111000101000011110, kOp_V16B, kOp_V16B }, // aesimc_v
3180    { 0b0100111000101000011010, kOp_V16B, kOp_V16B }, // aesmc_v
3181    { 0b0001111001100011010000, kOp_H, kOp_S }, // bfcvt_v
3182    { 0b0000111010100001011010, kOp_V4H, kOp_V4S }, // bfcvtn_v
3183    { 0b0100111010100001011010, kOp_V8H, kOp_V4S }, // bfcvtn2_v
3184    { 0b0001111001111110000000, kOp_GpW, kOp_D }, // fjcvtzs_v
3185    { 0b0101111000101000000010, kOp_S, kOp_S }, // sha1h_v
3186    { 0b0101111000101000000110, kOp_V4S, kOp_V4S }, // sha1su1_v
3187    { 0b0101111000101000001010, kOp_V4S, kOp_V4S }, // sha256su0_v
3188    { 0b1100111011000000100000, kOp_V2D, kOp_V2D }, // sha512su0_v
3189    { 0b1100111011000000100001, kOp_V4S, kOp_V4S }  // sm4e_v
3190});
3191
3192pub const I_SIMD_WWV: [ISimdWWV; 8] = table_new!(ISimdWWV, {
3193    { 0b0000111000100000000100, kVO_V_B8H4S2 }, // saddw_v
3194    { 0b0000111000100000000100, kVO_V_B16H8S4 }, // saddw2_v
3195    { 0b0000111000100000001100, kVO_V_B8H4S2 }, // ssubw_v
3196    { 0b0000111000100000001100, kVO_V_B16H8S4 }, // ssubw2_v
3197    { 0b0010111000100000000100, kVO_V_B8H4S2 }, // uaddw_v
3198    { 0b0010111000100000000100, kVO_V_B16H8S4 }, // uaddw2_v
3199    { 0b0010111000100000001100, kVO_V_B8H4S2 }, // usubw_v
3200    { 0b0010111000100000001100, kVO_V_B16H8S4 }  // usubw2_v
3201});
3202
3203pub const SIMD_BIC_ORR: [SimdBicOrr; 2] = table_new!(SimdBicOrr, {
3204    { 0b0000111001100000000111, 0b0010111100000000000001 }, // bic_v
3205    { 0b0000111010100000000111, 0b0000111100000000000001 }  // orr_v
3206});
3207
3208pub const SIMD_CMP: [SimdCmp; 7] = table_new!(SimdCmp, {
3209    { 0b0010111000100000100011, 0b0000111000100000100110, kVO_V_Any }, // cmeq_v
3210    { 0b0000111000100000001111, 0b0010111000100000100010, kVO_V_Any }, // cmge_v
3211    { 0b0000111000100000001101, 0b0000111000100000100010, kVO_V_Any }, // cmgt_v
3212    { 0b0010111000100000001101, 0b0000000000000000000000, kVO_V_Any }, // cmhi_v
3213    { 0b0010111000100000001111, 0b0000000000000000000000, kVO_V_Any }, // cmhs_v
3214    { 0b0000000000000000000000, 0b0010111000100000100110, kVO_V_Any }, // cmle_v
3215    { 0b0000000000000000000000, 0b0000111000100000101010, kVO_V_Any }  // cmlt_v
3216});
3217
3218pub const SIMD_DOT: [SimdDot; 5] = table_new!(SimdDot, {
3219    { 0b0010111001000000111111, 0b0000111101000000111100, kET_S, kET_H, kET_2H }, // bfdot_v
3220    { 0b0000111010000000100101, 0b0000111110000000111000, kET_S, kET_B, kET_4B }, // sdot_v
3221    { 0b0000000000000000000000, 0b0000111100000000111100, kET_S, kET_B, kET_4B }, // sudot_v
3222    { 0b0010111010000000100101, 0b0010111110000000111000, kET_S, kET_B, kET_4B }, // udot_v
3223    { 0b0000111010000000100111, 0b0000111110000000111100, kET_S, kET_B, kET_4B }  // usdot_v
3224});
3225
3226pub const SIMD_FCADD: [SimdFcadd; 1] = table_new!(SimdFcadd, {
3227    { 0b0010111000000000111001 } // fcadd_v
3228});
3229
3230pub const SIMD_FCCMP_FCCMPE: [SimdFccmpFccmpe; 2] = table_new!(SimdFccmpFccmpe, {
3231    { 0b00011110001000000000010000000000 }, // fccmp_v
3232    { 0b00011110001000000000010000010000 }  // fccmpe_v
3233});
3234
3235pub const SIMD_FCM: [SimdFcm; 5] = table_new!(SimdFcm, {
3236    { 0b0000111000100000111001, kHF_C, 0b0000111010100000110110 }, // fcmeq_v
3237    { 0b0010111000100000111001, kHF_C, 0b0010111010100000110010 }, // fcmge_v
3238    { 0b0010111010100000111001, kHF_C, 0b0000111010100000110010 }, // fcmgt_v
3239    { 0b0000000000000000000000, kHF_C, 0b0010111010100000110110 }, // fcmle_v
3240    { 0b0000000000000000000000, kHF_C, 0b0000111010100000111010 }  // fcmlt_v
3241});
3242
3243pub const SIMD_FCMLA: [SimdFcmla; 1] = table_new!(SimdFcmla, {
3244    { 0b0010111000000000110001, 0b0010111100000000000100 }  // fcmla_v
3245});
3246
3247pub const SIMD_FCMP_FCMPE: [SimdFcmpFcmpe; 2] = table_new!(SimdFcmpFcmpe, {
3248    { 0b00011110001000000010000000000000 }, // fcmp_v
3249    { 0b00011110001000000010000000010000 }  // fcmpe_v
3250});
3251
3252pub const SIMD_FCVT_LN: [SimdFcvtLN; 6] = table_new!(SimdFcvtLN, {
3253    { 0b0000111000100001011110, 0, 0 }, // fcvtl_v
3254    { 0b0100111000100001011110, 0, 0 }, // fcvtl2_v
3255    { 0b0000111000100001011010, 0, 0 }, // fcvtn_v
3256    { 0b0100111000100001011010, 0, 0 }, // fcvtn2_v
3257    { 0b0010111000100001011010, 1, 1 }, // fcvtxn_v
3258    { 0b0110111000100001011010, 1, 0 }  // fcvtxn2_v
3259});
3260
3261pub const SIMD_FCVT_SV: [SimdFcvtSV; 12] = table_new!(SimdFcvtSV, {
3262    { 0b0000111000100001110010, 0b0000000000000000000000, 0b0001111000100100000000, 1 }, // fcvtas_v
3263    { 0b0010111000100001110010, 0b0000000000000000000000, 0b0001111000100101000000, 1 }, // fcvtau_v
3264    { 0b0000111000100001101110, 0b0000000000000000000000, 0b0001111000110000000000, 1 }, // fcvtms_v
3265    { 0b0010111000100001101110, 0b0000000000000000000000, 0b0001111000110001000000, 1 }, // fcvtmu_v
3266    { 0b0000111000100001101010, 0b0000000000000000000000, 0b0001111000100000000000, 1 }, // fcvtns_v
3267    { 0b0010111000100001101010, 0b0000000000000000000000, 0b0001111000100001000000, 1 }, // fcvtnu_v
3268    { 0b0000111010100001101010, 0b0000000000000000000000, 0b0001111000101000000000, 1 }, // fcvtps_v
3269    { 0b0010111010100001101010, 0b0000000000000000000000, 0b0001111000101001000000, 1 }, // fcvtpu_v
3270    { 0b0000111010100001101110, 0b0000111100000000111111, 0b0001111000111000000000, 1 }, // fcvtzs_v
3271    { 0b0010111010100001101110, 0b0010111100000000111111, 0b0001111000111001000000, 1 }, // fcvtzu_v
3272    { 0b0000111000100001110110, 0b0000111100000000111001, 0b0001111000100010000000, 0 }, // scvtf_v
3273    { 0b0010111000100001110110, 0b0010111100000000111001, 0b0001111000100011000000, 0 }  // ucvtf_v
3274});
3275
3276pub const SIMD_FMLAL: [SimdFmlal; 6] = table_new!(SimdFmlal, {
3277    { 0b0010111011000000111111, 0b0000111111000000111100, 0, kET_S, kET_H, kET_H }, // bfmlalb_v
3278    { 0b0110111011000000111111, 0b0100111111000000111100, 0, kET_S, kET_H, kET_H }, // bfmlalt_v
3279    { 0b0000111000100000111011, 0b0000111110000000000000, 1, kET_S, kET_H, kET_H }, // fmlal_v
3280    { 0b0010111000100000110011, 0b0010111110000000100000, 1, kET_S, kET_H, kET_H }, // fmlal2_v
3281    { 0b0000111010100000111011, 0b0000111110000000010000, 1, kET_S, kET_H, kET_H }, // fmlsl_v
3282    { 0b0010111010100000110011, 0b0010111110000000110000, 1, kET_S, kET_H, kET_H }  // fmlsl2_v
3283});
3284
3285pub const SIMD_LD_N_ST_N: [SimdLdNStN; 12] = table_new!(SimdLdNStN, {
3286    { 0b0000110101000000000000, 0b0000110001000000001000, 1, 0 }, // ld1_v
3287    { 0b0000110101000000110000, 0b0000000000000000000000, 1, 1 }, // ld1r_v
3288    { 0b0000110101100000000000, 0b0000110001000000100000, 2, 0 }, // ld2_v
3289    { 0b0000110101100000110000, 0b0000000000000000000000, 2, 1 }, // ld2r_v
3290    { 0b0000110101000000001000, 0b0000110001000000010000, 3, 0 }, // ld3_v
3291    { 0b0000110101000000111000, 0b0000000000000000000000, 3, 1 }, // ld3r_v
3292    { 0b0000110101100000001000, 0b0000110001000000000000, 4, 0 }, // ld4_v
3293    { 0b0000110101100000111000, 0b0000000000000000000000, 4, 1 }, // ld4r_v
3294    { 0b0000110100000000000000, 0b0000110000000000001000, 1, 0 }, // st1_v
3295    { 0b0000110100100000000000, 0b0000110000000000100000, 2, 0 }, // st2_v
3296    { 0b0000110100000000001000, 0b0000110000000000010000, 3, 0 }, // st3_v
3297    { 0b0000110100100000001000, 0b0000110000000000000000, 4, 0 }  // st4_v
3298});
3299
3300pub const SIMD_LD_ST: [SimdLdSt; 2] = table_new!(SimdLdSt, {
3301    { 0b0011110101, 0b00111100010, 0b00111100011, 0b00011100, InstId::Ldur_v }, // ldr_v
3302    { 0b0011110100, 0b00111100000, 0b00111100001, 0b00000000, InstId::Stur_v }  // str_v
3303});
3304
3305pub const SIMD_LDP_STP: [SimdLdpStp; 4] = table_new!(SimdLdpStp, {
3306    { 0b0010110001, 0b0000000000 }, // ldnp_v
3307    { 0b0010110101, 0b0010110011 }, // ldp_v
3308    { 0b0010110000, 0b0000000000 }, // stnp_v
3309    { 0b0010110100, 0b0010110010 }  // stp_v
3310});
3311
3312pub const SIMD_LDUR_STUR: [SimdLdurStur; 2] = table_new!(SimdLdurStur, {
3313    { 0b0011110001000000000000 }, // ldur_v
3314    { 0b0011110000000000000000 }  // stur_v
3315});
3316
3317pub const SIMD_MOVI_MVNI: [SimdMoviMvni; 2] = table_new!(SimdMoviMvni, {
3318    { 0b0000111100000000000001, 0 }, // movi_v
3319    { 0b0000111100000000000001, 1 }  // mvni_v
3320});
3321
3322pub const SIMD_SHIFT: [SimdShift; 40] = table_new!(SimdShift, {
3323    { 0b0000000000000000000000, 0b0000111100000000100011, 1, kVO_V_B8H4S2 }, // rshrn_v
3324    { 0b0000000000000000000000, 0b0100111100000000100011, 1, kVO_V_B16H8S4 }, // rshrn2_v
3325    { 0b0000000000000000000000, 0b0000111100000000010101, 0, kVO_V_Any }, // shl_v
3326    { 0b0000000000000000000000, 0b0000111100000000100001, 1, kVO_V_B8H4S2 }, // shrn_v
3327    { 0b0000000000000000000000, 0b0100111100000000100001, 1, kVO_V_B16H8S4 }, // shrn2_v
3328    { 0b0000000000000000000000, 0b0010111100000000010101, 0, kVO_V_Any }, // sli_v
3329    { 0b0000111000100000010111, 0b0000000000000000000000, 1, kVO_SV_Any }, // sqrshl_v
3330    { 0b0000000000000000000000, 0b0000111100000000100111, 1, kVO_SV_B8H4S2 }, // sqrshrn_v
3331    { 0b0000000000000000000000, 0b0100111100000000100111, 1, kVO_V_B16H8S4 }, // sqrshrn2_v
3332    { 0b0000000000000000000000, 0b0010111100000000100011, 1, kVO_SV_B8H4S2 }, // sqrshrun_v
3333    { 0b0000000000000000000000, 0b0110111100000000100011, 1, kVO_V_B16H8S4 }, // sqrshrun2_v
3334    { 0b0000111000100000010011, 0b0000111100000000011101, 0, kVO_SV_Any }, // sqshl_v
3335    { 0b0000000000000000000000, 0b0010111100000000011001, 0, kVO_SV_Any }, // sqshlu_v
3336    { 0b0000000000000000000000, 0b0000111100000000100101, 1, kVO_SV_B8H4S2 }, // sqshrn_v
3337    { 0b0000000000000000000000, 0b0100111100000000100101, 1, kVO_V_B16H8S4 }, // sqshrn2_v
3338    { 0b0000000000000000000000, 0b0010111100000000100001, 1, kVO_SV_B8H4S2 }, // sqshrun_v
3339    { 0b0000000000000000000000, 0b0110111100000000100001, 1, kVO_V_B16H8S4 }, // sqshrun2_v
3340    { 0b0000000000000000000000, 0b0010111100000000010001, 1, kVO_V_Any }, // sri_v
3341    { 0b0000111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any }, // srshl_v
3342    { 0b0000000000000000000000, 0b0000111100000000001001, 1, kVO_V_Any }, // srshr_v
3343    { 0b0000000000000000000000, 0b0000111100000000001101, 1, kVO_V_Any }, // srsra_v
3344    { 0b0000111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any }, // sshl_v
3345    { 0b0000000000000000000000, 0b0000111100000000101001, 0, kVO_V_B8H4S2 }, // sshll_v
3346    { 0b0000000000000000000000, 0b0100111100000000101001, 0, kVO_V_B16H8S4 }, // sshll2_v
3347    { 0b0000000000000000000000, 0b0000111100000000000001, 1, kVO_V_Any }, // sshr_v
3348    { 0b0000000000000000000000, 0b0000111100000000000101, 1, kVO_V_Any }, // ssra_v
3349    { 0b0010111000100000010111, 0b0000000000000000000000, 0, kVO_SV_Any }, // uqrshl_v
3350    { 0b0000000000000000000000, 0b0010111100000000100111, 1, kVO_SV_B8H4S2 }, // uqrshrn_v
3351    { 0b0000000000000000000000, 0b0110111100000000100111, 1, kVO_V_B16H8S4 }, // uqrshrn2_v
3352    { 0b0010111000100000010011, 0b0010111100000000011101, 0, kVO_SV_Any }, // uqshl_v
3353    { 0b0000000000000000000000, 0b0010111100000000100101, 1, kVO_SV_B8H4S2 }, // uqshrn_v
3354    { 0b0000000000000000000000, 0b0110111100000000100101, 1, kVO_V_B16H8S4 }, // uqshrn2_v
3355    { 0b0010111000100000010101, 0b0000000000000000000000, 0, kVO_V_Any }, // urshl_v
3356    { 0b0000000000000000000000, 0b0010111100000000001001, 1, kVO_V_Any }, // urshr_v
3357    { 0b0000000000000000000000, 0b0010111100000000001101, 1, kVO_V_Any }, // ursra_v
3358    { 0b0010111000100000010001, 0b0000000000000000000000, 0, kVO_V_Any }, // ushl_v
3359    { 0b0000000000000000000000, 0b0010111100000000101001, 0, kVO_V_B8H4S2 }, // ushll_v
3360    { 0b0000000000000000000000, 0b0110111100000000101001, 0, kVO_V_B16H8S4 }, // ushll2_v
3361    { 0b0000000000000000000000, 0b0010111100000000000001, 1, kVO_V_Any }, // ushr_v
3362    { 0b0000000000000000000000, 0b0010111100000000000101, 1, kVO_V_Any }  // usra_v
3363});
3364
3365pub const SIMD_SHIFT_ES: [SimdShiftES; 2] = table_new!(SimdShiftES, {
3366    { 0b0010111000100001001110, kVO_V_B8H4S2 }, // shll_v
3367    { 0b0110111000100001001110, kVO_V_B16H8S4 }  // shll2_v
3368});
3369
3370pub const SIMD_SM3TT: [SimdSm3tt; 4] = table_new!(SimdSm3tt, {
3371    { 0b1100111001000000100000 }, // sm3tt1a_v
3372    { 0b1100111001000000100001 }, // sm3tt1b_v
3373    { 0b1100111001000000100010 }, // sm3tt2a_v
3374    { 0b1100111001000000100011 }  // sm3tt2b_v
3375});
3376
3377pub const SIMD_SMOV_UMOV: [SimdSmovUmov; 2] = table_new!(SimdSmovUmov, {
3378    { 0b0000111000000000001011, kVO_V_BHS, 1 }, // smov_v
3379    { 0b0000111000000000001111, kVO_V_Any, 0 }  // umov_v
3380});
3381
3382pub const SIMD_SXTL_UXTL: [SimdSxtlUxtl; 4] = table_new!(SimdSxtlUxtl, {
3383    { 0b0000111100000000101001, kVO_V_B8H4S2 }, // sxtl_v
3384    { 0b0100111100000000101001, kVO_V_B16H8S4 }, // sxtl2_v
3385    { 0b0010111100000000101001, kVO_V_B8H4S2 }, // uxtl_v
3386    { 0b0110111100000000101001, kVO_V_B16H8S4 }  // uxtl2_v
3387});
3388
3389pub const SIMD_TBL_TBX: [SimdTblTbx; 2] = table_new!(SimdTblTbx, {
3390    { 0b0000111000000000000000 }, // tbl_v
3391    { 0b0000111000000000000100 }  // tbx_v
3392});
3393
3394pub static INST_NAME_STRING_TABLE: &[u8] = b"autia1716autibldsmaxalhldsminalldumaxallduminalsha256su0sha512su1sm3partwsqrshrunldaddalldclralldeoralldsetallbstsmaxstsminstumaxstuminfrint32z64x64zh2sqdmlalsl2sqdmulsqrdmlaulhn2sqshruuqrshrspchkfeacrc32cstaddstclrsteorstsetxpaclbfcvtbfmlaltfcvtxfjcvtzfmaxnmfminnmfrsqrraddrsubsha1sm3tt12a2bsm4ekeysqxtuuqshrursqrsetfrev8";
3395#[rustfmt::skip]
3396pub static INST_NAME_INDEX_TABLE: &[u32] = &[
3397    0x80000000, // Small ''.
3398    0x80004C41, // Small 'abs'.
3399    0x80000C81, // Small 'adc'.
3400    0x80098C81, // Small 'adcs'.
3401    0x80001081, // Small 'add'.
3402    0x80039081, // Small 'addg'.
3403    0x80099081, // Small 'adds'.
3404    0x80004881, // Small 'adr'.
3405    0x80084881, // Small 'adrp'.
3406    0x800011C1, // Small 'and'.
3407    0x800991C1, // Small 'ands'.
3408    0x80004A61, // Small 'asr'.
3409    0x800B4A61, // Small 'asrv'.
3410    0x80000281, // Small 'at'.
3411    0x801252A1, // Small 'autda'.
3412    0x83A252A1, // Small 'autdza'.
3413    0x802252A1, // Small 'autdb'.
3414    0x85A252A1, // Small 'autdzb'.
3415    0x8014D2A1, // Small 'autia'.
3416    0x00009000, // Large 'autia1716'.
3417    0x20BF5000, // Large 'autia|sp'.
3418    0xB414D2A1, // Small 'autiaz'.
3419    0x8024D2A1, // Small 'autib'.
3420    0x40055009, // Large 'autib|1716'.
3421    0x20BF5009, // Large 'autib|sp'.
3422    0xB424D2A1, // Small 'autibz'.
3423    0x83A4D2A1, // Small 'autiza'.
3424    0x85A4D2A1, // Small 'autizb'.
3425    0x8E161B01, // Small 'axflag'.
3426    0x80000002, // Small 'b'.
3427    0x80000062, // Small 'bc'.
3428    0x80000CC2, // Small 'bfc'.
3429    0x800024C2, // Small 'bfi'.
3430    0x800034C2, // Small 'bfm'.
3431    0x80C4E0C2, // Small 'bfxil'.
3432    0x80000D22, // Small 'bic'.
3433    0x80098D22, // Small 'bics'.
3434    0x80000182, // Small 'bl'.
3435    0x80004982, // Small 'blr'.
3436    0x80000242, // Small 'br'.
3437    0x80002E42, // Small 'brk'.
3438    0x80002682, // Small 'bti'.
3439    0x80004C23, // Small 'cas'.
3440    0x8000CC23, // Small 'casa'.
3441    0x8020CC23, // Small 'casab'.
3442    0x8080CC23, // Small 'casah'.
3443    0x80C0CC23, // Small 'casal'.
3444    0x84C0CC23, // Small 'casalb'.
3445    0x90C0CC23, // Small 'casalh'.
3446    0x80014C23, // Small 'casb'.
3447    0x80044C23, // Small 'cash'.
3448    0x80064C23, // Small 'casl'.
3449    0x80264C23, // Small 'caslb'.
3450    0x80864C23, // Small 'caslh'.
3451    0x80084C23, // Small 'casp'.
3452    0x80184C23, // Small 'caspa'.
3453    0x98184C23, // Small 'caspal'.
3454    0x80C84C23, // Small 'caspl'.
3455    0x800D3843, // Small 'cbnz'.
3456    0x80006843, // Small 'cbz'.
3457    0x80073463, // Small 'ccmn'.
3458    0x80083463, // Small 'ccmp'.
3459    0x816724C3, // Small 'cfinv'.
3460    0x100260C1, // Large 'chkfea|t'.
3461    0x8001B923, // Small 'cinc'.
3462    0x800B3923, // Small 'cinv'.
3463    0x84814983, // Small 'clrbhb'.
3464    0x8182C983, // Small 'clrex'.
3465    0x80004D83, // Small 'cls'.
3466    0x80006983, // Small 'clz'.
3467    0x800039A3, // Small 'cmn'.
3468    0x800041A3, // Small 'cmp'.
3469    0x800841A3, // Small 'cmpp'.
3470    0x800395C3, // Small 'cneg'.
3471    0x800051C3, // Small 'cnt'.
3472    0x85DF0E43, // Small 'crc32b'.
3473    0x100D60C7, // Large 'crc32c|b'.
3474    0x101660C7, // Large 'crc32c|h'.
3475    0x104860C7, // Large 'crc32c|w'.
3476    0x101360C7, // Large 'crc32c|x'.
3477    0x91DF0E43, // Small 'crc32h'.
3478    0xAFDF0E43, // Small 'crc32w'.
3479    0xB1DF0E43, // Small 'crc32x'.
3480    0x80011263, // Small 'csdb'.
3481    0x80061663, // Small 'csel'.
3482    0x800A1663, // Small 'cset'.
3483    0x80DA1663, // Small 'csetm'.
3484    0x80372663, // Small 'csinc'.
3485    0x81672663, // Small 'csinv'.
3486    0x8072BA63, // Small 'csneg'.
3487    0x80006A83, // Small 'ctz'.
3488    0x80000064, // Small 'dc'.
3489    0x81C9C064, // Small 'dcps1'.
3490    0x81D9C064, // Small 'dcps2'.
3491    0x81E9C064, // Small 'dcps3'.
3492    0x800020E4, // Small 'dgh'.
3493    0x800009A4, // Small 'dmb'.
3494    0x8009C244, // Small 'drps'.
3495    0x80000A64, // Small 'dsb'.
3496    0x800039E5, // Small 'eon'.
3497    0x800049E5, // Small 'eor'.
3498    0x80000A65, // Small 'esb'.
3499    0x80095305, // Small 'extr'.
3500    0x800A1645, // Small 'eret'.
3501    0x800025A7, // Small 'gmi'.
3502    0x800A3928, // Small 'hint'.
3503    0x80005188, // Small 'hlt'.
3504    0x80000EC8, // Small 'hvc'.
3505    0x80000069, // Small 'ic'.
3506    0x80000A69, // Small 'isb'.
3507    0x8042048C, // Small 'ldadd'.
3508    0x8242048C, // Small 'ldadda'.
3509    0x100D6051, // Large 'ldadda|b'.
3510    0x10166051, // Large 'ldadda|h'.
3511    0x00007051, // Large 'ldaddal'.
3512    0x100D7051, // Large 'ldaddal|b'.
3513    0x10167051, // Large 'ldaddal|h'.
3514    0x8442048C, // Small 'ldaddb'.
3515    0x9042048C, // Small 'ldaddh'.
3516    0x9842048C, // Small 'ldaddl'.
3517    0x206D5051, // Large 'ldadd|lb'.
3518    0x20155051, // Large 'ldadd|lh'.
3519    0x8009048C, // Small 'ldar'.
3520    0x8029048C, // Small 'ldarb'.
3521    0x8089048C, // Small 'ldarh'.
3522    0x810C048C, // Small 'ldaxp'.
3523    0x812C048C, // Small 'ldaxr'.
3524    0x852C048C, // Small 'ldaxrb'.
3525    0x912C048C, // Small 'ldaxrh'.
3526    0x81260C8C, // Small 'ldclr'.
3527    0x83260C8C, // Small 'ldclra'.
3528    0x100D6058, // Large 'ldclra|b'.
3529    0x10166058, // Large 'ldclra|h'.
3530    0x00007058, // Large 'ldclral'.
3531    0x100D7058, // Large 'ldclral|b'.
3532    0x10167058, // Large 'ldclral|h'.
3533    0x85260C8C, // Small 'ldclrb'.
3534    0x91260C8C, // Small 'ldclrh'.
3535    0x99260C8C, // Small 'ldclrl'.
3536    0x206D5058, // Large 'ldclr|lb'.
3537    0x20155058, // Large 'ldclr|lh'.
3538    0x8127948C, // Small 'ldeor'.
3539    0x8327948C, // Small 'ldeora'.
3540    0x100D605F, // Large 'ldeora|b'.
3541    0x1016605F, // Large 'ldeora|h'.
3542    0x0000705F, // Large 'ldeoral'.
3543    0x100D705F, // Large 'ldeoral|b'.
3544    0x1016705F, // Large 'ldeoral|h'.
3545    0x8527948C, // Small 'ldeorb'.
3546    0x9127948C, // Small 'ldeorh'.
3547    0x9927948C, // Small 'ldeorl'.
3548    0x206D505F, // Large 'ldeor|lb'.
3549    0x2015505F, // Large 'ldeor|lh'.
3550    0x80001C8C, // Small 'ldg'.
3551    0x80069C8C, // Small 'ldgm'.
3552    0x8120B08C, // Small 'ldlar'.
3553    0x8520B08C, // Small 'ldlarb'.
3554    0x9120B08C, // Small 'ldlarh'.
3555    0x8008388C, // Small 'ldnp'.
3556    0x8000408C, // Small 'ldp'.
3557    0x8179C08C, // Small 'ldpsw'.
3558    0x8000488C, // Small 'ldr'.
3559    0x8010C88C, // Small 'ldraa'.
3560    0x8020C88C, // Small 'ldrab'.
3561    0x8001488C, // Small 'ldrb'.
3562    0x8004488C, // Small 'ldrh'.
3563    0x8029C88C, // Small 'ldrsb'.
3564    0x8089C88C, // Small 'ldrsh'.
3565    0x8179C88C, // Small 'ldrsw'.
3566    0x8142CC8C, // Small 'ldset'.
3567    0x8342CC8C, // Small 'ldseta'.
3568    0x100D6066, // Large 'ldseta|b'.
3569    0x10166066, // Large 'ldseta|h'.
3570    0x00007066, // Large 'ldsetal'.
3571    0x100D7066, // Large 'ldsetal|b'.
3572    0x10167066, // Large 'ldsetal|h'.
3573    0x8542CC8C, // Small 'ldsetb'.
3574    0x9142CC8C, // Small 'ldseth'.
3575    0x9942CC8C, // Small 'ldsetl'.
3576    0x206D5066, // Large 'ldset|lb'.
3577    0x20155066, // Large 'ldset|lh'.
3578    0xB016CC8C, // Small 'ldsmax'.
3579    0x0000700E, // Large 'ldsmaxa'.
3580    0x100D700E, // Large 'ldsmaxa|b'.
3581    0x1016700E, // Large 'ldsmaxa|h'.
3582    0x0000800E, // Large 'ldsmaxal'.
3583    0x100D800E, // Large 'ldsmaxal|b'.
3584    0x1016800E, // Large 'ldsmaxal|h'.
3585    0x100D600E, // Large 'ldsmax|b'.
3586    0x1016600E, // Large 'ldsmax|h'.
3587    0x100E600E, // Large 'ldsmax|l'.
3588    0x206D600E, // Large 'ldsmax|lb'.
3589    0x2015600E, // Large 'ldsmax|lh'.
3590    0x9C96CC8C, // Small 'ldsmin'.
3591    0x00007017, // Large 'ldsmina'.
3592    0x100D7017, // Large 'ldsmina|b'.
3593    0x10167017, // Large 'ldsmina|h'.
3594    0x00008017, // Large 'ldsminal'.
3595    0x100D8017, // Large 'ldsminal|b'.
3596    0x10168017, // Large 'ldsminal|h'.
3597    0x100D6017, // Large 'ldsmin|b'.
3598    0x10166017, // Large 'ldsmin|h'.
3599    0x100E6017, // Large 'ldsmin|l'.
3600    0x206D6017, // Large 'ldsmin|lb'.
3601    0x20156017, // Large 'ldsmin|lh'.
3602    0x8009508C, // Small 'ldtr'.
3603    0x8029508C, // Small 'ldtrb'.
3604    0x8089508C, // Small 'ldtrh'.
3605    0x8539508C, // Small 'ldtrsb'.
3606    0x9139508C, // Small 'ldtrsh'.
3607    0xAF39508C, // Small 'ldtrsw'.
3608    0xB016D48C, // Small 'ldumax'.
3609    0x0000701F, // Large 'ldumaxa'.
3610    0x100D701F, // Large 'ldumaxa|b'.
3611    0x1016701F, // Large 'ldumaxa|h'.
3612    0x0000801F, // Large 'ldumaxal'.
3613    0x100D801F, // Large 'ldumaxal|b'.
3614    0x1016801F, // Large 'ldumaxal|h'.
3615    0x100D601F, // Large 'ldumax|b'.
3616    0x1016601F, // Large 'ldumax|h'.
3617    0x100E601F, // Large 'ldumax|l'.
3618    0x206D601F, // Large 'ldumax|lb'.
3619    0x2015601F, // Large 'ldumax|lh'.
3620    0x9C96D48C, // Small 'ldumin'.
3621    0x00007027, // Large 'ldumina'.
3622    0x100D7027, // Large 'ldumina|b'.
3623    0x10167027, // Large 'ldumina|h'.
3624    0x00008027, // Large 'lduminal'.
3625    0x100D8027, // Large 'lduminal|b'.
3626    0x10168027, // Large 'lduminal|h'.
3627    0x100D6027, // Large 'ldumin|b'.
3628    0x10166027, // Large 'ldumin|h'.
3629    0x100E6027, // Large 'ldumin|l'.
3630    0x206D6027, // Large 'ldumin|lb'.
3631    0x20156027, // Large 'ldumin|lh'.
3632    0x8009548C, // Small 'ldur'.
3633    0x8029548C, // Small 'ldurb'.
3634    0x8089548C, // Small 'ldurh'.
3635    0x8539548C, // Small 'ldursb'.
3636    0x9139548C, // Small 'ldursh'.
3637    0xAF39548C, // Small 'ldursw'.
3638    0x8008608C, // Small 'ldxp'.
3639    0x8009608C, // Small 'ldxr'.
3640    0x8029608C, // Small 'ldxrb'.
3641    0x8089608C, // Small 'ldxrh'.
3642    0x8000326C, // Small 'lsl'.
3643    0x800B326C, // Small 'lslv'.
3644    0x80004A6C, // Small 'lsr'.
3645    0x800B4A6C, // Small 'lsrv'.
3646    0x8002102D, // Small 'madd'.
3647    0x800395CD, // Small 'mneg'.
3648    0x800059ED, // Small 'mov'.
3649    0x8005D9ED, // Small 'movk'.
3650    0x800759ED, // Small 'movn'.
3651    0x800D59ED, // Small 'movz'.
3652    0x80004E4D, // Small 'mrs'.
3653    0x80004A6D, // Small 'msr'.
3654    0x8001566D, // Small 'msub'.
3655    0x800032AD, // Small 'mul'.
3656    0x80003ACD, // Small 'mvn'.
3657    0x80001CAE, // Small 'neg'.
3658    0x80099CAE, // Small 'negs'.
3659    0x80000CEE, // Small 'ngc'.
3660    0x80098CEE, // Small 'ngcs'.
3661    0x800041EE, // Small 'nop'.
3662    0x80003A4F, // Small 'orn'.
3663    0x80004A4F, // Small 'orr'.
3664    0x80120C30, // Small 'pacda'.
3665    0x80220C30, // Small 'pacdb'.
3666    0x83A20C30, // Small 'pacdza'.
3667    0x85A20C30, // Small 'pacdzb'.
3668    0x80138C30, // Small 'pacga'.
3669    0x80069A50, // Small 'prfm'.
3670    0x80214E70, // Small 'pssbb'.
3671    0x800A2452, // Small 'rbit'.
3672    0x800050B2, // Small 'ret'.
3673    0x800058B2, // Small 'rev'.
3674    0x2007313E, // Large 'rev|16'.
3675    0x81DF58B2, // Small 'rev32'.
3676    0x208F313E, // Large 'rev|64'.
3677    0x800049F2, // Small 'ror'.
3678    0x800B49F2, // Small 'rorv'.
3679    0x80000C53, // Small 'sbc'.
3680    0x80098C53, // Small 'sbcs'.
3681    0x81A49853, // Small 'sbfiz'.
3682    0x80069853, // Small 'sbfm'.
3683    0x800C1853, // Small 'sbfx'.
3684    0x800B2493, // Small 'sdiv'.
3685    0x1141413A, // Large 'setf|8'.
3686    0x2007413A, // Large 'setf|16'.
3687    0x800058B3, // Small 'sev'.
3688    0x800658B3, // Small 'sevl'.
3689    0x984205B3, // Small 'smaddl'.
3690    0x800C05B3, // Small 'smax'.
3691    0x80000DB3, // Small 'smc'.
3692    0x800725B3, // Small 'smin'.
3693    0x9872B9B3, // Small 'smnegl'.
3694    0x982ACDB3, // Small 'smsubl'.
3695    0x808655B3, // Small 'smulh'.
3696    0x80C655B3, // Small 'smull'.
3697    0x80010A73, // Small 'ssbb'.
3698    0x8003F693, // Small 'st2g'.
3699    0x80420693, // Small 'stadd'.
3700    0x98420693, // Small 'staddl'.
3701    0x84420693, // Small 'staddb'.
3702    0x206D50CD, // Large 'stadd|lb'.
3703    0x90420693, // Small 'staddh'.
3704    0x201550CD, // Large 'stadd|lh'.
3705    0x81260E93, // Small 'stclr'.
3706    0x99260E93, // Small 'stclrl'.
3707    0x85260E93, // Small 'stclrb'.
3708    0x206D50D2, // Large 'stclr|lb'.
3709    0x91260E93, // Small 'stclrh'.
3710    0x201550D2, // Large 'stclr|lh'.
3711    0x81279693, // Small 'steor'.
3712    0x99279693, // Small 'steorl'.
3713    0x85279693, // Small 'steorb'.
3714    0x206D50D7, // Large 'steor|lb'.
3715    0x91279693, // Small 'steorh'.
3716    0x201550D7, // Large 'steor|lh'.
3717    0x80001E93, // Small 'stg'.
3718    0x80069E93, // Small 'stgm'.
3719    0x80081E93, // Small 'stgp'.
3720    0x81263293, // Small 'stllr'.
3721    0x85263293, // Small 'stllrb'.
3722    0x91263293, // Small 'stllrh'.
3723    0x80093293, // Small 'stlr'.
3724    0x80293293, // Small 'stlrb'.
3725    0x80893293, // Small 'stlrh'.
3726    0x810C3293, // Small 'stlxp'.
3727    0x812C3293, // Small 'stlxr'.
3728    0x852C3293, // Small 'stlxrb'.
3729    0x912C3293, // Small 'stlxrh'.
3730    0x80083A93, // Small 'stnp'.
3731    0x80004293, // Small 'stp'.
3732    0x80004A93, // Small 'str'.
3733    0x80014A93, // Small 'strb'.
3734    0x80044A93, // Small 'strh'.
3735    0x8142CE93, // Small 'stset'.
3736    0x9942CE93, // Small 'stsetl'.
3737    0x8542CE93, // Small 'stsetb'.
3738    0x206D50DC, // Large 'stset|lb'.
3739    0x9142CE93, // Small 'stseth'.
3740    0x201550DC, // Large 'stset|lh'.
3741    0xB016CE93, // Small 'stsmax'.
3742    0x100E606F, // Large 'stsmax|l'.
3743    0x100D606F, // Large 'stsmax|b'.
3744    0x206D606F, // Large 'stsmax|lb'.
3745    0x1016606F, // Large 'stsmax|h'.
3746    0x2015606F, // Large 'stsmax|lh'.
3747    0x9C96CE93, // Small 'stsmin'.
3748    0x100E6075, // Large 'stsmin|l'.
3749    0x100D6075, // Large 'stsmin|b'.
3750    0x206D6075, // Large 'stsmin|lb'.
3751    0x10166075, // Large 'stsmin|h'.
3752    0x20156075, // Large 'stsmin|lh'.
3753    0x80095293, // Small 'sttr'.
3754    0x80295293, // Small 'sttrb'.
3755    0x80895293, // Small 'sttrh'.
3756    0xB016D693, // Small 'stumax'.
3757    0x100E607B, // Large 'stumax|l'.
3758    0x100D607B, // Large 'stumax|b'.
3759    0x206D607B, // Large 'stumax|lb'.
3760    0x1016607B, // Large 'stumax|h'.
3761    0x2015607B, // Large 'stumax|lh'.
3762    0x9C96D693, // Small 'stumin'.
3763    0x100E6081, // Large 'stumin|l'.
3764    0x100D6081, // Large 'stumin|b'.
3765    0x206D6081, // Large 'stumin|lb'.
3766    0x10166081, // Large 'stumin|h'.
3767    0x20156081, // Large 'stumin|lh'.
3768    0x80095693, // Small 'stur'.
3769    0x80295693, // Small 'sturb'.
3770    0x80895693, // Small 'sturh'.
3771    0x80086293, // Small 'stxp'.
3772    0x80096293, // Small 'stxr'.
3773    0x80296293, // Small 'stxrb'.
3774    0x80896293, // Small 'stxrh'.
3775    0x807EEA93, // Small 'stz2g'.
3776    0x8003EA93, // Small 'stzg'.
3777    0x80D3EA93, // Small 'stzgm'.
3778    0x80000AB3, // Small 'sub'.
3779    0x80038AB3, // Small 'subg'.
3780    0x80080AB3, // Small 'subp'.
3781    0x81380AB3, // Small 'subps'.
3782    0x80098AB3, // Small 'subs'.
3783    0x80000ED3, // Small 'svc'.
3784    0x800042F3, // Small 'swp'.
3785    0x8000C2F3, // Small 'swpa'.
3786    0x8020C2F3, // Small 'swpab'.
3787    0x8080C2F3, // Small 'swpah'.
3788    0x80C0C2F3, // Small 'swpal'.
3789    0x84C0C2F3, // Small 'swpalb'.
3790    0x90C0C2F3, // Small 'swpalh'.
3791    0x800142F3, // Small 'swpb'.
3792    0x800442F3, // Small 'swph'.
3793    0x800642F3, // Small 'swpl'.
3794    0x802642F3, // Small 'swplb'.
3795    0x808642F3, // Small 'swplh'.
3796    0x80015313, // Small 'sxtb'.
3797    0x80045313, // Small 'sxth'.
3798    0x800BD313, // Small 'sxtw'.
3799    0x80004F33, // Small 'sys'.
3800    0x80048994, // Small 'tlbi'.
3801    0x80005274, // Small 'tst'.
3802    0x800D3854, // Small 'tbnz'.
3803    0x80006854, // Small 'tbz'.
3804    0x81A49855, // Small 'ubfiz'.
3805    0x80069855, // Small 'ubfm'.
3806    0x800C1855, // Small 'ubfx'.
3807    0x80001895, // Small 'udf'.
3808    0x800B2495, // Small 'udiv'.
3809    0x984205B5, // Small 'umaddl'.
3810    0x800C05B5, // Small 'umax'.
3811    0x800725B5, // Small 'umin'.
3812    0x9872B9B5, // Small 'umnegl'.
3813    0x80C655B5, // Small 'umull'.
3814    0x808655B5, // Small 'umulh'.
3815    0x982ACDB5, // Small 'umsubl'.
3816    0x80015315, // Small 'uxtb'.
3817    0x80045315, // Small 'uxth'.
3818    0x800014D7, // Small 'wfe'.
3819    0x800024D7, // Small 'wfi'.
3820    0x8E161838, // Small 'xaflag'.
3821    0x80418618, // Small 'xpacd'.
3822    0x80918618, // Small 'xpaci'.
3823    0x208850E1, // Large 'xpacl|ri'.
3824    0x80461539, // Small 'yield'.
3825    0x80004C41, // Small 'abs'.
3826    0x80001081, // Small 'add'.
3827    0x80E41081, // Small 'addhn'.
3828    0xBAE41081, // Small 'addhn2'.
3829    0x80081081, // Small 'addp'.
3830    0x800B1081, // Small 'addv'.
3831    0x80024CA1, // Small 'aesd'.
3832    0x8002CCA1, // Small 'aese'.
3833    0x86D4CCA1, // Small 'aesimc'.
3834    0x8036CCA1, // Small 'aesmc'.
3835    0x800011C1, // Small 'and'.
3836    0x800C0462, // Small 'bcax'.
3837    0x814B0CC2, // Small 'bfcvt'.
3838    0x9D4B0CC2, // Small 'bfcvtn'.
3839    0x20B150E6, // Large 'bfcvt|n2'.
3840    0x814790C2, // Small 'bfdot'.
3841    0x206D50EB, // Large 'bfmla|lb'.
3842    0x20F050EB, // Large 'bfmla|lt'.
3843    0x82C6B4C2, // Small 'bfmmla'.
3844    0x80000D22, // Small 'bic'.
3845    0x80001922, // Small 'bif'.
3846    0x80005122, // Small 'bit'.
3847    0x80003262, // Small 'bsl'.
3848    0x80004D83, // Small 'cls'.
3849    0x80006983, // Small 'clz'.
3850    0x800895A3, // Small 'cmeq'.
3851    0x80029DA3, // Small 'cmge'.
3852    0x800A1DA3, // Small 'cmgt'.
3853    0x8004A1A3, // Small 'cmhi'.
3854    0x8009A1A3, // Small 'cmhs'.
3855    0x8002B1A3, // Small 'cmle'.
3856    0x800A31A3, // Small 'cmlt'.
3857    0x8149D1A3, // Small 'cmtst'.
3858    0x800051C3, // Small 'cnt'.
3859    0x800042A4, // Small 'dup'.
3860    0x800049E5, // Small 'eor'.
3861    0x800F49E5, // Small 'eor3'.
3862    0x80005305, // Small 'ext'.
3863    0x80020826, // Small 'fabd'.
3864    0x80098826, // Small 'fabs'.
3865    0x80538C26, // Small 'facge'.
3866    0x81438C26, // Small 'facgt'.
3867    0x80021026, // Small 'fadd'.
3868    0x81021026, // Small 'faddp'.
3869    0x80420466, // Small 'fcadd'.
3870    0x81068C66, // Small 'fccmp'.
3871    0x8B068C66, // Small 'fccmpe'.
3872    0x8112B466, // Small 'fcmeq'.
3873    0x8053B466, // Small 'fcmge'.
3874    0x8143B466, // Small 'fcmgt'.
3875    0x80163466, // Small 'fcmla'.
3876    0x80563466, // Small 'fcmle'.
3877    0x81463466, // Small 'fcmlt'.
3878    0x80083466, // Small 'fcmp'.
3879    0x80583466, // Small 'fcmpe'.
3880    0x80C2CC66, // Small 'fcsel'.
3881    0x800A5866, // Small 'fcvt'.
3882    0xA61A5866, // Small 'fcvtas'.
3883    0xAA1A5866, // Small 'fcvtau'.
3884    0x80CA5866, // Small 'fcvtl'.
3885    0xBACA5866, // Small 'fcvtl2'.
3886    0xA6DA5866, // Small 'fcvtms'.
3887    0xAADA5866, // Small 'fcvtmu'.
3888    0x80EA5866, // Small 'fcvtn'.
3889    0xBAEA5866, // Small 'fcvtn2'.
3890    0xA6EA5866, // Small 'fcvtns'.
3891    0xAAEA5866, // Small 'fcvtnu'.
3892    0xA70A5866, // Small 'fcvtps'.
3893    0xAB0A5866, // Small 'fcvtpu'.
3894    0x9D8A5866, // Small 'fcvtxn'.
3895    0x20B150F2, // Large 'fcvtx|n2'.
3896    0xA7AA5866, // Small 'fcvtzs'.
3897    0xABAA5866, // Small 'fcvtzu'.
3898    0x800B2486, // Small 'fdiv'.
3899    0x101060F7, // Large 'fjcvtz|s'.
3900    0x804205A6, // Small 'fmadd'.
3901    0x800C05A6, // Small 'fmax'.
3902    0x9AEC05A6, // Small 'fmaxnm'.
3903    0x104460FD, // Large 'fmaxnm|p'.
3904    0x10E960FD, // Large 'fmaxnm|v'.
3905    0x810C05A6, // Small 'fmaxp'.
3906    0x816C05A6, // Small 'fmaxv'.
3907    0x800725A6, // Small 'fmin'.
3908    0x9AE725A6, // Small 'fminnm'.
3909    0x10446103, // Large 'fminnm|p'.
3910    0x10E96103, // Large 'fminnm|v'.
3911    0x810725A6, // Small 'fminp'.
3912    0x816725A6, // Small 'fminv'.
3913    0x8000B1A6, // Small 'fmla'.
3914    0x80C0B1A6, // Small 'fmlal'.
3915    0xBAC0B1A6, // Small 'fmlal2'.
3916    0x8009B1A6, // Small 'fmls'.
3917    0x80C9B1A6, // Small 'fmlsl'.
3918    0xBAC9B1A6, // Small 'fmlsl2'.
3919    0x800B3DA6, // Small 'fmov'.
3920    0x802ACDA6, // Small 'fmsub'.
3921    0x800655A6, // Small 'fmul'.
3922    0x818655A6, // Small 'fmulx'.
3923    0x800395C6, // Small 'fneg'.
3924    0x8840B5C6, // Small 'fnmadd'.
3925    0x8559B5C6, // Small 'fnmsub'.
3926    0x80CAB5C6, // Small 'fnmul'.
3927    0x8B019646, // Small 'frecpe'.
3928    0xA7019646, // Small 'frecps'.
3929    0xB1019646, // Small 'frecpx'.
3930    0x10137087, // Large 'frint32|x'.
3931    0x108E7087, // Large 'frint32|z'.
3932    0x308F5087, // Large 'frint|64x'.
3933    0x30925087, // Large 'frint|64z'.
3934    0x83472646, // Small 'frinta'.
3935    0x93472646, // Small 'frinti'.
3936    0x9B472646, // Small 'frintm'.
3937    0x9D472646, // Small 'frintn'.
3938    0xA1472646, // Small 'frintp'.
3939    0xB1472646, // Small 'frintx'.
3940    0xB5472646, // Small 'frintz'.
3941    0x20D85109, // Large 'frsqr|te'.
3942    0x20705109, // Large 'frsqr|ts'.
3943    0x81494666, // Small 'fsqrt'.
3944    0x80015666, // Small 'fsub'.
3945    0x80004DC9, // Small 'ins'.
3946    0x8000708C, // Small 'ld1'.
3947    0x8009708C, // Small 'ld1r'.
3948    0x8000748C, // Small 'ld2'.
3949    0x8009748C, // Small 'ld2r'.
3950    0x8000788C, // Small 'ld3'.
3951    0x8009788C, // Small 'ld3r'.
3952    0x80007C8C, // Small 'ld4'.
3953    0x80097C8C, // Small 'ld4r'.
3954    0x8008388C, // Small 'ldnp'.
3955    0x8000408C, // Small 'ldp'.
3956    0x8000488C, // Small 'ldr'.
3957    0x8009548C, // Small 'ldur'.
3958    0x8000058D, // Small 'mla'.
3959    0x80004D8D, // Small 'mls'.
3960    0x800059ED, // Small 'mov'.
3961    0x8004D9ED, // Small 'movi'.
3962    0x800032AD, // Small 'mul'.
3963    0x80003ACD, // Small 'mvn'.
3964    0x8004BACD, // Small 'mvni'.
3965    0x80001CAE, // Small 'neg'.
3966    0x800051EE, // Small 'not'.
3967    0x80003A4F, // Small 'orn'.
3968    0x80004A4F, // Small 'orr'.
3969    0x800655B0, // Small 'pmul'.
3970    0x80C655B0, // Small 'pmull'.
3971    0xBAC655B0, // Small 'pmull2'.
3972    0x9C821032, // Small 'raddhn'.
3973    0x30B0410E, // Large 'radd|hn2'.
3974    0x800E6032, // Small 'rax1'.
3975    0x800A2452, // Small 'rbit'.
3976    0x2007313E, // Large 'rev|16'.
3977    0x81DF58B2, // Small 'rev32'.
3978    0x208F313E, // Large 'rev|64'.
3979    0x80E92272, // Small 'rshrn'.
3980    0xBAE92272, // Small 'rshrn2'.
3981    0x9C815672, // Small 'rsubhn'.
3982    0x30B04112, // Large 'rsub|hn2'.
3983    0x80008833, // Small 'saba'.
3984    0x80C08833, // Small 'sabal'.
3985    0xBAC08833, // Small 'sabal2'.
3986    0x80020833, // Small 'sabd'.
3987    0x80C20833, // Small 'sabdl'.
3988    0xBAC20833, // Small 'sabdl2'.
3989    0xA0C09033, // Small 'sadalp'.
3990    0x80C21033, // Small 'saddl'.
3991    0xBAC21033, // Small 'saddl2'.
3992    0xA0C21033, // Small 'saddlp'.
3993    0xACC21033, // Small 'saddlv'.
3994    0x81721033, // Small 'saddw'.
3995    0xBB721033, // Small 'saddw2'.
3996    0x806A5873, // Small 'scvtf'.
3997    0x800A3C93, // Small 'sdot'.
3998    0x803E0513, // Small 'sha1c'.
3999    0x808E0513, // Small 'sha1h'.
4000    0x80DE0513, // Small 'sha1m'.
4001    0x810E0513, // Small 'sha1p'.
4002    0x30354116, // Large 'sha1|su0'.
4003    0x303E4116, // Large 'sha1|su1'.
4004    0x1016602F, // Large 'sha256|h'.
4005    0x2095602F, // Large 'sha256|h2'.
4006    0x0000902F, // Large 'sha256su0'.
4007    0x1005802F, // Large 'sha256su|1'.
4008    0x10166038, // Large 'sha512|h'.
4009    0x20956038, // Large 'sha512|h2'.
4010    0x30356038, // Large 'sha512|su0'.
4011    0x303E6038, // Large 'sha512|su1'.
4012    0x80420513, // Small 'shadd'.
4013    0x80003113, // Small 'shl'.
4014    0x80063113, // Small 'shll'.
4015    0x81D63113, // Small 'shll2'.
4016    0x80074913, // Small 'shrn'.
4017    0x81D74913, // Small 'shrn2'.
4018    0x802ACD13, // Small 'shsub'.
4019    0x80002593, // Small 'sli'.
4020    0x10058041, // Large 'sm3partw|1'.
4021    0x10328041, // Large 'sm3partw|2'.
4022    0xB939F9B3, // Small 'sm3ss1'.
4023    0x1000611A, // Large 'sm3tt1|a'.
4024    0x100D611A, // Large 'sm3tt1|b'.
4025    0x2120511A, // Large 'sm3tt|2a'.
4026    0x2122511A, // Large 'sm3tt|2b'.
4027    0x8002FDB3, // Small 'sm4e'.
4028    0x00007124, // Large 'sm4ekey'.
4029    0x800C05B3, // Small 'smax'.
4030    0x810C05B3, // Small 'smaxp'.
4031    0x816C05B3, // Small 'smaxv'.
4032    0x800725B3, // Small 'smin'.
4033    0x810725B3, // Small 'sminp'.
4034    0x816725B3, // Small 'sminv'.
4035    0x80C0B1B3, // Small 'smlal'.
4036    0xBAC0B1B3, // Small 'smlal2'.
4037    0x80C9B1B3, // Small 'smlsl'.
4038    0xBAC9B1B3, // Small 'smlsl2'.
4039    0x801635B3, // Small 'smmla'.
4040    0x800B3DB3, // Small 'smov'.
4041    0x80C655B3, // Small 'smull'.
4042    0xBAC655B3, // Small 'smull2'.
4043    0x81310633, // Small 'sqabs'.
4044    0x80420633, // Small 'sqadd'.
4045    0x00007097, // Large 'sqdmlal'.
4046    0x10327097, // Large 'sqdmlal|2'.
4047    0x209E5097, // Large 'sqdml|sl'.
4048    0x309E5097, // Large 'sqdml|sl2'.
4049    0x101660A1, // Large 'sqdmul|h'.
4050    0x100E60A1, // Large 'sqdmul|l'.
4051    0x209F60A1, // Large 'sqdmul|l2'.
4052    0x8072BA33, // Small 'sqneg'.
4053    0x101670A7, // Large 'sqrdmla|h'.
4054    0x202F60A7, // Large 'sqrdml|sh'.
4055    0x30AE50A7, // Large 'sqrdm|ulh'.
4056    0x9889CA33, // Small 'sqrshl'.
4057    0x101C6049, // Large 'sqrshr|n'.
4058    0x20B16049, // Large 'sqrshr|n2'.
4059    0x00008049, // Large 'sqrshrun'.
4060    0x10328049, // Large 'sqrshrun|2'.
4061    0x80C44E33, // Small 'sqshl'.
4062    0xAAC44E33, // Small 'sqshlu'.
4063    0x9D244E33, // Small 'sqshrn'.
4064    0x20B150B3, // Large 'sqshr|n2'.
4065    0x101C60B3, // Large 'sqshru|n'.
4066    0x20B160B3, // Large 'sqshru|n2'.
4067    0x802ACE33, // Small 'sqsub'.
4068    0x80EA6233, // Small 'sqxtn'.
4069    0xBAEA6233, // Small 'sqxtn2'.
4070    0x9D5A6233, // Small 'sqxtun'.
4071    0x20B1512B, // Large 'sqxtu|n2'.
4072    0x8840A253, // Small 'srhadd'.
4073    0x80002653, // Small 'sri'.
4074    0x80C44E53, // Small 'srshl'.
4075    0x81244E53, // Small 'srshr'.
4076    0x80194E53, // Small 'srsra'.
4077    0x80062273, // Small 'sshl'.
4078    0x80C62273, // Small 'sshll'.
4079    0xBAC62273, // Small 'sshll2'.
4080    0x80092273, // Small 'sshr'.
4081    0x8000CA73, // Small 'ssra'.
4082    0x80C15673, // Small 'ssubl'.
4083    0xBAC15673, // Small 'ssubl2'.
4084    0x81715673, // Small 'ssubw'.
4085    0xBB715673, // Small 'ssubw2'.
4086    0x80007293, // Small 'st1'.
4087    0x80007693, // Small 'st2'.
4088    0x80007A93, // Small 'st3'.
4089    0x80007E93, // Small 'st4'.
4090    0x80083A93, // Small 'stnp'.
4091    0x80004293, // Small 'stp'.
4092    0x80004A93, // Small 'str'.
4093    0x80095693, // Small 'stur'.
4094    0x80000AB3, // Small 'sub'.
4095    0x80E40AB3, // Small 'subhn'.
4096    0xBAE40AB3, // Small 'subhn2'.
4097    0x814792B3, // Small 'sudot'.
4098    0x8840C6B3, // Small 'suqadd'.
4099    0x80065313, // Small 'sxtl'.
4100    0x81D65313, // Small 'sxtl2'.
4101    0x80003054, // Small 'tbl'.
4102    0x80006054, // Small 'tbx'.
4103    0x800E3A54, // Small 'trn1'.
4104    0x800EBA54, // Small 'trn2'.
4105    0x80008835, // Small 'uaba'.
4106    0x80C08835, // Small 'uabal'.
4107    0xBAC08835, // Small 'uabal2'.
4108    0x80020835, // Small 'uabd'.
4109    0x80C20835, // Small 'uabdl'.
4110    0xBAC20835, // Small 'uabdl2'.
4111    0xA0C09035, // Small 'uadalp'.
4112    0x80C21035, // Small 'uaddl'.
4113    0xBAC21035, // Small 'uaddl2'.
4114    0xA0C21035, // Small 'uaddlp'.
4115    0xACC21035, // Small 'uaddlv'.
4116    0x81721035, // Small 'uaddw'.
4117    0xBB721035, // Small 'uaddw2'.
4118    0x806A5875, // Small 'ucvtf'.
4119    0x800A3C95, // Small 'udot'.
4120    0x80420515, // Small 'uhadd'.
4121    0x802ACD15, // Small 'uhsub'.
4122    0x800C05B5, // Small 'umax'.
4123    0x810C05B5, // Small 'umaxp'.
4124    0x816C05B5, // Small 'umaxv'.
4125    0x800725B5, // Small 'umin'.
4126    0x810725B5, // Small 'uminp'.
4127    0x816725B5, // Small 'uminv'.
4128    0x80C0B1B5, // Small 'umlal'.
4129    0xBAC0B1B5, // Small 'umlal2'.
4130    0x80C9B1B5, // Small 'umlsl'.
4131    0xBAC9B1B5, // Small 'umlsl2'.
4132    0x801635B5, // Small 'ummla'.
4133    0x800B3DB5, // Small 'umov'.
4134    0x80C655B5, // Small 'umull'.
4135    0xBAC655B5, // Small 'umull2'.
4136    0x80420635, // Small 'uqadd'.
4137    0x9889CA35, // Small 'uqrshl'.
4138    0x101C60B9, // Large 'uqrshr|n'.
4139    0x20B160B9, // Large 'uqrshr|n2'.
4140    0x80C44E35, // Small 'uqshl'.
4141    0x9D244E35, // Small 'uqshrn'.
4142    0x20B15130, // Large 'uqshr|n2'.
4143    0x802ACE35, // Small 'uqsub'.
4144    0x80EA6235, // Small 'uqxtn'.
4145    0xBAEA6235, // Small 'uqxtn2'.
4146    0x8B019655, // Small 'urecpe'.
4147    0x8840A255, // Small 'urhadd'.
4148    0x80C44E55, // Small 'urshl'.
4149    0x81244E55, // Small 'urshr'.
4150    0x20D85135, // Large 'ursqr|te'.
4151    0x80194E55, // Small 'ursra'.
4152    0x81479275, // Small 'usdot'.
4153    0x80062275, // Small 'ushl'.
4154    0x80C62275, // Small 'ushll'.
4155    0xBAC62275, // Small 'ushll2'.
4156    0x80092275, // Small 'ushr'.
4157    0x82C6B675, // Small 'usmmla'.
4158    0x8840C675, // Small 'usqadd'.
4159    0x8000CA75, // Small 'usra'.
4160    0x80C15675, // Small 'usubl'.
4161    0xBAC15675, // Small 'usubl2'.
4162    0x81715675, // Small 'usubw'.
4163    0xBB715675, // Small 'usubw2'.
4164    0x80065315, // Small 'uxtl'.
4165    0x81D65315, // Small 'uxtl2'.
4166    0x800E4355, // Small 'uzp1'.
4167    0x800EC355, // Small 'uzp2'.
4168    0x80004838, // Small 'xar'.
4169    0x80003A98, // Small 'xtn'.
4170    0x800EBA98, // Small 'xtn2'.
4171    0x800E413A, // Small 'zip1'.
4172    0x800EC13A // Small 'zip2'.
4173];
4174
4175#[rustfmt::skip]
4176#[derive(Debug, Clone, Copy, PartialEq, Eq)]
4177#[allow(non_camel_case_types)]
4178#[repr(u32)]
4179pub enum InstId {
4180    None = 0, // Instruction ''.
4181    Abs, // Instruction 'abs'.
4182    Adc, // Instruction 'adc'.
4183    Adcs, // Instruction 'adcs'.
4184    Add, // Instruction 'add'.
4185    Addg, // Instruction 'addg'.
4186    Adds, // Instruction 'adds'.
4187    Adr, // Instruction 'adr'.
4188    Adrp, // Instruction 'adrp'.
4189    And, // Instruction 'and'.
4190    Ands, // Instruction 'ands'.
4191    Asr, // Instruction 'asr'.
4192    Asrv, // Instruction 'asrv'.
4193    At, // Instruction 'at'.
4194    Autda, // Instruction 'autda'.
4195    Autdza, // Instruction 'autdza'.
4196    Autdb, // Instruction 'autdb'.
4197    Autdzb, // Instruction 'autdzb'.
4198    Autia, // Instruction 'autia'.
4199    Autia1716, // Instruction 'autia1716'.
4200    Autiasp, // Instruction 'autiasp'.
4201    Autiaz, // Instruction 'autiaz'.
4202    Autib, // Instruction 'autib'.
4203    Autib1716, // Instruction 'autib1716'.
4204    Autibsp, // Instruction 'autibsp'.
4205    Autibz, // Instruction 'autibz'.
4206    Autiza, // Instruction 'autiza'.
4207    Autizb, // Instruction 'autizb'.
4208    Axflag, // Instruction 'axflag'.
4209    B, // Instruction 'b'.
4210    Bc, // Instruction 'bc'.
4211    Bfc, // Instruction 'bfc'.
4212    Bfi, // Instruction 'bfi'.
4213    Bfm, // Instruction 'bfm'.
4214    Bfxil, // Instruction 'bfxil'.
4215    Bic, // Instruction 'bic'.
4216    Bics, // Instruction 'bics'.
4217    Bl, // Instruction 'bl'.
4218    Blr, // Instruction 'blr'.
4219    Br, // Instruction 'br'.
4220    Brk, // Instruction 'brk'.
4221    Bti, // Instruction 'bti'.
4222    Cas, // Instruction 'cas'.
4223    Casa, // Instruction 'casa'.
4224    Casab, // Instruction 'casab'.
4225    Casah, // Instruction 'casah'.
4226    Casal, // Instruction 'casal'.
4227    Casalb, // Instruction 'casalb'.
4228    Casalh, // Instruction 'casalh'.
4229    Casb, // Instruction 'casb'.
4230    Cash, // Instruction 'cash'.
4231    Casl, // Instruction 'casl'.
4232    Caslb, // Instruction 'caslb'.
4233    Caslh, // Instruction 'caslh'.
4234    Casp, // Instruction 'casp'.
4235    Caspa, // Instruction 'caspa'.
4236    Caspal, // Instruction 'caspal'.
4237    Caspl, // Instruction 'caspl'.
4238    Cbnz, // Instruction 'cbnz'.
4239    Cbz, // Instruction 'cbz'.
4240    Ccmn, // Instruction 'ccmn'.
4241    Ccmp, // Instruction 'ccmp'.
4242    Cfinv, // Instruction 'cfinv'.
4243    Chkfeat, // Instruction 'chkfeat'.
4244    Cinc, // Instruction 'cinc'.
4245    Cinv, // Instruction 'cinv'.
4246    Clrbhb, // Instruction 'clrbhb'.
4247    Clrex, // Instruction 'clrex'.
4248    Cls, // Instruction 'cls'.
4249    Clz, // Instruction 'clz'.
4250    Cmn, // Instruction 'cmn'.
4251    Cmp, // Instruction 'cmp'.
4252    Cmpp, // Instruction 'cmpp'.
4253    Cneg, // Instruction 'cneg'.
4254    Cnt, // Instruction 'cnt'.
4255    Crc32b, // Instruction 'crc32b'.
4256    Crc32cb, // Instruction 'crc32cb'.
4257    Crc32ch, // Instruction 'crc32ch'.
4258    Crc32cw, // Instruction 'crc32cw'.
4259    Crc32cx, // Instruction 'crc32cx'.
4260    Crc32h, // Instruction 'crc32h'.
4261    Crc32w, // Instruction 'crc32w'.
4262    Crc32x, // Instruction 'crc32x'.
4263    Csdb, // Instruction 'csdb'.
4264    Csel, // Instruction 'csel'.
4265    Cset, // Instruction 'cset'.
4266    Csetm, // Instruction 'csetm'.
4267    Csinc, // Instruction 'csinc'.
4268    Csinv, // Instruction 'csinv'.
4269    Csneg, // Instruction 'csneg'.
4270    Ctz, // Instruction 'ctz'.
4271    Dc, // Instruction 'dc'.
4272    Dcps1, // Instruction 'dcps1'.
4273    Dcps2, // Instruction 'dcps2'.
4274    Dcps3, // Instruction 'dcps3'.
4275    Dgh, // Instruction 'dgh'.
4276    Dmb, // Instruction 'dmb'.
4277    Drps, // Instruction 'drps'.
4278    Dsb, // Instruction 'dsb'.
4279    Eon, // Instruction 'eon'.
4280    Eor, // Instruction 'eor'.
4281    Esb, // Instruction 'esb'.
4282    Extr, // Instruction 'extr'.
4283    Eret, // Instruction 'eret'.
4284    Gmi, // Instruction 'gmi'.
4285    Hint, // Instruction 'hint'.
4286    Hlt, // Instruction 'hlt'.
4287    Hvc, // Instruction 'hvc'.
4288    Ic, // Instruction 'ic'.
4289    Isb, // Instruction 'isb'.
4290    Ldadd, // Instruction 'ldadd'.
4291    Ldadda, // Instruction 'ldadda'.
4292    Ldaddab, // Instruction 'ldaddab'.
4293    Ldaddah, // Instruction 'ldaddah'.
4294    Ldaddal, // Instruction 'ldaddal'.
4295    Ldaddalb, // Instruction 'ldaddalb'.
4296    Ldaddalh, // Instruction 'ldaddalh'.
4297    Ldaddb, // Instruction 'ldaddb'.
4298    Ldaddh, // Instruction 'ldaddh'.
4299    Ldaddl, // Instruction 'ldaddl'.
4300    Ldaddlb, // Instruction 'ldaddlb'.
4301    Ldaddlh, // Instruction 'ldaddlh'.
4302    Ldar, // Instruction 'ldar'.
4303    Ldarb, // Instruction 'ldarb'.
4304    Ldarh, // Instruction 'ldarh'.
4305    Ldaxp, // Instruction 'ldaxp'.
4306    Ldaxr, // Instruction 'ldaxr'.
4307    Ldaxrb, // Instruction 'ldaxrb'.
4308    Ldaxrh, // Instruction 'ldaxrh'.
4309    Ldclr, // Instruction 'ldclr'.
4310    Ldclra, // Instruction 'ldclra'.
4311    Ldclrab, // Instruction 'ldclrab'.
4312    Ldclrah, // Instruction 'ldclrah'.
4313    Ldclral, // Instruction 'ldclral'.
4314    Ldclralb, // Instruction 'ldclralb'.
4315    Ldclralh, // Instruction 'ldclralh'.
4316    Ldclrb, // Instruction 'ldclrb'.
4317    Ldclrh, // Instruction 'ldclrh'.
4318    Ldclrl, // Instruction 'ldclrl'.
4319    Ldclrlb, // Instruction 'ldclrlb'.
4320    Ldclrlh, // Instruction 'ldclrlh'.
4321    Ldeor, // Instruction 'ldeor'.
4322    Ldeora, // Instruction 'ldeora'.
4323    Ldeorab, // Instruction 'ldeorab'.
4324    Ldeorah, // Instruction 'ldeorah'.
4325    Ldeoral, // Instruction 'ldeoral'.
4326    Ldeoralb, // Instruction 'ldeoralb'.
4327    Ldeoralh, // Instruction 'ldeoralh'.
4328    Ldeorb, // Instruction 'ldeorb'.
4329    Ldeorh, // Instruction 'ldeorh'.
4330    Ldeorl, // Instruction 'ldeorl'.
4331    Ldeorlb, // Instruction 'ldeorlb'.
4332    Ldeorlh, // Instruction 'ldeorlh'.
4333    Ldg, // Instruction 'ldg'.
4334    Ldgm, // Instruction 'ldgm'.
4335    Ldlar, // Instruction 'ldlar'.
4336    Ldlarb, // Instruction 'ldlarb'.
4337    Ldlarh, // Instruction 'ldlarh'.
4338    Ldnp, // Instruction 'ldnp'.
4339    Ldp, // Instruction 'ldp'.
4340    Ldpsw, // Instruction 'ldpsw'.
4341    Ldr, // Instruction 'ldr'.
4342    Ldraa, // Instruction 'ldraa'.
4343    Ldrab, // Instruction 'ldrab'.
4344    Ldrb, // Instruction 'ldrb'.
4345    Ldrh, // Instruction 'ldrh'.
4346    Ldrsb, // Instruction 'ldrsb'.
4347    Ldrsh, // Instruction 'ldrsh'.
4348    Ldrsw, // Instruction 'ldrsw'.
4349    Ldset, // Instruction 'ldset'.
4350    Ldseta, // Instruction 'ldseta'.
4351    Ldsetab, // Instruction 'ldsetab'.
4352    Ldsetah, // Instruction 'ldsetah'.
4353    Ldsetal, // Instruction 'ldsetal'.
4354    Ldsetalb, // Instruction 'ldsetalb'.
4355    Ldsetalh, // Instruction 'ldsetalh'.
4356    Ldsetb, // Instruction 'ldsetb'.
4357    Ldseth, // Instruction 'ldseth'.
4358    Ldsetl, // Instruction 'ldsetl'.
4359    Ldsetlb, // Instruction 'ldsetlb'.
4360    Ldsetlh, // Instruction 'ldsetlh'.
4361    Ldsmax, // Instruction 'ldsmax'.
4362    Ldsmaxa, // Instruction 'ldsmaxa'.
4363    Ldsmaxab, // Instruction 'ldsmaxab'.
4364    Ldsmaxah, // Instruction 'ldsmaxah'.
4365    Ldsmaxal, // Instruction 'ldsmaxal'.
4366    Ldsmaxalb, // Instruction 'ldsmaxalb'.
4367    Ldsmaxalh, // Instruction 'ldsmaxalh'.
4368    Ldsmaxb, // Instruction 'ldsmaxb'.
4369    Ldsmaxh, // Instruction 'ldsmaxh'.
4370    Ldsmaxl, // Instruction 'ldsmaxl'.
4371    Ldsmaxlb, // Instruction 'ldsmaxlb'.
4372    Ldsmaxlh, // Instruction 'ldsmaxlh'.
4373    Ldsmin, // Instruction 'ldsmin'.
4374    Ldsmina, // Instruction 'ldsmina'.
4375    Ldsminab, // Instruction 'ldsminab'.
4376    Ldsminah, // Instruction 'ldsminah'.
4377    Ldsminal, // Instruction 'ldsminal'.
4378    Ldsminalb, // Instruction 'ldsminalb'.
4379    Ldsminalh, // Instruction 'ldsminalh'.
4380    Ldsminb, // Instruction 'ldsminb'.
4381    Ldsminh, // Instruction 'ldsminh'.
4382    Ldsminl, // Instruction 'ldsminl'.
4383    Ldsminlb, // Instruction 'ldsminlb'.
4384    Ldsminlh, // Instruction 'ldsminlh'.
4385    Ldtr, // Instruction 'ldtr'.
4386    Ldtrb, // Instruction 'ldtrb'.
4387    Ldtrh, // Instruction 'ldtrh'.
4388    Ldtrsb, // Instruction 'ldtrsb'.
4389    Ldtrsh, // Instruction 'ldtrsh'.
4390    Ldtrsw, // Instruction 'ldtrsw'.
4391    Ldumax, // Instruction 'ldumax'.
4392    Ldumaxa, // Instruction 'ldumaxa'.
4393    Ldumaxab, // Instruction 'ldumaxab'.
4394    Ldumaxah, // Instruction 'ldumaxah'.
4395    Ldumaxal, // Instruction 'ldumaxal'.
4396    Ldumaxalb, // Instruction 'ldumaxalb'.
4397    Ldumaxalh, // Instruction 'ldumaxalh'.
4398    Ldumaxb, // Instruction 'ldumaxb'.
4399    Ldumaxh, // Instruction 'ldumaxh'.
4400    Ldumaxl, // Instruction 'ldumaxl'.
4401    Ldumaxlb, // Instruction 'ldumaxlb'.
4402    Ldumaxlh, // Instruction 'ldumaxlh'.
4403    Ldumin, // Instruction 'ldumin'.
4404    Ldumina, // Instruction 'ldumina'.
4405    Lduminab, // Instruction 'lduminab'.
4406    Lduminah, // Instruction 'lduminah'.
4407    Lduminal, // Instruction 'lduminal'.
4408    Lduminalb, // Instruction 'lduminalb'.
4409    Lduminalh, // Instruction 'lduminalh'.
4410    Lduminb, // Instruction 'lduminb'.
4411    Lduminh, // Instruction 'lduminh'.
4412    Lduminl, // Instruction 'lduminl'.
4413    Lduminlb, // Instruction 'lduminlb'.
4414    Lduminlh, // Instruction 'lduminlh'.
4415    Ldur, // Instruction 'ldur'.
4416    Ldurb, // Instruction 'ldurb'.
4417    Ldurh, // Instruction 'ldurh'.
4418    Ldursb, // Instruction 'ldursb'.
4419    Ldursh, // Instruction 'ldursh'.
4420    Ldursw, // Instruction 'ldursw'.
4421    Ldxp, // Instruction 'ldxp'.
4422    Ldxr, // Instruction 'ldxr'.
4423    Ldxrb, // Instruction 'ldxrb'.
4424    Ldxrh, // Instruction 'ldxrh'.
4425    Lsl, // Instruction 'lsl'.
4426    Lslv, // Instruction 'lslv'.
4427    Lsr, // Instruction 'lsr'.
4428    Lsrv, // Instruction 'lsrv'.
4429    Madd, // Instruction 'madd'.
4430    Mneg, // Instruction 'mneg'.
4431    Mov, // Instruction 'mov'.
4432    Movk, // Instruction 'movk'.
4433    Movn, // Instruction 'movn'.
4434    Movz, // Instruction 'movz'.
4435    Mrs, // Instruction 'mrs'.
4436    Msr, // Instruction 'msr'.
4437    Msub, // Instruction 'msub'.
4438    Mul, // Instruction 'mul'.
4439    Mvn, // Instruction 'mvn'.
4440    Neg, // Instruction 'neg'.
4441    Negs, // Instruction 'negs'.
4442    Ngc, // Instruction 'ngc'.
4443    Ngcs, // Instruction 'ngcs'.
4444    Nop, // Instruction 'nop'.
4445    Orn, // Instruction 'orn'.
4446    Orr, // Instruction 'orr'.
4447    Pacda, // Instruction 'pacda'.
4448    Pacdb, // Instruction 'pacdb'.
4449    Pacdza, // Instruction 'pacdza'.
4450    Pacdzb, // Instruction 'pacdzb'.
4451    Pacga, // Instruction 'pacga'.
4452    Prfm, // Instruction 'prfm'.
4453    Pssbb, // Instruction 'pssbb'.
4454    Rbit, // Instruction 'rbit'.
4455    Ret, // Instruction 'ret'.
4456    Rev, // Instruction 'rev'.
4457    Rev16, // Instruction 'rev16'.
4458    Rev32, // Instruction 'rev32'.
4459    Rev64, // Instruction 'rev64'.
4460    Ror, // Instruction 'ror'.
4461    Rorv, // Instruction 'rorv'.
4462    Sbc, // Instruction 'sbc'.
4463    Sbcs, // Instruction 'sbcs'.
4464    Sbfiz, // Instruction 'sbfiz'.
4465    Sbfm, // Instruction 'sbfm'.
4466    Sbfx, // Instruction 'sbfx'.
4467    Sdiv, // Instruction 'sdiv'.
4468    Setf8, // Instruction 'setf8'.
4469    Setf16, // Instruction 'setf16'.
4470    Sev, // Instruction 'sev'.
4471    Sevl, // Instruction 'sevl'.
4472    Smaddl, // Instruction 'smaddl'.
4473    Smax, // Instruction 'smax'.
4474    Smc, // Instruction 'smc'.
4475    Smin, // Instruction 'smin'.
4476    Smnegl, // Instruction 'smnegl'.
4477    Smsubl, // Instruction 'smsubl'.
4478    Smulh, // Instruction 'smulh'.
4479    Smull, // Instruction 'smull'.
4480    Ssbb, // Instruction 'ssbb'.
4481    St2g, // Instruction 'st2g'.
4482    Stadd, // Instruction 'stadd'.
4483    Staddl, // Instruction 'staddl'.
4484    Staddb, // Instruction 'staddb'.
4485    Staddlb, // Instruction 'staddlb'.
4486    Staddh, // Instruction 'staddh'.
4487    Staddlh, // Instruction 'staddlh'.
4488    Stclr, // Instruction 'stclr'.
4489    Stclrl, // Instruction 'stclrl'.
4490    Stclrb, // Instruction 'stclrb'.
4491    Stclrlb, // Instruction 'stclrlb'.
4492    Stclrh, // Instruction 'stclrh'.
4493    Stclrlh, // Instruction 'stclrlh'.
4494    Steor, // Instruction 'steor'.
4495    Steorl, // Instruction 'steorl'.
4496    Steorb, // Instruction 'steorb'.
4497    Steorlb, // Instruction 'steorlb'.
4498    Steorh, // Instruction 'steorh'.
4499    Steorlh, // Instruction 'steorlh'.
4500    Stg, // Instruction 'stg'.
4501    Stgm, // Instruction 'stgm'.
4502    Stgp, // Instruction 'stgp'.
4503    Stllr, // Instruction 'stllr'.
4504    Stllrb, // Instruction 'stllrb'.
4505    Stllrh, // Instruction 'stllrh'.
4506    Stlr, // Instruction 'stlr'.
4507    Stlrb, // Instruction 'stlrb'.
4508    Stlrh, // Instruction 'stlrh'.
4509    Stlxp, // Instruction 'stlxp'.
4510    Stlxr, // Instruction 'stlxr'.
4511    Stlxrb, // Instruction 'stlxrb'.
4512    Stlxrh, // Instruction 'stlxrh'.
4513    Stnp, // Instruction 'stnp'.
4514    Stp, // Instruction 'stp'.
4515    Str, // Instruction 'str'.
4516    Strb, // Instruction 'strb'.
4517    Strh, // Instruction 'strh'.
4518    Stset, // Instruction 'stset'.
4519    Stsetl, // Instruction 'stsetl'.
4520    Stsetb, // Instruction 'stsetb'.
4521    Stsetlb, // Instruction 'stsetlb'.
4522    Stseth, // Instruction 'stseth'.
4523    Stsetlh, // Instruction 'stsetlh'.
4524    Stsmax, // Instruction 'stsmax'.
4525    Stsmaxl, // Instruction 'stsmaxl'.
4526    Stsmaxb, // Instruction 'stsmaxb'.
4527    Stsmaxlb, // Instruction 'stsmaxlb'.
4528    Stsmaxh, // Instruction 'stsmaxh'.
4529    Stsmaxlh, // Instruction 'stsmaxlh'.
4530    Stsmin, // Instruction 'stsmin'.
4531    Stsminl, // Instruction 'stsminl'.
4532    Stsminb, // Instruction 'stsminb'.
4533    Stsminlb, // Instruction 'stsminlb'.
4534    Stsminh, // Instruction 'stsminh'.
4535    Stsminlh, // Instruction 'stsminlh'.
4536    Sttr, // Instruction 'sttr'.
4537    Sttrb, // Instruction 'sttrb'.
4538    Sttrh, // Instruction 'sttrh'.
4539    Stumax, // Instruction 'stumax'.
4540    Stumaxl, // Instruction 'stumaxl'.
4541    Stumaxb, // Instruction 'stumaxb'.
4542    Stumaxlb, // Instruction 'stumaxlb'.
4543    Stumaxh, // Instruction 'stumaxh'.
4544    Stumaxlh, // Instruction 'stumaxlh'.
4545    Stumin, // Instruction 'stumin'.
4546    Stuminl, // Instruction 'stuminl'.
4547    Stuminb, // Instruction 'stuminb'.
4548    Stuminlb, // Instruction 'stuminlb'.
4549    Stuminh, // Instruction 'stuminh'.
4550    Stuminlh, // Instruction 'stuminlh'.
4551    Stur, // Instruction 'stur'.
4552    Sturb, // Instruction 'sturb'.
4553    Sturh, // Instruction 'sturh'.
4554    Stxp, // Instruction 'stxp'.
4555    Stxr, // Instruction 'stxr'.
4556    Stxrb, // Instruction 'stxrb'.
4557    Stxrh, // Instruction 'stxrh'.
4558    Stz2g, // Instruction 'stz2g'.
4559    Stzg, // Instruction 'stzg'.
4560    Stzgm, // Instruction 'stzgm'.
4561    Sub, // Instruction 'sub'.
4562    Subg, // Instruction 'subg'.
4563    Subp, // Instruction 'subp'.
4564    Subps, // Instruction 'subps'.
4565    Subs, // Instruction 'subs'.
4566    Svc, // Instruction 'svc'.
4567    Swp, // Instruction 'swp'.
4568    Swpa, // Instruction 'swpa'.
4569    Swpab, // Instruction 'swpab'.
4570    Swpah, // Instruction 'swpah'.
4571    Swpal, // Instruction 'swpal'.
4572    Swpalb, // Instruction 'swpalb'.
4573    Swpalh, // Instruction 'swpalh'.
4574    Swpb, // Instruction 'swpb'.
4575    Swph, // Instruction 'swph'.
4576    Swpl, // Instruction 'swpl'.
4577    Swplb, // Instruction 'swplb'.
4578    Swplh, // Instruction 'swplh'.
4579    Sxtb, // Instruction 'sxtb'.
4580    Sxth, // Instruction 'sxth'.
4581    Sxtw, // Instruction 'sxtw'.
4582    Sys, // Instruction 'sys'.
4583    Tlbi, // Instruction 'tlbi'.
4584    Tst, // Instruction 'tst'.
4585    Tbnz, // Instruction 'tbnz'.
4586    Tbz, // Instruction 'tbz'.
4587    Ubfiz, // Instruction 'ubfiz'.
4588    Ubfm, // Instruction 'ubfm'.
4589    Ubfx, // Instruction 'ubfx'.
4590    Udf, // Instruction 'udf'.
4591    Udiv, // Instruction 'udiv'.
4592    Umaddl, // Instruction 'umaddl'.
4593    Umax, // Instruction 'umax'.
4594    Umin, // Instruction 'umin'.
4595    Umnegl, // Instruction 'umnegl'.
4596    Umull, // Instruction 'umull'.
4597    Umulh, // Instruction 'umulh'.
4598    Umsubl, // Instruction 'umsubl'.
4599    Uxtb, // Instruction 'uxtb'.
4600    Uxth, // Instruction 'uxth'.
4601    Wfe, // Instruction 'wfe'.
4602    Wfi, // Instruction 'wfi'.
4603    Xaflag, // Instruction 'xaflag'.
4604    Xpacd, // Instruction 'xpacd'.
4605    Xpaci, // Instruction 'xpaci'.
4606    Xpaclri, // Instruction 'xpaclri'.
4607    Yield, // Instruction 'yield'.
4608    Abs_v, // Instruction 'abs' {ASIMD}.
4609    Add_v, // Instruction 'add' {ASIMD}.
4610    Addhn_v, // Instruction 'addhn' {ASIMD}.
4611    Addhn2_v, // Instruction 'addhn2' {ASIMD}.
4612    Addp_v, // Instruction 'addp' {ASIMD}.
4613    Addv_v, // Instruction 'addv' {ASIMD}.
4614    Aesd_v, // Instruction 'aesd' {ASIMD}.
4615    Aese_v, // Instruction 'aese' {ASIMD}.
4616    Aesimc_v, // Instruction 'aesimc' {ASIMD}.
4617    Aesmc_v, // Instruction 'aesmc' {ASIMD}.
4618    And_v, // Instruction 'and' {ASIMD}.
4619    Bcax_v, // Instruction 'bcax' {ASIMD}.
4620    Bfcvt_v, // Instruction 'bfcvt' {ASIMD}.
4621    Bfcvtn_v, // Instruction 'bfcvtn' {ASIMD}.
4622    Bfcvtn2_v, // Instruction 'bfcvtn2' {ASIMD}.
4623    Bfdot_v, // Instruction 'bfdot' {ASIMD}.
4624    Bfmlalb_v, // Instruction 'bfmlalb' {ASIMD}.
4625    Bfmlalt_v, // Instruction 'bfmlalt' {ASIMD}.
4626    Bfmmla_v, // Instruction 'bfmmla' {ASIMD}.
4627    Bic_v, // Instruction 'bic' {ASIMD}.
4628    Bif_v, // Instruction 'bif' {ASIMD}.
4629    Bit_v, // Instruction 'bit' {ASIMD}.
4630    Bsl_v, // Instruction 'bsl' {ASIMD}.
4631    Cls_v, // Instruction 'cls' {ASIMD}.
4632    Clz_v, // Instruction 'clz' {ASIMD}.
4633    Cmeq_v, // Instruction 'cmeq' {ASIMD}.
4634    Cmge_v, // Instruction 'cmge' {ASIMD}.
4635    Cmgt_v, // Instruction 'cmgt' {ASIMD}.
4636    Cmhi_v, // Instruction 'cmhi' {ASIMD}.
4637    Cmhs_v, // Instruction 'cmhs' {ASIMD}.
4638    Cmle_v, // Instruction 'cmle' {ASIMD}.
4639    Cmlt_v, // Instruction 'cmlt' {ASIMD}.
4640    Cmtst_v, // Instruction 'cmtst' {ASIMD}.
4641    Cnt_v, // Instruction 'cnt' {ASIMD}.
4642    Dup_v, // Instruction 'dup' {ASIMD}.
4643    Eor_v, // Instruction 'eor' {ASIMD}.
4644    Eor3_v, // Instruction 'eor3' {ASIMD}.
4645    Ext_v, // Instruction 'ext' {ASIMD}.
4646    Fabd_v, // Instruction 'fabd' {ASIMD}.
4647    Fabs_v, // Instruction 'fabs' {ASIMD}.
4648    Facge_v, // Instruction 'facge' {ASIMD}.
4649    Facgt_v, // Instruction 'facgt' {ASIMD}.
4650    Fadd_v, // Instruction 'fadd' {ASIMD}.
4651    Faddp_v, // Instruction 'faddp' {ASIMD}.
4652    Fcadd_v, // Instruction 'fcadd' {ASIMD}.
4653    Fccmp_v, // Instruction 'fccmp' {ASIMD}.
4654    Fccmpe_v, // Instruction 'fccmpe' {ASIMD}.
4655    Fcmeq_v, // Instruction 'fcmeq' {ASIMD}.
4656    Fcmge_v, // Instruction 'fcmge' {ASIMD}.
4657    Fcmgt_v, // Instruction 'fcmgt' {ASIMD}.
4658    Fcmla_v, // Instruction 'fcmla' {ASIMD}.
4659    Fcmle_v, // Instruction 'fcmle' {ASIMD}.
4660    Fcmlt_v, // Instruction 'fcmlt' {ASIMD}.
4661    Fcmp_v, // Instruction 'fcmp' {ASIMD}.
4662    Fcmpe_v, // Instruction 'fcmpe' {ASIMD}.
4663    Fcsel_v, // Instruction 'fcsel' {ASIMD}.
4664    Fcvt_v, // Instruction 'fcvt' {ASIMD}.
4665    Fcvtas_v, // Instruction 'fcvtas' {ASIMD}.
4666    Fcvtau_v, // Instruction 'fcvtau' {ASIMD}.
4667    Fcvtl_v, // Instruction 'fcvtl' {ASIMD}.
4668    Fcvtl2_v, // Instruction 'fcvtl2' {ASIMD}.
4669    Fcvtms_v, // Instruction 'fcvtms' {ASIMD}.
4670    Fcvtmu_v, // Instruction 'fcvtmu' {ASIMD}.
4671    Fcvtn_v, // Instruction 'fcvtn' {ASIMD}.
4672    Fcvtn2_v, // Instruction 'fcvtn2' {ASIMD}.
4673    Fcvtns_v, // Instruction 'fcvtns' {ASIMD}.
4674    Fcvtnu_v, // Instruction 'fcvtnu' {ASIMD}.
4675    Fcvtps_v, // Instruction 'fcvtps' {ASIMD}.
4676    Fcvtpu_v, // Instruction 'fcvtpu' {ASIMD}.
4677    Fcvtxn_v, // Instruction 'fcvtxn' {ASIMD}.
4678    Fcvtxn2_v, // Instruction 'fcvtxn2' {ASIMD}.
4679    Fcvtzs_v, // Instruction 'fcvtzs' {ASIMD}.
4680    Fcvtzu_v, // Instruction 'fcvtzu' {ASIMD}.
4681    Fdiv_v, // Instruction 'fdiv' {ASIMD}.
4682    Fjcvtzs_v, // Instruction 'fjcvtzs' {ASIMD}.
4683    Fmadd_v, // Instruction 'fmadd' {ASIMD}.
4684    Fmax_v, // Instruction 'fmax' {ASIMD}.
4685    Fmaxnm_v, // Instruction 'fmaxnm' {ASIMD}.
4686    Fmaxnmp_v, // Instruction 'fmaxnmp' {ASIMD}.
4687    Fmaxnmv_v, // Instruction 'fmaxnmv' {ASIMD}.
4688    Fmaxp_v, // Instruction 'fmaxp' {ASIMD}.
4689    Fmaxv_v, // Instruction 'fmaxv' {ASIMD}.
4690    Fmin_v, // Instruction 'fmin' {ASIMD}.
4691    Fminnm_v, // Instruction 'fminnm' {ASIMD}.
4692    Fminnmp_v, // Instruction 'fminnmp' {ASIMD}.
4693    Fminnmv_v, // Instruction 'fminnmv' {ASIMD}.
4694    Fminp_v, // Instruction 'fminp' {ASIMD}.
4695    Fminv_v, // Instruction 'fminv' {ASIMD}.
4696    Fmla_v, // Instruction 'fmla' {ASIMD}.
4697    Fmlal_v, // Instruction 'fmlal' {ASIMD}.
4698    Fmlal2_v, // Instruction 'fmlal2' {ASIMD}.
4699    Fmls_v, // Instruction 'fmls' {ASIMD}.
4700    Fmlsl_v, // Instruction 'fmlsl' {ASIMD}.
4701    Fmlsl2_v, // Instruction 'fmlsl2' {ASIMD}.
4702    Fmov_v, // Instruction 'fmov' {ASIMD}.
4703    Fmsub_v, // Instruction 'fmsub' {ASIMD}.
4704    Fmul_v, // Instruction 'fmul' {ASIMD}.
4705    Fmulx_v, // Instruction 'fmulx' {ASIMD}.
4706    Fneg_v, // Instruction 'fneg' {ASIMD}.
4707    Fnmadd_v, // Instruction 'fnmadd' {ASIMD}.
4708    Fnmsub_v, // Instruction 'fnmsub' {ASIMD}.
4709    Fnmul_v, // Instruction 'fnmul' {ASIMD}.
4710    Frecpe_v, // Instruction 'frecpe' {ASIMD}.
4711    Frecps_v, // Instruction 'frecps' {ASIMD}.
4712    Frecpx_v, // Instruction 'frecpx' {ASIMD}.
4713    Frint32x_v, // Instruction 'frint32x' {ASIMD}.
4714    Frint32z_v, // Instruction 'frint32z' {ASIMD}.
4715    Frint64x_v, // Instruction 'frint64x' {ASIMD}.
4716    Frint64z_v, // Instruction 'frint64z' {ASIMD}.
4717    Frinta_v, // Instruction 'frinta' {ASIMD}.
4718    Frinti_v, // Instruction 'frinti' {ASIMD}.
4719    Frintm_v, // Instruction 'frintm' {ASIMD}.
4720    Frintn_v, // Instruction 'frintn' {ASIMD}.
4721    Frintp_v, // Instruction 'frintp' {ASIMD}.
4722    Frintx_v, // Instruction 'frintx' {ASIMD}.
4723    Frintz_v, // Instruction 'frintz' {ASIMD}.
4724    Frsqrte_v, // Instruction 'frsqrte' {ASIMD}.
4725    Frsqrts_v, // Instruction 'frsqrts' {ASIMD}.
4726    Fsqrt_v, // Instruction 'fsqrt' {ASIMD}.
4727    Fsub_v, // Instruction 'fsub' {ASIMD}.
4728    Ins_v, // Instruction 'ins' {ASIMD}.
4729    Ld1_v, // Instruction 'ld1' {ASIMD}.
4730    Ld1r_v, // Instruction 'ld1r' {ASIMD}.
4731    Ld2_v, // Instruction 'ld2' {ASIMD}.
4732    Ld2r_v, // Instruction 'ld2r' {ASIMD}.
4733    Ld3_v, // Instruction 'ld3' {ASIMD}.
4734    Ld3r_v, // Instruction 'ld3r' {ASIMD}.
4735    Ld4_v, // Instruction 'ld4' {ASIMD}.
4736    Ld4r_v, // Instruction 'ld4r' {ASIMD}.
4737    Ldnp_v, // Instruction 'ldnp' {ASIMD}.
4738    Ldp_v, // Instruction 'ldp' {ASIMD}.
4739    Ldr_v, // Instruction 'ldr' {ASIMD}.
4740    Ldur_v, // Instruction 'ldur' {ASIMD}.
4741    Mla_v, // Instruction 'mla' {ASIMD}.
4742    Mls_v, // Instruction 'mls' {ASIMD}.
4743    Mov_v, // Instruction 'mov' {ASIMD}.
4744    Movi_v, // Instruction 'movi' {ASIMD}.
4745    Mul_v, // Instruction 'mul' {ASIMD}.
4746    Mvn_v, // Instruction 'mvn' {ASIMD}.
4747    Mvni_v, // Instruction 'mvni' {ASIMD}.
4748    Neg_v, // Instruction 'neg' {ASIMD}.
4749    Not_v, // Instruction 'not' {ASIMD}.
4750    Orn_v, // Instruction 'orn' {ASIMD}.
4751    Orr_v, // Instruction 'orr' {ASIMD}.
4752    Pmul_v, // Instruction 'pmul' {ASIMD}.
4753    Pmull_v, // Instruction 'pmull' {ASIMD}.
4754    Pmull2_v, // Instruction 'pmull2' {ASIMD}.
4755    Raddhn_v, // Instruction 'raddhn' {ASIMD}.
4756    Raddhn2_v, // Instruction 'raddhn2' {ASIMD}.
4757    Rax1_v, // Instruction 'rax1' {ASIMD}.
4758    Rbit_v, // Instruction 'rbit' {ASIMD}.
4759    Rev16_v, // Instruction 'rev16' {ASIMD}.
4760    Rev32_v, // Instruction 'rev32' {ASIMD}.
4761    Rev64_v, // Instruction 'rev64' {ASIMD}.
4762    Rshrn_v, // Instruction 'rshrn' {ASIMD}.
4763    Rshrn2_v, // Instruction 'rshrn2' {ASIMD}.
4764    Rsubhn_v, // Instruction 'rsubhn' {ASIMD}.
4765    Rsubhn2_v, // Instruction 'rsubhn2' {ASIMD}.
4766    Saba_v, // Instruction 'saba' {ASIMD}.
4767    Sabal_v, // Instruction 'sabal' {ASIMD}.
4768    Sabal2_v, // Instruction 'sabal2' {ASIMD}.
4769    Sabd_v, // Instruction 'sabd' {ASIMD}.
4770    Sabdl_v, // Instruction 'sabdl' {ASIMD}.
4771    Sabdl2_v, // Instruction 'sabdl2' {ASIMD}.
4772    Sadalp_v, // Instruction 'sadalp' {ASIMD}.
4773    Saddl_v, // Instruction 'saddl' {ASIMD}.
4774    Saddl2_v, // Instruction 'saddl2' {ASIMD}.
4775    Saddlp_v, // Instruction 'saddlp' {ASIMD}.
4776    Saddlv_v, // Instruction 'saddlv' {ASIMD}.
4777    Saddw_v, // Instruction 'saddw' {ASIMD}.
4778    Saddw2_v, // Instruction 'saddw2' {ASIMD}.
4779    Scvtf_v, // Instruction 'scvtf' {ASIMD}.
4780    Sdot_v, // Instruction 'sdot' {ASIMD}.
4781    Sha1c_v, // Instruction 'sha1c' {ASIMD}.
4782    Sha1h_v, // Instruction 'sha1h' {ASIMD}.
4783    Sha1m_v, // Instruction 'sha1m' {ASIMD}.
4784    Sha1p_v, // Instruction 'sha1p' {ASIMD}.
4785    Sha1su0_v, // Instruction 'sha1su0' {ASIMD}.
4786    Sha1su1_v, // Instruction 'sha1su1' {ASIMD}.
4787    Sha256h_v, // Instruction 'sha256h' {ASIMD}.
4788    Sha256h2_v, // Instruction 'sha256h2' {ASIMD}.
4789    Sha256su0_v, // Instruction 'sha256su0' {ASIMD}.
4790    Sha256su1_v, // Instruction 'sha256su1' {ASIMD}.
4791    Sha512h_v, // Instruction 'sha512h' {ASIMD}.
4792    Sha512h2_v, // Instruction 'sha512h2' {ASIMD}.
4793    Sha512su0_v, // Instruction 'sha512su0' {ASIMD}.
4794    Sha512su1_v, // Instruction 'sha512su1' {ASIMD}.
4795    Shadd_v, // Instruction 'shadd' {ASIMD}.
4796    Shl_v, // Instruction 'shl' {ASIMD}.
4797    Shll_v, // Instruction 'shll' {ASIMD}.
4798    Shll2_v, // Instruction 'shll2' {ASIMD}.
4799    Shrn_v, // Instruction 'shrn' {ASIMD}.
4800    Shrn2_v, // Instruction 'shrn2' {ASIMD}.
4801    Shsub_v, // Instruction 'shsub' {ASIMD}.
4802    Sli_v, // Instruction 'sli' {ASIMD}.
4803    Sm3partw1_v, // Instruction 'sm3partw1' {ASIMD}.
4804    Sm3partw2_v, // Instruction 'sm3partw2' {ASIMD}.
4805    Sm3ss1_v, // Instruction 'sm3ss1' {ASIMD}.
4806    Sm3tt1a_v, // Instruction 'sm3tt1a' {ASIMD}.
4807    Sm3tt1b_v, // Instruction 'sm3tt1b' {ASIMD}.
4808    Sm3tt2a_v, // Instruction 'sm3tt2a' {ASIMD}.
4809    Sm3tt2b_v, // Instruction 'sm3tt2b' {ASIMD}.
4810    Sm4e_v, // Instruction 'sm4e' {ASIMD}.
4811    Sm4ekey_v, // Instruction 'sm4ekey' {ASIMD}.
4812    Smax_v, // Instruction 'smax' {ASIMD}.
4813    Smaxp_v, // Instruction 'smaxp' {ASIMD}.
4814    Smaxv_v, // Instruction 'smaxv' {ASIMD}.
4815    Smin_v, // Instruction 'smin' {ASIMD}.
4816    Sminp_v, // Instruction 'sminp' {ASIMD}.
4817    Sminv_v, // Instruction 'sminv' {ASIMD}.
4818    Smlal_v, // Instruction 'smlal' {ASIMD}.
4819    Smlal2_v, // Instruction 'smlal2' {ASIMD}.
4820    Smlsl_v, // Instruction 'smlsl' {ASIMD}.
4821    Smlsl2_v, // Instruction 'smlsl2' {ASIMD}.
4822    Smmla_v, // Instruction 'smmla' {ASIMD}.
4823    Smov_v, // Instruction 'smov' {ASIMD}.
4824    Smull_v, // Instruction 'smull' {ASIMD}.
4825    Smull2_v, // Instruction 'smull2' {ASIMD}.
4826    Sqabs_v, // Instruction 'sqabs' {ASIMD}.
4827    Sqadd_v, // Instruction 'sqadd' {ASIMD}.
4828    Sqdmlal_v, // Instruction 'sqdmlal' {ASIMD}.
4829    Sqdmlal2_v, // Instruction 'sqdmlal2' {ASIMD}.
4830    Sqdmlsl_v, // Instruction 'sqdmlsl' {ASIMD}.
4831    Sqdmlsl2_v, // Instruction 'sqdmlsl2' {ASIMD}.
4832    Sqdmulh_v, // Instruction 'sqdmulh' {ASIMD}.
4833    Sqdmull_v, // Instruction 'sqdmull' {ASIMD}.
4834    Sqdmull2_v, // Instruction 'sqdmull2' {ASIMD}.
4835    Sqneg_v, // Instruction 'sqneg' {ASIMD}.
4836    Sqrdmlah_v, // Instruction 'sqrdmlah' {ASIMD}.
4837    Sqrdmlsh_v, // Instruction 'sqrdmlsh' {ASIMD}.
4838    Sqrdmulh_v, // Instruction 'sqrdmulh' {ASIMD}.
4839    Sqrshl_v, // Instruction 'sqrshl' {ASIMD}.
4840    Sqrshrn_v, // Instruction 'sqrshrn' {ASIMD}.
4841    Sqrshrn2_v, // Instruction 'sqrshrn2' {ASIMD}.
4842    Sqrshrun_v, // Instruction 'sqrshrun' {ASIMD}.
4843    Sqrshrun2_v, // Instruction 'sqrshrun2' {ASIMD}.
4844    Sqshl_v, // Instruction 'sqshl' {ASIMD}.
4845    Sqshlu_v, // Instruction 'sqshlu' {ASIMD}.
4846    Sqshrn_v, // Instruction 'sqshrn' {ASIMD}.
4847    Sqshrn2_v, // Instruction 'sqshrn2' {ASIMD}.
4848    Sqshrun_v, // Instruction 'sqshrun' {ASIMD}.
4849    Sqshrun2_v, // Instruction 'sqshrun2' {ASIMD}.
4850    Sqsub_v, // Instruction 'sqsub' {ASIMD}.
4851    Sqxtn_v, // Instruction 'sqxtn' {ASIMD}.
4852    Sqxtn2_v, // Instruction 'sqxtn2' {ASIMD}.
4853    Sqxtun_v, // Instruction 'sqxtun' {ASIMD}.
4854    Sqxtun2_v, // Instruction 'sqxtun2' {ASIMD}.
4855    Srhadd_v, // Instruction 'srhadd' {ASIMD}.
4856    Sri_v, // Instruction 'sri' {ASIMD}.
4857    Srshl_v, // Instruction 'srshl' {ASIMD}.
4858    Srshr_v, // Instruction 'srshr' {ASIMD}.
4859    Srsra_v, // Instruction 'srsra' {ASIMD}.
4860    Sshl_v, // Instruction 'sshl' {ASIMD}.
4861    Sshll_v, // Instruction 'sshll' {ASIMD}.
4862    Sshll2_v, // Instruction 'sshll2' {ASIMD}.
4863    Sshr_v, // Instruction 'sshr' {ASIMD}.
4864    Ssra_v, // Instruction 'ssra' {ASIMD}.
4865    Ssubl_v, // Instruction 'ssubl' {ASIMD}.
4866    Ssubl2_v, // Instruction 'ssubl2' {ASIMD}.
4867    Ssubw_v, // Instruction 'ssubw' {ASIMD}.
4868    Ssubw2_v, // Instruction 'ssubw2' {ASIMD}.
4869    St1_v, // Instruction 'st1' {ASIMD}.
4870    St2_v, // Instruction 'st2' {ASIMD}.
4871    St3_v, // Instruction 'st3' {ASIMD}.
4872    St4_v, // Instruction 'st4' {ASIMD}.
4873    Stnp_v, // Instruction 'stnp' {ASIMD}.
4874    Stp_v, // Instruction 'stp' {ASIMD}.
4875    Str_v, // Instruction 'str' {ASIMD}.
4876    Stur_v, // Instruction 'stur' {ASIMD}.
4877    Sub_v, // Instruction 'sub' {ASIMD}.
4878    Subhn_v, // Instruction 'subhn' {ASIMD}.
4879    Subhn2_v, // Instruction 'subhn2' {ASIMD}.
4880    Sudot_v, // Instruction 'sudot' {ASIMD}.
4881    Suqadd_v, // Instruction 'suqadd' {ASIMD}.
4882    Sxtl_v, // Instruction 'sxtl' {ASIMD}.
4883    Sxtl2_v, // Instruction 'sxtl2' {ASIMD}.
4884    Tbl_v, // Instruction 'tbl' {ASIMD}.
4885    Tbx_v, // Instruction 'tbx' {ASIMD}.
4886    Trn1_v, // Instruction 'trn1' {ASIMD}.
4887    Trn2_v, // Instruction 'trn2' {ASIMD}.
4888    Uaba_v, // Instruction 'uaba' {ASIMD}.
4889    Uabal_v, // Instruction 'uabal' {ASIMD}.
4890    Uabal2_v, // Instruction 'uabal2' {ASIMD}.
4891    Uabd_v, // Instruction 'uabd' {ASIMD}.
4892    Uabdl_v, // Instruction 'uabdl' {ASIMD}.
4893    Uabdl2_v, // Instruction 'uabdl2' {ASIMD}.
4894    Uadalp_v, // Instruction 'uadalp' {ASIMD}.
4895    Uaddl_v, // Instruction 'uaddl' {ASIMD}.
4896    Uaddl2_v, // Instruction 'uaddl2' {ASIMD}.
4897    Uaddlp_v, // Instruction 'uaddlp' {ASIMD}.
4898    Uaddlv_v, // Instruction 'uaddlv' {ASIMD}.
4899    Uaddw_v, // Instruction 'uaddw' {ASIMD}.
4900    Uaddw2_v, // Instruction 'uaddw2' {ASIMD}.
4901    Ucvtf_v, // Instruction 'ucvtf' {ASIMD}.
4902    Udot_v, // Instruction 'udot' {ASIMD}.
4903    Uhadd_v, // Instruction 'uhadd' {ASIMD}.
4904    Uhsub_v, // Instruction 'uhsub' {ASIMD}.
4905    Umax_v, // Instruction 'umax' {ASIMD}.
4906    Umaxp_v, // Instruction 'umaxp' {ASIMD}.
4907    Umaxv_v, // Instruction 'umaxv' {ASIMD}.
4908    Umin_v, // Instruction 'umin' {ASIMD}.
4909    Uminp_v, // Instruction 'uminp' {ASIMD}.
4910    Uminv_v, // Instruction 'uminv' {ASIMD}.
4911    Umlal_v, // Instruction 'umlal' {ASIMD}.
4912    Umlal2_v, // Instruction 'umlal2' {ASIMD}.
4913    Umlsl_v, // Instruction 'umlsl' {ASIMD}.
4914    Umlsl2_v, // Instruction 'umlsl2' {ASIMD}.
4915    Ummla_v, // Instruction 'ummla' {ASIMD}.
4916    Umov_v, // Instruction 'umov' {ASIMD}.
4917    Umull_v, // Instruction 'umull' {ASIMD}.
4918    Umull2_v, // Instruction 'umull2' {ASIMD}.
4919    Uqadd_v, // Instruction 'uqadd' {ASIMD}.
4920    Uqrshl_v, // Instruction 'uqrshl' {ASIMD}.
4921    Uqrshrn_v, // Instruction 'uqrshrn' {ASIMD}.
4922    Uqrshrn2_v, // Instruction 'uqrshrn2' {ASIMD}.
4923    Uqshl_v, // Instruction 'uqshl' {ASIMD}.
4924    Uqshrn_v, // Instruction 'uqshrn' {ASIMD}.
4925    Uqshrn2_v, // Instruction 'uqshrn2' {ASIMD}.
4926    Uqsub_v, // Instruction 'uqsub' {ASIMD}.
4927    Uqxtn_v, // Instruction 'uqxtn' {ASIMD}.
4928    Uqxtn2_v, // Instruction 'uqxtn2' {ASIMD}.
4929    Urecpe_v, // Instruction 'urecpe' {ASIMD}.
4930    Urhadd_v, // Instruction 'urhadd' {ASIMD}.
4931    Urshl_v, // Instruction 'urshl' {ASIMD}.
4932    Urshr_v, // Instruction 'urshr' {ASIMD}.
4933    Ursqrte_v, // Instruction 'ursqrte' {ASIMD}.
4934    Ursra_v, // Instruction 'ursra' {ASIMD}.
4935    Usdot_v, // Instruction 'usdot' {ASIMD}.
4936    Ushl_v, // Instruction 'ushl' {ASIMD}.
4937    Ushll_v, // Instruction 'ushll' {ASIMD}.
4938    Ushll2_v, // Instruction 'ushll2' {ASIMD}.
4939    Ushr_v, // Instruction 'ushr' {ASIMD}.
4940    Usmmla_v, // Instruction 'usmmla' {ASIMD}.
4941    Usqadd_v, // Instruction 'usqadd' {ASIMD}.
4942    Usra_v, // Instruction 'usra' {ASIMD}.
4943    Usubl_v, // Instruction 'usubl' {ASIMD}.
4944    Usubl2_v, // Instruction 'usubl2' {ASIMD}.
4945    Usubw_v, // Instruction 'usubw' {ASIMD}.
4946    Usubw2_v, // Instruction 'usubw2' {ASIMD}.
4947    Uxtl_v, // Instruction 'uxtl' {ASIMD}.
4948    Uxtl2_v, // Instruction 'uxtl2' {ASIMD}.
4949    Uzp1_v, // Instruction 'uzp1' {ASIMD}.
4950    Uzp2_v, // Instruction 'uzp2' {ASIMD}.
4951    Xar_v, // Instruction 'xar' {ASIMD}.
4952    Xtn_v, // Instruction 'xtn' {ASIMD}.
4953    Xtn2_v, // Instruction 'xtn2' {ASIMD}.
4954    Zip1_v, // Instruction 'zip1' {ASIMD}.
4955    Zip2_v, // Instruction 'zip2' {ASIMD}.
4956    _Count
4957}