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asmkit/aarch64/
emit.rs

1//! Top-level emit path: InstInfo lookup, signature validation, operand
2//! analysis, and dispatch to the emit handlers.
3//!
4//! The [`Handler`] enum dispatches per encoding: the encoding arms (a `match`
5//! on [`Encoding`]) validate operands and compose the opcode in
6//! [`A64EmitState`], while the actual word emission is done by the handlers
7//! in [`super::encoder`].
8//!
9//! Derived from AsmJit (Zlib license): this file is an altered version; see LICENSE notices.
10
11#![allow(clippy::eq_op, clippy::erasing_op, dead_code, unused)]
12use crate::AsmError;
13use crate::aarch64::encoder::*;
14use crate::aarch64::encoder_tables::*;
15use crate::aarch64::operands::*;
16use crate::aarch64::{Assembler, Gp, Reg, ShiftOp, instdb::*};
17use crate::core::arch_traits::Arch;
18use crate::core::buffer::CodeBuffer;
19use crate::core::buffer::{Constant, LabelUse, Reloc, RelocDistance, RelocTarget};
20use crate::core::globals::CondCode;
21use crate::core::operand::*;
22
23macro_rules! B {
24    ($e: expr) => {
25        1 << $e
26    };
27}
28
29macro_rules! check_signature {
30    ($op0: expr, $op1: expr) => {
31        $op0.signature() == $op1.signature()
32    };
33    ($op0: expr, $op1: expr, $op2: expr) => {
34        $op0.signature() == $op1.signature() && $op1.signature() == $op2.signature()
35    };
36
37    ($op0: expr, $op1: expr, $op2: expr, $op3: expr) => {
38        $op0.signature() == $op1.signature()
39            && $op1.signature() == $op2.signature()
40            && $op2.signature() == $op3.signature()
41    };
42}
43
44macro_rules! enc_ops {
45    ($op0: ident) => {
46        OperandType::$op0 as u32
47    };
48
49    ($op0: ident, $op1: ident) => {
50        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3
51    };
52    ($op0: ident, $op1: ident, $op2: ident) => {
53        OperandType::$op0 as u32 | (OperandType::$op1 as u32) << 3 | (OperandType::$op2 as u32) << 6
54    };
55    ($op0: ident, $op1: ident, $op2: ident, $op3: ident) => {
56        OperandType::$op0 as u32
57            | (OperandType::$op1 as u32) << 3
58            | (OperandType::$op2 as u32) << 6
59            | (OperandType::$op3 as u32) << 9
60    };
61}
62
63/// Emit handler selected by an encoding arm (AsmJit's `goto EmitXxx` labels).
64#[derive(Clone, Copy, PartialEq, Eq, Debug)]
65pub(crate) enum Handler {
66    /// `EmitOp`: write the composed opcode word.
67    Op,
68    /// `EmitOp_DispImm`: pack the displacement immediate, then `EmitOp`.
69    OpDispImm,
70    /// `EmitOp_Rel`: resolve a label/immediate pc-relative operand, then
71    /// `EmitOp_DispImm`. Falls through when `rm_rel` is not relative.
72    OpRel,
73    /// Multi-word emission (mov sequences in `multiple_op_data`).
74    Multi,
75}
76
77impl<'a> Assembler<'a> {
78    /// Validates the instruction's operand signature, composes the opcode,
79    /// and dispatches to the emit handlers. Errors are recorded in
80    /// `last_error`.
81    pub(crate) fn _emit(&mut self, id: u32, ops: &[&Operand]) {
82        if id & !(InstId::REAL_ID | InstId::ARM_COND) != 0 {
83            self.last_error = Some(AsmError::InvalidInstruction);
84            return;
85        }
86
87        let inst_cc = InstId::extract_cc(id);
88        let inst_id = InstId::extract_real_id(id);
89
90        if inst_id == InstId::None as u32 || inst_id >= InstId::_Count as u32 {
91            self.last_error = Some(AsmError::InvalidInstruction);
92            return;
93        }
94
95        let inst_info = &INST_INFO_TABLE[inst_id as usize];
96        let mut encoding_index = inst_info.encoding_data_index as usize;
97
98        let mut st = A64EmitState::new();
99
100        let isign4;
101        let inst_flags;
102
103        const NOREG: &Operand = &Operand::new();
104
105        let op0 = *ops.get(0).unwrap_or(&NOREG);
106        let op1 = *ops.get(1).unwrap_or(&NOREG);
107        let op2 = *ops.get(2).unwrap_or(&NOREG);
108        let op3 = *ops.get(3).unwrap_or(&NOREG);
109        let op4 = *ops.get(4).unwrap_or(&NOREG);
110        let op5 = *ops.get(5).unwrap_or(&NOREG);
111
112        isign4 = op0.op_type() as u32
113            + ((op1.op_type() as u32) << 3)
114            + ((op2.op_type() as u32) << 6)
115            + ((op3.op_type() as u32) << 9);
116        inst_flags = inst_info.flags;
117
118        macro_rules! check_features {
119            () => {{
120                let (required, context) =
121                    required_features_for_form(inst_id as usize, st.opcode.get(), ops);
122                if !self.environment().supports_aarch64_features(required) {
123                    self.last_error = Some(AsmError::MissingCpuFeature { feature: context });
124                    return;
125                }
126            }};
127        }
128
129        macro_rules! emit_op {
130            () => {{
131                check_features!();
132                self.emit_handler(Handler::Op, &mut st);
133                return;
134            }};
135        }
136
137        macro_rules! emit_disp_imm {
138            () => {{
139                check_features!();
140                self.emit_handler(Handler::OpDispImm, &mut st);
141                return;
142            }};
143        }
144
145        macro_rules! emit_rel {
146            () => {{
147                check_features!();
148                if self.emit_handler(Handler::OpRel, &mut st) {
149                    return;
150                }
151            }};
152        }
153
154        macro_rules! emit_rd0 {
155            () => {
156                st.opcode.add_reg(op0.id(), 0);
157                emit_op!();
158            };
159        }
160
161        macro_rules! emit_rn5 {
162            () => {
163                st.opcode.add_reg(op0.id(), 5);
164                emit_op!();
165            };
166        }
167
168        macro_rules! emit_rn5_rm16 {
169            () => {
170                st.opcode.add_reg(op0.id(), 5);
171                st.opcode.add_reg(op1.id(), 16);
172                emit_op!();
173            };
174        }
175
176        macro_rules! emit_rd0_rn5 {
177            () => {
178                st.opcode.add_reg(op0.id(), 0);
179                st.opcode.add_reg(op1.id(), 5);
180                emit_op!();
181            };
182        }
183
184        macro_rules! emit_rd0_rn5_rm16_ra10 {
185            () => {
186                st.opcode.add_reg(op0.id(), 0);
187                st.opcode.add_reg(op1.id(), 5);
188                st.opcode.add_reg(op2.id(), 16);
189                st.opcode.add_reg(op3.id(), 10);
190                emit_op!();
191            };
192        }
193
194        macro_rules! emit_rd0_rn5_rm16 {
195            () => {
196                st.opcode.add_reg(op0.id(), 0);
197                st.opcode.add_reg(op1.id(), 5);
198                st.opcode.add_reg(op2.id(), 16);
199                emit_op!();
200            };
201        }
202
203        macro_rules! emit_mem_base_rn5 {
204            () => {
205                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
206                emit_op!();
207            };
208        }
209
210        macro_rules! emit_mem_base_index_rn5_rm16 {
211            () => {
212                st.opcode.add_reg(op0.as_::<Mem>().base_id(), 5);
213                st.opcode.add_reg(op0.as_::<Mem>().index_id(), 16);
214                emit_op!();
215            };
216        }
217
218        macro_rules! emit_mem_base_no_imm_rn5 {
219            () => {
220                st.opcode.add_reg(st.rm_rel.as_::<Mem>().base_id(), 5);
221                emit_op!();
222            };
223        }
224
225        let mut encoding = match Encoding::try_from(inst_info.encoding) {
226            Ok(encoding) => encoding,
227            Err(()) => unreachable!("instdb encoding index is always a valid Encoding"),
228        };
229
230        macro_rules! simd_insn {
231            () => {
232                if isign4 == enc_ops!(Reg, Reg) && op0.as_::<Reg>().is_vec128() {
233                    if !op0.as_::<Vec>().has_element_index() {
234                        self.last_error = Some(AsmError::InvalidInstruction);
235                        return;
236                    }
237                    let element_type = op0.as_::<Vec>().element_type() as u32;
238                    let dst_index = op0.as_::<Vec>().element_index();
239                    let lsb_index = element_type - 1;
240                    let imm5 = ((dst_index << 1) | 1) << lsb_index;
241                    if imm5 > 31 {
242                        self.last_error = Some(AsmError::InvalidOperand);
243                        return;
244                    }
245                    if op1.as_::<Reg>().is_gp() {
246                        // INS - Vec[N] <- GP register.
247                        st.opcode.reset(0b0100111000000000000111 << 10);
248                        st.opcode.add_imm(imm5, 16);
249                        emit_rd0_rn5!();
250                        return;
251                    } else if op1.as_::<Reg>().is_vec128() && op1.as_::<Vec>().has_element_index() {
252                        // INS - Vec[N] <- Vec[M].
253                        if op0.as_::<Vec>().element_type() != op1.as_::<Vec>().element_type() {
254                            self.last_error = Some(AsmError::InvalidInstruction);
255                            return;
256                        }
257                        let src_index = op1.as_::<Vec>().element_index();
258                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type() {
259                            self.last_error = Some(AsmError::InvalidInstruction);
260                            return;
261                        }
262                        let imm4 = src_index << lsb_index;
263                        if imm4 > 15 {
264                            self.last_error = Some(AsmError::InvalidOperand);
265                            return;
266                        }
267                        st.opcode.reset(0b0110111000000000000001 << 10);
268                        st.opcode.add_imm(imm5, 16);
269                        st.opcode.add_imm(imm4, 11);
270                        emit_rd0_rn5!();
271                        return;
272                    }
273                }
274            };
275        }
276
277        macro_rules! simd_dup {
278            () => {
279                if isign4 == enc_ops!(Reg, Reg) {
280                    let k_valid_encodings = B!(VecElementType::B as u32 + 0)
281                        | B!(VecElementType::H as u32 + 0)
282                        | B!(VecElementType::S as u32 + 0)
283                        | B!(VecElementType::B as u32 + 8)
284                        | B!(VecElementType::H as u32 + 8)
285                        | B!(VecElementType::S as u32 + 8)
286                        | B!(VecElementType::D as u32 + 8);
287
288                    let q =
289                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
290
291                    if op1.as_::<Reg>().is_gp() {
292                        let element_type = op0.as_::<Vec>().element_type() as u32;
293                        if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
294                            self.last_error = Some(AsmError::InvalidInstruction);
295                            return;
296                        }
297
298                        let lsb_index = element_type - 1;
299                        let imm5 = 1u32 << lsb_index;
300
301                        st.opcode.reset(0b0000111000000000000011 << 10);
302                        st.opcode.add_imm(q, 30);
303                        st.opcode.add_imm(imm5, 16);
304                        emit_rd0_rn5!();
305                    } else if !op1.as_::<Reg>().is_vec() || !op1.as_::<Vec>().has_element_index() {
306                        self.last_error = Some(AsmError::InvalidInstruction);
307                        return;
308                    } else {
309                        let dst_index = op1.as_::<Vec>().element_index();
310                        if !op0.as_::<Vec>().has_element_type() {
311                            let lsb_index = (op0.as_::<Reg>().reg_type() as u32)
312                                .wrapping_sub(RegType::Vec8 as u32);
313                            if lsb_index
314                                != op1.as_::<Vec>().element_type() as u32 - VecElementType::B as u32
315                                || lsb_index > 3
316                            {
317                                self.last_error = Some(AsmError::InvalidInstruction);
318                                return;
319                            }
320
321                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
322                            if imm5 > 31 {
323                                self.last_error = Some(AsmError::InvalidOperand);
324                                return;
325                            }
326
327                            st.opcode.reset(0b0101111000000000000001 << 10);
328                            st.opcode.add_imm(imm5, 16);
329                            emit_rd0_rn5!();
330                        } else {
331                            let element_type = op0.as_::<Vec>().element_type() as u32;
332                            if q > 1 || !bit_test(k_valid_encodings, (q << 3) | element_type) {
333                                self.last_error = Some(AsmError::InvalidInstruction);
334                                return;
335                            }
336
337                            let lsb_index = element_type - 1;
338                            let imm5 = ((dst_index << 1) | 1u32) << lsb_index;
339                            if imm5 > 31 {
340                                self.last_error = Some(AsmError::InvalidOperand);
341                                return;
342                            }
343
344                            st.opcode.reset(0b0000111000000000000001 << 10);
345                            st.opcode.add_imm(q, 30);
346                            st.opcode.add_imm(imm5, 16);
347                            emit_rd0_rn5!();
348                        }
349                    }
350                }
351            };
352        }
353
354        macro_rules! simd_umov {
355            () => {
356                let op_data = &SIMD_SMOV_UMOV[encoding_index];
357                if isign4 == enc_ops!(Reg, Reg)
358                    && op0.as_::<Reg>().is_gp()
359                    && op1.as_::<Reg>().is_vec()
360                {
361                    let size_op = element_type_to_size_op(
362                        op_data.vec_op_type,
363                        op1.as_::<Reg>().reg_type(),
364                        op1.as_::<Vec>().element_type(),
365                    );
366                    if !size_op.is_valid() {
367                        self.last_error = Some(AsmError::InvalidInstruction);
368                        return;
369                    }
370                    if !op1.as_::<Vec>().has_element_index() {
371                        self.last_error = Some(AsmError::InvalidInstruction);
372                        return;
373                    }
374                    let x = op0.as_::<Gp>().is_gp64() as u32;
375                    let gp_must_be_x = (size_op.size() >= 3u32 - op_data.is_signed as u32) as u32;
376                    if op_data.is_signed != 0 {
377                        if gp_must_be_x != 0 && x == 0 {
378                            self.last_error = Some(AsmError::InvalidInstruction);
379                            return;
380                        }
381                    } else {
382                        if x != gp_must_be_x {
383                            self.last_error = Some(AsmError::InvalidInstruction);
384                            return;
385                        }
386                    }
387                    let element_index = op1.as_::<Vec>().element_index();
388                    let max_element_index = 15u32 >> size_op.size();
389                    if element_index > max_element_index {
390                        self.last_error = Some(AsmError::InvalidOperand);
391                        return;
392                    }
393                    let imm5 = (1u32 | (element_index << 1)) << size_op.size();
394                    st.opcode.reset((op_data.opcode as u32) << 10);
395                    st.opcode.add_imm(x, 30);
396                    st.opcode.add_imm(imm5, 16);
397                    emit_rd0_rn5!();
398                    return;
399                }
400            };
401        }
402
403        match encoding {
404            Encoding::BaseOp => {
405                let op_data = &BASE_OP[encoding_index];
406                if isign4 == 0 {
407                    st.opcode.reset(op_data.opcode);
408                    emit_op!();
409                }
410            }
411
412            Encoding::BaseOpX16 => {
413                let op_data = &BASE_OP_X16[encoding_index];
414                if isign4 == enc_ops!(Reg) && op0.as_::<Reg>().is_gp64() && op0.id() == 16 {
415                    st.opcode.reset(op_data.opcode);
416                    emit_op!();
417                }
418            }
419
420            Encoding::BaseOpImm => {
421                let op_data = &BASE_OP_IMM[encoding_index];
422                if isign4 == enc_ops!(Imm) {
423                    let imm = op0.as_::<Imm>().value() as u64;
424                    let imm_max = 1u64 << op_data.imm_bits as u32;
425                    if imm >= imm_max {
426                        self.last_error = Some(AsmError::TooLarge);
427                        return;
428                    }
429                    st.opcode.reset(op_data.opcode);
430                    st.opcode.add_imm(imm as u32, op_data.imm_offset as _);
431                    emit_op!();
432                }
433            }
434
435            Encoding::BaseR => {
436                let op_data = &BASE_R[encoding_index];
437                if isign4 == enc_ops!(Reg) {
438                    st.opcode.reset(op_data.opcode);
439                    st.opcode.add_reg(op0.id(), op_data.r_shift);
440                    emit_op!();
441                }
442            }
443
444            Encoding::BaseRR => {
445                let op_data = &BASE_RR[encoding_index];
446                if isign4 == enc_ops!(Reg, Reg) {
447                    let mut x = 0;
448                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
449                        self.last_error = Some(AsmError::InvalidOperand);
450                        return;
451                    }
452                    if !check_gp_type(op1, op_data.b_type) {
453                        self.last_error = Some(AsmError::InvalidOperand);
454                        return;
455                    }
456
457                    if op_data.uniform != 0 && !check_signature!(op0, op1) {
458                        self.last_error = Some(AsmError::InvalidOperand);
459                        return;
460                    }
461
462                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
463                        self.last_error = Some(AsmError::InvalidOperand);
464                        return;
465                    }
466                    st.opcode.reset(op_data.opcode);
467                    st.opcode.add_imm(x, 31);
468                    st.opcode.add_reg(op1.id(), op_data.b_shift);
469                    st.opcode.add_reg(op0.id(), op_data.a_shift);
470                    emit_op!();
471                }
472            }
473
474            Encoding::BaseRRR => {
475                let op_data = &BASE_RRR[encoding_index];
476                if isign4 == enc_ops!(Reg, Reg, Reg) {
477                    let mut x = 0;
478                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
479                        self.last_error = Some(AsmError::InvalidOperand);
480                        return;
481                    }
482                    if !check_gp_type(op1, op_data.b_type) || !check_gp_type(op2, op_data.c_type) {
483                        self.last_error = Some(AsmError::InvalidOperand);
484                        return;
485                    }
486
487                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2) {
488                        self.last_error = Some(AsmError::InvalidInstruction);
489                        return;
490                    }
491
492                    if !check_gp_id(op0, op_data.a_hi_id)
493                        || !check_gp_id(op1, op_data.b_hi_id)
494                        || !check_gp_id(op2, op_data.c_hi_id)
495                    {
496                        self.last_error = Some(AsmError::InvalidOperand);
497                        return;
498                    }
499                    st.opcode.reset(op_data.opcode());
500                    st.opcode.add_imm(x, 31);
501                    st.opcode.add_reg(op2.id(), 16);
502                    st.opcode.add_reg(op1.id(), 5);
503                    st.opcode.add_reg(op0.id(), 0);
504                    emit_op!();
505                }
506            }
507
508            Encoding::BaseRRRR => {
509                let op_data = &BASE_RRRR[encoding_index];
510                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
511                    let mut x = 0;
512                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
513                        self.last_error = Some(AsmError::InvalidOperand);
514                        return;
515                    }
516                    if !check_gp_type(op1, op_data.b_type)
517                        || !check_gp_type(op2, op_data.c_type)
518                        || !check_gp_type(op3, op_data.d_type)
519                    {
520                        self.last_error = Some(AsmError::InvalidOperand);
521                        return;
522                    }
523
524                    if op_data.uniform != 0 && !check_signature!(op0, op1, op2, op3) {
525                        self.last_error = Some(AsmError::InvalidInstruction);
526                        return;
527                    }
528
529                    if !check_gp_id(op0, op_data.a_hi_id)
530                        || !check_gp_id(op1, op_data.b_hi_id)
531                        || !check_gp_id(op2, op_data.c_hi_id)
532                        || !check_gp_id(op3, op_data.d_hi_id)
533                    {
534                        self.last_error = Some(AsmError::InvalidOperand);
535                        return;
536                    }
537                    st.opcode.reset(op_data.opcode());
538                    st.opcode.add_imm(x, 31);
539                    st.opcode.add_reg(op2.id(), 16);
540                    st.opcode.add_reg(op3.id(), 10);
541                    st.opcode.add_reg(op1.id(), 5);
542                    st.opcode.add_reg(op0.id(), 0);
543                    emit_op!();
544                }
545            }
546
547            Encoding::BaseRRII => {
548                let op_data = &BASE_RRII[encoding_index];
549                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
550                    let mut x = 0;
551                    if !check_gp_typex(op0, op_data.a_type, &mut x) {
552                        self.last_error = Some(AsmError::InvalidOperand);
553                        return;
554                    }
555                    if !check_gp_type(op1, op_data.b_type) {
556                        self.last_error = Some(AsmError::InvalidOperand);
557                        return;
558                    }
559
560                    if !check_gp_id(op0, op_data.a_hi_id) || !check_gp_id(op1, op_data.b_hi_id) {
561                        self.last_error = Some(AsmError::InvalidOperand);
562                        return;
563                    }
564
565                    let imm2 = op2.as_::<Imm>().value() as u64;
566                    let imm3 = op3.as_::<Imm>().value() as u64;
567
568                    if imm2 >= 1u64 << (op_data.a_imm_size + op_data.a_imm_discard_lsb)
569                        || imm3 >= 1u64 << (op_data.b_imm_size + op_data.b_imm_discard_lsb)
570                    {
571                        self.last_error = Some(AsmError::TooLarge);
572                        return;
573                    }
574
575                    let a_imm = imm2 as u32 >> op_data.a_imm_discard_lsb;
576                    let b_imm = imm3 as u32 >> op_data.b_imm_discard_lsb;
577
578                    if (a_imm << op_data.a_imm_discard_lsb) != imm2 as u32
579                        || (b_imm << op_data.b_imm_discard_lsb) != imm3 as u32
580                    {
581                        self.last_error = Some(AsmError::TooLarge);
582                        return;
583                    }
584
585                    st.opcode.reset(op_data.opcode());
586                    st.opcode.add_imm(a_imm, op_data.a_imm_offset);
587                    st.opcode.add_imm(b_imm, op_data.b_imm_offset);
588                    st.opcode.add_reg(op1.id(), 5);
589                    st.opcode.add_reg(op0.id(), 0);
590                    emit_op!();
591                }
592            }
593
594            Encoding::BaseMov => {
595                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
596                if x > 1 {
597                    self.last_error = Some(AsmError::InvalidOperand);
598                    return;
599                }
600
601                if isign4 == enc_ops!(Reg, Reg) {
602                    if !op0.as_::<Reg>().is_gp() || !op1.as_::<Reg>().is_gp() {
603                        self.last_error = Some(AsmError::InvalidOperand);
604                        return;
605                    }
606
607                    if !check_signature!(op0, op1) {
608                        self.last_error = Some(AsmError::InvalidInstruction);
609                        return;
610                    }
611
612                    let has_sp = op0.as_::<Reg>().is_sp() || op1.as_::<Reg>().is_sp();
613
614                    if has_sp {
615                        if !check_gp_id2(op0, op1, 31) {
616                            self.last_error = Some(AsmError::InvalidOperand);
617                            return;
618                        }
619                        st.opcode.reset(0b00010001000000000000000000000000);
620                        st.opcode.add_imm(x, 31);
621                        st.opcode.add_reg(op1.id(), 5);
622                        st.opcode.add_reg(op0.id(), 0);
623                        emit_op!();
624                    } else {
625                        if !check_gp_id2(op0, op1, 63) {
626                            self.last_error = Some(AsmError::InvalidOperand);
627                            return;
628                        }
629                        st.opcode.reset(0b00101010000000000000001111100000);
630                        st.opcode.add_imm(x, 31);
631                        st.opcode.add_reg(op1.id(), 16);
632                        st.opcode.add_reg(op0.id(), 0);
633                        emit_op!();
634                    }
635                }
636
637                if isign4 == enc_ops!(Reg, Imm) {
638                    if !op0.as_::<Reg>().is_gp() {
639                        self.last_error = Some(AsmError::InvalidOperand);
640                        return;
641                    }
642
643                    let mut imm_value = op1.as_::<Imm>().value() as u64;
644                    if x == 0 {
645                        imm_value &= 0xFFFFFFFF;
646                    }
647
648                    // Prefer a single MOVN/MOVZ instruction over a logical instruction.
649                    st.multiple_op_count = encode_mov_sequence64(
650                        &mut st.multiple_op_data,
651                        imm_value,
652                        op0.id() & 31,
653                        x,
654                    );
655                    if st.multiple_op_count == 1 && !op0.as_::<Gp>().is_sp() {
656                        st.opcode.reset(st.multiple_op_data[0]);
657                        emit_op!();
658                    }
659
660                    if !op0.as_::<Gp>().is_zr() {
661                        if let Some(logical_imm) =
662                            encode_logical_imm(imm_value, if x != 0 { 64 } else { 32 })
663                        {
664                            st.opcode.reset(0b00110010000000000000001111100000);
665                            st.opcode.add_imm(x, 31);
666                            st.opcode.add_logical_imm(&logical_imm);
667                            st.opcode.add_reg(op0.id(), 0);
668                            emit_op!();
669                        }
670                    }
671
672                    check_features!();
673                    self.emit_handler(Handler::Multi, &mut st);
674                    return;
675                }
676            }
677
678            Encoding::BaseMovKNZ => {
679                let op_data = &BASE_MOV_KNZ[encoding_index];
680
681                let x = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Gp32 as u32);
682                if x > 1 {
683                    self.last_error = Some(AsmError::InvalidInstruction);
684                    return;
685                }
686
687                if !check_gp_id(op0, 63) {
688                    self.last_error = Some(AsmError::InvalidOperand);
689                    return;
690                }
691
692                st.opcode.reset(op_data.opcode);
693                st.opcode.add_imm(x, 31);
694
695                if isign4 == enc_ops!(Reg, Imm) {
696                    let imm16 = op1.as_::<Imm>().value() as u64;
697                    if imm16 > 0xFFFF {
698                        self.last_error = Some(AsmError::TooLarge);
699                        return;
700                    }
701
702                    st.opcode.add_imm(imm16 as u32, 5);
703                    st.opcode.add_reg(op0.id(), 0);
704                    emit_op!();
705                }
706
707                if isign4 == enc_ops!(Reg, Imm, Imm) {
708                    let imm16 = op1.as_::<Imm>().value() as u64;
709                    let shift_type = op2.as_::<Imm>().predicate();
710                    let shift_value = op2.as_::<Imm>().value() as u64;
711
712                    if imm16 > 0xFFFF || shift_value > 48 || shift_type != ShiftOp::LSL as u32 {
713                        self.last_error = Some(AsmError::TooLarge);
714                        return;
715                    }
716
717                    let hw = (shift_value as u32) >> 4;
718
719                    if hw << 4 != shift_value as u32 {
720                        self.last_error = Some(AsmError::InvalidOperand);
721                        return;
722                    }
723
724                    st.opcode.add_imm(hw, 21);
725                    st.opcode.add_imm(imm16 as u32, 5);
726                    st.opcode.add_reg(op0.id(), 0);
727
728                    if x == 0 && hw > 1 {
729                        self.last_error = Some(AsmError::InvalidOperand);
730                        return;
731                    }
732
733                    emit_op!();
734                }
735            }
736
737            Encoding::BaseAdr => {
738                let op_data = &BASE_ADR[encoding_index];
739                if isign4 == enc_ops!(Reg, Label)
740                    || isign4 == enc_ops!(Reg, Sym)
741                    || isign4 == enc_ops!(Reg, Imm)
742                {
743                    if !op0.as_::<Reg>().is_gp() {
744                        self.last_error = Some(AsmError::InvalidOperand);
745                        return;
746                    }
747
748                    if !check_gp_id(op0, 63) {
749                        self.last_error = Some(AsmError::InvalidOperand);
750                        return;
751                    }
752
753                    st.opcode.reset(op_data.opcode());
754                    st.opcode.add_reg(op0.id(), 0);
755                    st.offset_format.reset_to_imm_type(
756                        match OffsetType::try_from(op_data.offset_type) {
757                            Ok(offset_type) => offset_type,
758                            Err(()) => {
759                                unreachable!("instdb offset type is always a valid OffsetType")
760                            }
761                        },
762                        4,
763                        5,
764                        21,
765                        0,
766                    );
767
768                    if inst_id == InstId::Adrp as u32 {
769                        st.offset_format.imm_discard_lsb = 12;
770                    }
771                    st.rm_rel = *op1;
772                    emit_rel!();
773                }
774            }
775
776            Encoding::BaseAddSub => {
777                let op_data = &BASE_ADD_SUB[encoding_index];
778
779                let mut x = 0;
780                if !check_gp_typex2(op0, op1, 3, &mut x) {
781                    self.last_error = Some(AsmError::InvalidOperand);
782                    return;
783                }
784
785                if isign4 == enc_ops!(Reg, Reg, Imm) || isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
786                    st.opcode.reset((op_data.immediate_op as u32) << 24);
787
788                    // ADD | SUB (immediate) - ZR is not allowed.
789                    // ADDS|SUBS (immediate) - ZR allowed in Rd, SP allowed in Rn.
790                    let a_hi_id = if st.opcode.get() & 1 << 29 != 0 {
791                        63
792                    } else {
793                        31
794                    };
795                    let b_hi_id = 31;
796                    if !check_gp_id(op0, a_hi_id) || !check_gp_id(op1, b_hi_id) {
797                        self.last_error = Some(AsmError::InvalidOperand);
798                        return;
799                    }
800
801                    let mut imm = op2.as_::<Imm>().value() as u64;
802                    let mut shift = 0;
803
804                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
805                        if op3.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
806                            self.last_error = Some(AsmError::InvalidOperand);
807                            return;
808                        }
809
810                        if op3.as_::<Imm>().value() != 0 && op3.as_::<Imm>().value() != 12 {
811                            self.last_error = Some(AsmError::InvalidOperand);
812                            return;
813                        }
814
815                        shift = (op3.as_::<Imm>().value() != 0) as u32;
816                    }
817
818                    if imm > 0xfff {
819                        if shift != 0 || (imm & !(0xfff << 12)) != 0 {
820                            self.last_error = Some(AsmError::TooLarge);
821                            return;
822                        }
823
824                        shift = 1;
825                        imm >>= 12;
826                    }
827
828                    st.opcode.add_imm(x, 31);
829                    st.opcode.add_imm(shift, 12);
830                    st.opcode.add_imm(imm as u32, 10);
831                    st.opcode.add_reg(op1.id(), 5);
832                    st.opcode.add_reg(op0.id(), 0);
833                    emit_op!();
834                }
835
836                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
837                    let op_size = if x != 0 { 64 } else { 32 };
838                    let mut shift = 0;
839                    let mut shift_type = ShiftOp::LSL as u32;
840
841                    if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
842                        shift_type = op3.as_::<Imm>().predicate();
843                        shift = op3.as_::<Imm>().value() as u32;
844                    }
845
846                    if !check_gp_id(op2, 63) {
847                        self.last_error = Some(AsmError::InvalidOperand);
848                        return;
849                    }
850
851                    if shift_type <= ShiftOp::ASR as u32 {
852                        let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
853
854                        if !has_sp {
855                            if !check_signature!(op1, op2) {
856                                self.last_error = Some(AsmError::InvalidInstruction);
857                                return;
858                            }
859
860                            if !check_gp_id3(op0, op1, op2, 63) {
861                                self.last_error = Some(AsmError::InvalidOperand);
862                                return;
863                            }
864
865                            if shift >= op_size {
866                                self.last_error = Some(AsmError::InvalidOperand);
867                                return;
868                            }
869
870                            st.opcode.reset((op_data.shifted_op as u32) << 21);
871                            st.opcode.add_imm(x, 31);
872                            st.opcode.add_imm(shift_type, 22);
873                            st.opcode.add_reg(op2.id(), 16);
874                            st.opcode.add_imm(shift, 10);
875                            st.opcode.add_reg(op1.id(), 5);
876                            st.opcode.add_reg(op0.id(), 0);
877                            emit_op!();
878                        }
879
880                        if shift_type != ShiftOp::LSL as u32 {
881                            self.last_error = Some(AsmError::InvalidOperand);
882                            return;
883                        }
884
885                        shift_type = if x != 0 {
886                            ShiftOp::UXTX as u32
887                        } else {
888                            ShiftOp::UXTW as u32
889                        };
890                    }
891
892                    st.opcode.reset((op_data.extended_op as u32) << 21);
893                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
894
895                    if shift_type > 7 || shift > 4 {
896                        self.last_error = Some(AsmError::InvalidOperand);
897                        return;
898                    }
899
900                    if (st.opcode.get() & (1 << 29)) == 0 {
901                        if !check_gp_id2(op0, op1, 31) {
902                            self.last_error = Some(AsmError::InvalidOperand);
903                            return;
904                        }
905                    } else {
906                        if !check_gp_id(op0, 63) || !check_gp_id(op1, 31) {
907                            self.last_error = Some(AsmError::InvalidOperand);
908                            return;
909                        }
910                    }
911
912                    st.opcode.add_imm(x, 31);
913                    st.opcode.add_reg(op2.id(), 16);
914                    st.opcode.add_imm(shift_type, 13);
915                    st.opcode.add_imm(shift, 10);
916                    st.opcode.add_reg(op1.id(), 5);
917                    st.opcode.add_reg(op0.id(), 0);
918                    emit_op!();
919                }
920            }
921
922            Encoding::BaseLogical => {
923                let op_data = &BASE_LOGICAL[encoding_index];
924
925                let mut x = 0;
926                if !check_gp_typex2(op0, op1, 3, &mut x) {
927                    self.last_error = Some(AsmError::InvalidOperand);
928                    return;
929                }
930
931                if !check_signature!(op0, op1) {
932                    self.last_error = Some(AsmError::InvalidInstruction);
933                    return;
934                }
935
936                let op_size = if x != 0 { 64 } else { 32 };
937
938                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
939                    st.opcode.reset((op_data.immediate_op as u32) << 23);
940
941                    let imm_mask = lsb_mask::<u64>(op_size);
942                    let mut imm_value = op2.as_::<Imm>().value() as u64;
943
944                    if op_data.negate_imm != 0 {
945                        imm_value ^= imm_mask;
946                    }
947
948                    let Some(logical_imm) = encode_logical_imm(imm_value, op_size) else {
949                        self.last_error = Some(AsmError::InvalidOperand);
950                        return;
951                    };
952
953                    let op_ands = 0x3 << 29;
954                    let is_ands = (st.opcode.get() & op_ands) == op_ands;
955
956                    if !check_gp_id(op0, if is_ands { 63 } else { 31 }) || !check_gp_id(op1, 63) {
957                        self.last_error = Some(AsmError::InvalidOperand);
958                        return;
959                    }
960
961                    st.opcode.add_imm(x, 31);
962                    st.opcode.add_logical_imm(&logical_imm);
963                    st.opcode.add_reg(op1.id(), 5);
964                    st.opcode.add_reg(op0.id(), 0);
965                    emit_op!();
966                }
967
968                if !check_signature!(op1, op2) {
969                    self.last_error = Some(AsmError::InvalidInstruction);
970                    return;
971                }
972
973                if isign4 == enc_ops!(Reg, Reg, Reg) {
974                    if !check_gp_id3(op0, op1, op2, 63) {
975                        self.last_error = Some(AsmError::InvalidOperand);
976                        return;
977                    }
978
979                    st.opcode.reset((op_data.shifted_op as u32) << 21);
980                    st.opcode.add_imm(x, 31);
981                    st.opcode.add_reg(op2.id(), 16);
982                    st.opcode.add_reg(op1.id(), 5);
983                    st.opcode.add_reg(op0.id(), 0);
984                    emit_op!();
985                }
986
987                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
988                    if !check_gp_id3(op0, op1, op2, 63) {
989                        self.last_error = Some(AsmError::InvalidOperand);
990                        return;
991                    }
992
993                    let shift_type = op3.as_::<Imm>().predicate();
994                    let op_shift = op3.as_::<Imm>().value() as u32;
995
996                    if shift_type > 0x3 || op_shift >= op_size {
997                        self.last_error = Some(AsmError::InvalidOperand);
998                        return;
999                    }
1000
1001                    st.opcode.reset((op_data.shifted_op as u32) << 21);
1002                    st.opcode.add_imm(x, 31);
1003                    st.opcode.add_imm(shift_type, 22);
1004                    st.opcode.add_reg(op2.id(), 16);
1005                    st.opcode.add_imm(op_shift, 10);
1006                    st.opcode.add_reg(op1.id(), 5);
1007                    st.opcode.add_reg(op0.id(), 0);
1008                    emit_op!();
1009                }
1010            }
1011
1012            Encoding::BaseCmpCmn => {
1013                let op_data = &BASE_CMP_CMN[encoding_index];
1014
1015                let mut x = 0;
1016                if !check_gp_typex(op0, 3, &mut x) {
1017                    self.last_error = Some(AsmError::InvalidOperand);
1018                    return;
1019                }
1020
1021                if isign4 == enc_ops!(Reg, Imm) {
1022                    if !check_gp_id(op0, 31) {
1023                        self.last_error = Some(AsmError::InvalidOperand);
1024                        return;
1025                    }
1026
1027                    let imm12 = op1.as_::<Imm>();
1028                    let mut imm_shift = 0;
1029                    let mut imm_value = imm12.value() as u64;
1030
1031                    if imm_value > 0xfff {
1032                        if (imm_value & !(0xfff << 12)) != 0 {
1033                            self.last_error = Some(AsmError::TooLarge);
1034                            return;
1035                        }
1036                        imm_shift = 1;
1037                        imm_value >>= 12;
1038                    }
1039
1040                    st.opcode.reset((op_data.immediate_op as u32) << 24);
1041                    st.opcode.add_imm(x, 31);
1042                    st.opcode.add_imm(imm_shift, 22);
1043                    st.opcode.add_imm(imm_value as u32, 10);
1044                    st.opcode.add_reg(op0.id(), 5);
1045                    st.opcode.add_reg(63, 0);
1046                    emit_op!();
1047                }
1048
1049                if isign4 == enc_ops!(Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Imm) {
1050                    let op_size = if x != 0 { 64 } else { 32 };
1051                    let mut shift_type = 0;
1052                    let mut shift_value = 0;
1053
1054                    if isign4 == enc_ops!(Reg, Reg, Imm) {
1055                        shift_type = op2.as_::<Imm>().predicate();
1056                        shift_value = op2.as_::<Imm>().value() as u32;
1057                    }
1058
1059                    let has_sp = op0.as_::<Gp>().is_sp() || op1.as_::<Gp>().is_sp();
1060
1061                    if shift_type <= ShiftOp::ASR as u32 {
1062                        if !has_sp {
1063                            if !check_signature!(op0, op1) {
1064                                self.last_error = Some(AsmError::InvalidInstruction);
1065                                return;
1066                            }
1067
1068                            if shift_value >= op_size {
1069                                self.last_error = Some(AsmError::InvalidOperand);
1070                                return;
1071                            }
1072
1073                            st.opcode.reset((op_data.shifted_op as u32) << 21);
1074                            st.opcode.add_imm(x, 31);
1075                            st.opcode.add_imm(shift_type, 22);
1076                            st.opcode.add_reg(op1.id(), 16);
1077                            st.opcode.add_imm(shift_value, 10);
1078                            st.opcode.add_reg(op0.id(), 5);
1079                            st.opcode.add_reg(63, 0);
1080                            emit_op!();
1081                        }
1082
1083                        if shift_type != ShiftOp::LSL as u32 {
1084                            self.last_error = Some(AsmError::InvalidOperand);
1085                            return;
1086                        }
1087
1088                        shift_type = if x != 0 {
1089                            ShiftOp::UXTX as u32
1090                        } else {
1091                            ShiftOp::UXTW as u32
1092                        }
1093                    }
1094
1095                    shift_type = shift_type.wrapping_sub(ShiftOp::UXTB as u32);
1096
1097                    if shift_type > 7 || shift_value > 4 {
1098                        self.last_error = Some(AsmError::InvalidOperand);
1099                        return;
1100                    }
1101
1102                    st.opcode.reset((op_data.extended_op as u32) << 21);
1103                    st.opcode.add_imm(x, 31);
1104                    st.opcode.add_reg(op1.id(), 16);
1105                    st.opcode.add_imm(shift_type, 13);
1106                    st.opcode.add_imm(shift_value, 10);
1107                    st.opcode.add_reg(op0.id(), 5);
1108                    st.opcode.add_reg(63, 0);
1109                    emit_op!();
1110                }
1111            }
1112
1113            Encoding::BaseMvnNeg => {
1114                let op_data = &BASE_MVN_NEG[encoding_index];
1115
1116                let mut x = 0;
1117                if !check_gp_typex2(op0, op1, 3, &mut x) {
1118                    self.last_error = Some(AsmError::InvalidOperand);
1119                    return;
1120                }
1121
1122                st.opcode.reset(op_data.opcode);
1123                st.opcode.add_imm(x, 31);
1124                st.opcode.add_reg(op1.id(), 16);
1125                st.opcode.add_reg(op0.id(), 0);
1126
1127                if isign4 == enc_ops!(Reg, Reg) {
1128                    if !check_gp_id2(op0, op1, 63) {
1129                        self.last_error = Some(AsmError::InvalidOperand);
1130                        return;
1131                    }
1132
1133                    emit_op!();
1134                }
1135
1136                if isign4 == enc_ops!(Reg, Reg, Imm) {
1137                    if !check_gp_id2(op0, op1, 63) {
1138                        self.last_error = Some(AsmError::InvalidOperand);
1139                        return;
1140                    }
1141
1142                    let op_size = if x != 0 { 64 } else { 32 };
1143                    let shift_type = op2.as_::<Imm>().predicate();
1144                    let shift_value = op2.as_::<Imm>().value() as u32;
1145
1146                    if shift_type > ShiftOp::ROR as u32 || shift_value >= op_size {
1147                        self.last_error = Some(AsmError::InvalidOperand);
1148                        return;
1149                    }
1150
1151                    st.opcode.add_imm(shift_type, 22);
1152                    st.opcode.add_imm(shift_value, 10);
1153                    emit_op!();
1154                }
1155            }
1156
1157            Encoding::BaseTst => {
1158                let op_data = &BASE_TST[encoding_index];
1159
1160                let mut x = 0;
1161                if !check_gp_typex(op0, 3, &mut x) {
1162                    self.last_error = Some(AsmError::InvalidOperand);
1163                    return;
1164                }
1165
1166                if isign4 == enc_ops!(Reg, Imm) && op_data.immediate_op != 0 {
1167                    if !check_gp_id(op0, 63) {
1168                        self.last_error = Some(AsmError::InvalidOperand);
1169                        return;
1170                    }
1171                    let op_size = if x != 0 { 64 } else { 32 };
1172                    let imm_mask = lsb_mask::<u64>(op_size);
1173                    let imm_value = op1.as_::<Imm>().value() as u64;
1174
1175                    let Some(logical_imm) = encode_logical_imm(imm_value & imm_mask, op_size)
1176                    else {
1177                        self.last_error = Some(AsmError::InvalidOperand);
1178                        return;
1179                    };
1180
1181                    st.opcode.reset((op_data.immediate_op as u32) << 22);
1182                    st.opcode.add_logical_imm(&logical_imm);
1183                    st.opcode.add_imm(x, 31);
1184                    st.opcode.add_reg(op0.id(), 5);
1185                    st.opcode.add_reg(63, 0);
1186                    emit_op!();
1187                }
1188
1189                st.opcode.reset((op_data.shifted_op as u32) << 21);
1190                st.opcode.add_imm(x, 31);
1191                st.opcode.add_reg(op1.id(), 16);
1192                st.opcode.add_reg(op0.id(), 5);
1193                st.opcode.add_reg(63, 0);
1194
1195                if isign4 == enc_ops!(Reg, Reg) {
1196                    if !check_gp_id2(op0, op1, 63) {
1197                        self.last_error = Some(AsmError::InvalidOperand);
1198                        return;
1199                    }
1200
1201                    emit_op!();
1202                }
1203
1204                if isign4 == enc_ops!(Reg, Reg, Imm) {
1205                    if !check_gp_id2(op0, op1, 63) {
1206                        self.last_error = Some(AsmError::InvalidOperand);
1207                        return;
1208                    }
1209
1210                    let shift_type = op2.as_::<Imm>().predicate();
1211                    let shift_value = op2.as_::<Imm>().value() as u32;
1212
1213                    if shift_type > 0x3 || shift_value >= (if x != 0 { 64 } else { 32 }) {
1214                        self.last_error = Some(AsmError::InvalidOperand);
1215                        return;
1216                    }
1217
1218                    st.opcode.add_imm(shift_type, 22);
1219                    st.opcode.add_imm(shift_value, 10);
1220                    emit_op!();
1221                }
1222            }
1223
1224            Encoding::BaseBfc => {
1225                let op_data = &BASE_BFC[encoding_index];
1226                if isign4 == enc_ops!(Reg, Imm, Imm) {
1227                    let mut x = 0;
1228                    if !check_gp_typex(op0, 3, &mut x) {
1229                        self.last_error = Some(AsmError::InvalidOperand);
1230                        return;
1231                    }
1232
1233                    let lsb = op1.as_::<Imm>().value() as u64;
1234                    let width = op2.as_::<Imm>().value() as u64;
1235                    let op_size = if x != 0 { 64 } else { 32 };
1236
1237                    if lsb >= op_size || width == 0 || width > op_size {
1238                        self.last_error = Some(AsmError::InvalidOperand);
1239                        return;
1240                    }
1241
1242                    let lsb32 = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1243                    let width32 = width as u32 - 1;
1244
1245                    st.opcode.reset(op_data.opcode);
1246                    st.opcode.add_imm(x, 31);
1247                    st.opcode.add_imm(x, 22);
1248                    st.opcode.add_imm(lsb32, 16);
1249                    st.opcode.add_imm(width32, 10);
1250                    st.opcode.add_reg(op0.id(), 0);
1251                    emit_op!();
1252                }
1253            }
1254
1255            Encoding::BaseBfi => {
1256                let op_data = &BASE_BFI[encoding_index];
1257                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1258                    let mut x = 0;
1259                    if !check_gp_typex(op0, 3, &mut x) {
1260                        self.last_error = Some(AsmError::InvalidOperand);
1261                        return;
1262                    }
1263
1264                    if !check_signature!(op0, op1) {
1265                        self.last_error = Some(AsmError::InvalidInstruction);
1266                        return;
1267                    }
1268
1269                    if !check_gp_id2(op0, op1, 63) {
1270                        self.last_error = Some(AsmError::InvalidOperand);
1271                        return;
1272                    }
1273
1274                    let lsb = op2.as_::<Imm>().value() as u64;
1275                    let width = op3.as_::<Imm>().value() as u64;
1276                    let op_size = if x != 0 { 64 } else { 32 };
1277
1278                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1279                        self.last_error = Some(AsmError::InvalidOperand);
1280                        return;
1281                    }
1282
1283                    let imm_l = 0u32.wrapping_sub(lsb as u32) & (op_size as u32 - 1);
1284                    let imm_w = width as u32 - 1;
1285
1286                    st.opcode.reset(op_data.opcode);
1287                    st.opcode.add_imm(x, 31);
1288                    st.opcode.add_imm(x, 22);
1289                    st.opcode.add_imm(imm_l, 16);
1290                    st.opcode.add_imm(imm_w, 10);
1291                    st.opcode.add_reg(op1.id(), 5);
1292                    st.opcode.add_reg(op0.id(), 0);
1293                    emit_op!();
1294                }
1295            }
1296
1297            Encoding::BaseBfm => {
1298                let op_data = &BASE_BFM[encoding_index];
1299                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1300                    let mut x = 0;
1301                    if !check_gp_typex(op0, 3, &mut x) {
1302                        self.last_error = Some(AsmError::InvalidInstruction);
1303                        return;
1304                    }
1305
1306                    if !check_signature!(op0, op1) {
1307                        self.last_error = Some(AsmError::InvalidInstruction);
1308                        return;
1309                    }
1310
1311                    if !check_gp_id2(op0, op1, 63) {
1312                        self.last_error = Some(AsmError::InvalidOperand);
1313                        return;
1314                    }
1315
1316                    let imm_r = op2.as_::<Imm>().value() as u64;
1317                    let imm_s = op3.as_::<Imm>().value() as u64;
1318                    let op_size = if x != 0 { 64 } else { 32 };
1319
1320                    if (imm_r | imm_s) >= op_size as u64 {
1321                        self.last_error = Some(AsmError::InvalidOperand);
1322                        return;
1323                    }
1324
1325                    st.opcode.reset(op_data.opcode);
1326                    st.opcode.add_imm(x, 31);
1327                    st.opcode.add_imm(x, 22);
1328                    st.opcode.add_imm(imm_r as u32, 16);
1329                    st.opcode.add_imm(imm_s as u32, 10);
1330                    st.opcode.add_reg(op1.id(), 5);
1331                    st.opcode.add_reg(op0.id(), 0);
1332                    emit_op!();
1333                }
1334            }
1335
1336            Encoding::BaseBfx => {
1337                let op_data = &BASE_BFX[encoding_index];
1338                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1339                    let mut x = 0;
1340                    if !check_gp_typex(op0, 3, &mut x) {
1341                        self.last_error = Some(AsmError::InvalidInstruction);
1342                        return;
1343                    }
1344
1345                    if !check_signature!(op0, op1) {
1346                        self.last_error = Some(AsmError::InvalidInstruction);
1347                        return;
1348                    }
1349
1350                    if !check_gp_id2(op0, op1, 63) {
1351                        self.last_error = Some(AsmError::InvalidOperand);
1352                        return;
1353                    }
1354
1355                    let lsb = op2.as_::<Imm>().value() as u64;
1356                    let width = op3.as_::<Imm>().value() as u64;
1357                    let op_size = if x != 0 { 64 } else { 32 };
1358
1359                    if lsb >= op_size as u64 || width == 0 || width > op_size as u64 {
1360                        self.last_error = Some(AsmError::InvalidOperand);
1361                        return;
1362                    }
1363
1364                    let lsb32 = lsb as u32;
1365                    let width32 = lsb32 + width as u32 - 1;
1366
1367                    if width32 >= op_size as u32 {
1368                        self.last_error = Some(AsmError::InvalidOperand);
1369                        return;
1370                    }
1371
1372                    st.opcode.reset(op_data.opcode);
1373                    st.opcode.add_imm(x, 31);
1374                    st.opcode.add_imm(x, 22);
1375                    st.opcode.add_imm(lsb32, 16);
1376                    st.opcode.add_imm(width32, 10);
1377                    st.opcode.add_reg(op1.id(), 5);
1378                    st.opcode.add_reg(op0.id(), 0);
1379                    emit_op!();
1380                }
1381            }
1382
1383            Encoding::BaseExtend => {
1384                let op_data = &BASE_EXTEND[encoding_index];
1385
1386                if isign4 == enc_ops!(Reg, Reg) {
1387                    let mut x = 0;
1388                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
1389                        self.last_error = Some(AsmError::InvalidOperand);
1390                        return;
1391                    }
1392
1393                    if !op1.as_::<Reg>().is_gp32() {
1394                        self.last_error = Some(AsmError::InvalidOperand);
1395                        return;
1396                    }
1397
1398                    if !check_gp_id2(op0, op1, 63) {
1399                        self.last_error = Some(AsmError::InvalidOperand);
1400                        return;
1401                    }
1402
1403                    st.opcode.reset(op_data.opcode());
1404                    st.opcode.add_imm(x, 31);
1405                    st.opcode.add_imm(x, 22);
1406                    st.opcode.add_reg(op1.id(), 5);
1407                    st.opcode.add_reg(op0.id(), 0);
1408                    emit_op!();
1409                }
1410            }
1411
1412            Encoding::BaseExtract => {
1413                let op_data = &BASE_EXTRACT[encoding_index];
1414
1415                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1416                    let mut x = 0;
1417                    if !check_gp_typex(op0, 3, &mut x) {
1418                        self.last_error = Some(AsmError::InvalidInstruction);
1419                        return;
1420                    }
1421
1422                    if !check_signature!(op0, op1, op2) {
1423                        self.last_error = Some(AsmError::InvalidInstruction);
1424                        return;
1425                    }
1426
1427                    if !check_gp_id3(op0, op1, op2, 63) {
1428                        self.last_error = Some(AsmError::InvalidOperand);
1429                        return;
1430                    }
1431
1432                    let lsb = op3.as_::<Imm>().value() as u64;
1433                    let op_size = if x != 0 { 64 } else { 32 };
1434
1435                    if lsb >= op_size as u64 {
1436                        self.last_error = Some(AsmError::InvalidOperand);
1437                        return;
1438                    }
1439
1440                    st.opcode.reset(op_data.opcode);
1441                    st.opcode.add_imm(x, 31);
1442                    st.opcode.add_imm(x, 22);
1443                    st.opcode.add_reg(op2.id(), 16);
1444                    st.opcode.add_imm(lsb as u32, 10);
1445                    st.opcode.add_reg(op1.id(), 5);
1446                    st.opcode.add_reg(op0.id(), 0);
1447                    emit_op!();
1448                }
1449            }
1450
1451            Encoding::BaseRev => {
1452                if isign4 == enc_ops!(Reg, Reg) {
1453                    let mut x = 0;
1454                    if !check_gp_typex(op0, 3, &mut x) {
1455                        self.last_error = Some(AsmError::InvalidInstruction);
1456                        return;
1457                    }
1458
1459                    if !check_signature!(op0, op1) {
1460                        self.last_error = Some(AsmError::InvalidInstruction);
1461                        return;
1462                    }
1463
1464                    if !check_gp_id2(op0, op1, 63) {
1465                        self.last_error = Some(AsmError::InvalidOperand);
1466                        return;
1467                    }
1468
1469                    st.opcode.reset(0b01011010110000000000100000000000);
1470                    st.opcode.add_imm(x, 31);
1471                    st.opcode.add_imm(x, 10);
1472                    st.opcode.add_reg(op1.id(), 5);
1473                    st.opcode.add_reg(op0.id(), 0);
1474                    emit_op!();
1475                }
1476            }
1477
1478            Encoding::BaseShift => {
1479                let op_data = &BASE_SHIFT[encoding_index];
1480
1481                let mut x = 0;
1482                if !check_gp_typex(op0, 3, &mut x) {
1483                    self.last_error = Some(AsmError::InvalidInstruction);
1484                    return;
1485                }
1486
1487                if isign4 == enc_ops!(Reg, Reg, Reg) {
1488                    if !check_signature!(op0, op1, op2) {
1489                        self.last_error = Some(AsmError::InvalidInstruction);
1490                        return;
1491                    }
1492
1493                    if !check_gp_id3(op0, op1, op2, 63) {
1494                        self.last_error = Some(AsmError::InvalidOperand);
1495                        return;
1496                    }
1497
1498                    st.opcode.reset(op_data.register_op());
1499                    st.opcode.add_imm(x, 31);
1500                    st.opcode.add_reg(op2.id(), 16);
1501                    st.opcode.add_reg(op1.id(), 5);
1502                    st.opcode.add_reg(op0.id(), 0);
1503                    emit_op!();
1504                }
1505
1506                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
1507                    if !check_signature!(op0, op1) {
1508                        self.last_error = Some(AsmError::InvalidInstruction);
1509                        return;
1510                    }
1511
1512                    if !check_gp_id2(op0, op1, 63) {
1513                        self.last_error = Some(AsmError::InvalidOperand);
1514                        return;
1515                    }
1516
1517                    let imm_r = op2.as_::<Imm>().value() as u64;
1518                    let op_size = if x != 0 { 64 } else { 32 };
1519
1520                    if imm_r >= op_size as u64 {
1521                        self.last_error = Some(AsmError::InvalidOperand);
1522                        return;
1523                    }
1524
1525                    st.opcode.reset(op_data.immediate_op());
1526                    st.opcode.add_imm(x, 31);
1527                    st.opcode.add_imm(x, 22);
1528                    st.opcode.add_reg(op1.id(), 5);
1529                    st.opcode.add_reg(op0.id(), 0);
1530
1531                    if st.opcode.get() & (1 << 10) != 0 {
1532                        st.opcode.add_imm(x, 15);
1533                        st.opcode.add_imm(imm_r as u32, 16);
1534                        emit_op!();
1535                    }
1536
1537                    if op_data.ror == 0 {
1538                        let ubfm_imm_r = (0u32).wrapping_sub(imm_r as u32) & (op_size as u32 - 1);
1539                        let ubfm_imm_s = op_size as u32 - 1 - imm_r as u32;
1540
1541                        st.opcode.add_imm(ubfm_imm_r, 16);
1542                        st.opcode.add_imm(ubfm_imm_s, 10);
1543                        emit_op!();
1544                    } else {
1545                        st.opcode.add_imm(imm_r as u32, 10);
1546                        st.opcode.add_reg(op1.id(), 16);
1547                        emit_op!();
1548                    }
1549                }
1550            }
1551
1552            Encoding::BaseCCmp => {
1553                let op_data = &BASE_C_CMP[encoding_index];
1554
1555                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) || isign4 == enc_ops!(Reg, Imm, Imm, Imm)
1556                {
1557                    let mut x = 0;
1558                    if !check_gp_typex(op0, 3, &mut x) {
1559                        self.last_error = Some(AsmError::InvalidOperand);
1560                        return;
1561                    }
1562
1563                    if !check_gp_id(op0, 31) {
1564                        self.last_error = Some(AsmError::InvalidOperand);
1565                        return;
1566                    }
1567
1568                    let nzcv = op2.as_::<Imm>().value() as u64;
1569                    let cond = op3.as_::<Imm>().value() as u64;
1570
1571                    if (nzcv | cond) > 0xF {
1572                        self.last_error = Some(AsmError::TooLarge);
1573                        return;
1574                    }
1575
1576                    st.opcode.reset(op_data.opcode);
1577                    st.opcode.add_imm(x, 31);
1578                    st.opcode
1579                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1580                    st.opcode.add_imm(nzcv as u32, 0);
1581
1582                    if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
1583                        if !check_signature!(op0, op1) {
1584                            self.last_error = Some(AsmError::InvalidInstruction);
1585                            return;
1586                        }
1587
1588                        if !check_gp_id(op1, 31) {
1589                            self.last_error = Some(AsmError::InvalidOperand);
1590                            return;
1591                        }
1592
1593                        st.opcode.add_reg(op1.id(), 16);
1594                        st.opcode.add_reg(op0.id(), 5);
1595                        emit_op!();
1596                    } else {
1597                        let imm5 = op1.as_::<Imm>().value() as u64;
1598                        if imm5 > 0x1F {
1599                            self.last_error = Some(AsmError::TooLarge);
1600                            return;
1601                        }
1602
1603                        st.opcode.add_imm(1, 11);
1604                        st.opcode.add_imm(imm5 as u32, 16);
1605                        st.opcode.add_reg(op0.id(), 5);
1606                        emit_op!();
1607                    }
1608                }
1609            }
1610
1611            Encoding::BaseCInc => {
1612                let op_data = &BASE_C_INC[encoding_index];
1613
1614                if isign4 == enc_ops!(Reg, Reg, Imm) {
1615                    let mut x = 0;
1616                    if !check_gp_typex2(op0, op1, 3, &mut x) {
1617                        self.last_error = Some(AsmError::InvalidInstruction);
1618                        return;
1619                    }
1620
1621                    if !check_gp_id2(op0, op1, 31) {
1622                        self.last_error = Some(AsmError::InvalidOperand);
1623                        return;
1624                    }
1625
1626                    let cond = op2.as_::<Imm>().value() as u64;
1627                    if cond.wrapping_sub(2) > 0xE {
1628                        self.last_error = Some(AsmError::TooLarge);
1629                        return;
1630                    }
1631
1632                    st.opcode.reset(op_data.opcode);
1633                    st.opcode.add_imm(x, 31);
1634                    st.opcode.add_reg(op1.id(), 16);
1635                    st.opcode
1636                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1637                    st.opcode.add_reg(op1.id(), 5);
1638                    st.opcode.add_reg(op0.id(), 0);
1639                    emit_op!();
1640                }
1641            }
1642
1643            Encoding::BaseCSel => {
1644                let op_data = &BASE_C_SEL[encoding_index];
1645
1646                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
1647                    let mut x = 0;
1648                    if !check_gp_typex(op0, 3, &mut x) {
1649                        self.last_error = Some(AsmError::InvalidInstruction);
1650                        return;
1651                    }
1652
1653                    if !check_signature!(op0, op1, op2) {
1654                        self.last_error = Some(AsmError::InvalidInstruction);
1655                        return;
1656                    }
1657
1658                    // `Rm` (op2) may be `XZR`/`WZR` (id 63, e.g. a `CSEL`
1659                    // zeroing idiom); it encodes as 31 like `SP`.
1660                    if !check_gp_id2(op0, op1, 31) || !check_gp_id(op2, 63) {
1661                        self.last_error = Some(AsmError::InvalidOperand);
1662                        return;
1663                    }
1664
1665                    let cond = op3.as_::<Imm>().value() as u64;
1666                    if cond > 0xF {
1667                        self.last_error = Some(AsmError::TooLarge);
1668                        return;
1669                    }
1670
1671                    st.opcode.reset(op_data.opcode);
1672                    st.opcode.add_imm(x, 31);
1673                    st.opcode.add_reg(op2.id(), 16);
1674                    st.opcode
1675                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
1676                    st.opcode.add_reg(op1.id(), 5);
1677                    st.opcode.add_reg(op0.id(), 0);
1678                    emit_op!();
1679                }
1680            }
1681
1682            Encoding::BaseCSet => {
1683                let op_data = &BASE_C_SET[encoding_index];
1684
1685                if isign4 == enc_ops!(Reg, Imm) {
1686                    let mut x = 0;
1687                    if !check_gp_typex(op0, 3, &mut x) {
1688                        self.last_error = Some(AsmError::InvalidInstruction);
1689                        return;
1690                    }
1691
1692                    if !check_gp_id(op0, 31) {
1693                        self.last_error = Some(AsmError::InvalidOperand);
1694                        return;
1695                    }
1696
1697                    let cond = op1.as_::<Imm>().value() as u64;
1698                    if cond.wrapping_sub(2) >= 0xE {
1699                        self.last_error = Some(AsmError::TooLarge);
1700                        return;
1701                    }
1702
1703                    st.opcode.reset(op_data.opcode);
1704                    st.opcode.add_imm(x, 31);
1705                    st.opcode
1706                        .add_imm(cond_code_to_opcode_field((cond as u32) ^ 1), 12);
1707                    st.opcode.add_reg(op0.id(), 0);
1708                    emit_op!();
1709                }
1710            }
1711
1712            Encoding::BaseMinMax => {
1713                let op_data = &BASE_MIN_MAX[encoding_index];
1714
1715                if isign4 == enc_ops!(Reg, Reg, Reg) {
1716                    let mut x = 0;
1717                    if !check_gp_typex(op0, 3, &mut x) {
1718                        self.last_error = Some(AsmError::InvalidInstruction);
1719                        return;
1720                    }
1721
1722                    if !check_signature!(op0, op1, op2) {
1723                        self.last_error = Some(AsmError::InvalidInstruction);
1724                        return;
1725                    }
1726
1727                    st.opcode.reset(op_data.register_op);
1728                    st.opcode.add_imm(x, 31);
1729                    st.opcode.add_reg(op2.id(), 16);
1730                    st.opcode.add_reg(op1.id(), 5);
1731                    st.opcode.add_reg(op0.id(), 0);
1732                    emit_op!();
1733                }
1734
1735                if isign4 == enc_ops!(Reg, Reg, Imm) {
1736                    let mut x = 0;
1737                    if !check_gp_typex(op0, 3, &mut x) {
1738                        self.last_error = Some(AsmError::InvalidInstruction);
1739                        return;
1740                    }
1741
1742                    if !check_signature!(op0, op1) {
1743                        self.last_error = Some(AsmError::InvalidInstruction);
1744                        return;
1745                    }
1746
1747                    let imm = op2.as_::<Imm>().value() as u64;
1748
1749                    if (op_data.immediate_op & (1u32 << 18)) != 0 {
1750                        if imm > 0xFF {
1751                            self.last_error = Some(AsmError::TooLarge);
1752                            return;
1753                        }
1754                    } else {
1755                        if (imm as i64) < -128 || (imm as i64) > 127 {
1756                            self.last_error = Some(AsmError::TooLarge);
1757                            return;
1758                        }
1759                    }
1760
1761                    st.opcode.reset(op_data.immediate_op);
1762                    st.opcode.add_imm(x, 31);
1763                    st.opcode.add_imm((imm & 0xFF) as u32, 10);
1764                    st.opcode.add_reg(op1.id(), 5);
1765                    st.opcode.add_reg(op0.id(), 0);
1766                    emit_op!();
1767                }
1768            }
1769
1770            Encoding::BaseAtDcIcTlbi => {
1771                let op_data = &BASE_AT_DC_IC_TLBI[encoding_index];
1772
1773                if isign4 == enc_ops!(Imm) || isign4 == enc_ops!(Imm, Reg) {
1774                    if op_data.mandatory_reg != 0 && isign4 != enc_ops!(Imm, Reg) {
1775                        self.last_error = Some(AsmError::InvalidInstruction);
1776                        return;
1777                    }
1778
1779                    if op0.as_::<Imm>().value() as u64 > 0x7FFF {
1780                        self.last_error = Some(AsmError::TooLarge);
1781                        return;
1782                    }
1783
1784                    let imm = op0.as_::<Imm>().value() as u32;
1785                    if (imm & op_data.imm_verify_mask) != op_data.imm_verify_data {
1786                        self.last_error = Some(AsmError::InvalidOperand);
1787                        return;
1788                    }
1789
1790                    let mut rt = 31;
1791                    if op1.is_reg() {
1792                        if !op1.as_::<Reg>().is_gp64() {
1793                            self.last_error = Some(AsmError::InvalidInstruction);
1794                            return;
1795                        }
1796
1797                        if !check_gp_id(op1, 63) {
1798                            self.last_error = Some(AsmError::InvalidOperand);
1799                            return;
1800                        }
1801
1802                        rt = op1.id() & 31;
1803                    }
1804
1805                    st.opcode.reset(0b11010101000010000000000000000000);
1806                    st.opcode.add_imm(imm, 5);
1807                    st.opcode.add_reg(rt, 0);
1808                    emit_op!();
1809                }
1810            }
1811
1812            Encoding::BaseMrs => {
1813                if isign4 == enc_ops!(Reg, Imm) {
1814                    if !op0.as_::<Reg>().is_gp64() {
1815                        self.last_error = Some(AsmError::InvalidInstruction);
1816                        return;
1817                    }
1818
1819                    if !check_gp_id(op0, 63) {
1820                        self.last_error = Some(AsmError::InvalidOperand);
1821                        return;
1822                    }
1823
1824                    if op1.as_::<Imm>().value() as u64 > 0xFFFF {
1825                        self.last_error = Some(AsmError::TooLarge);
1826                        return;
1827                    }
1828
1829                    let imm = op1.as_::<Imm>().value() as u32;
1830                    if (imm & (1 << 15)) == 0 {
1831                        self.last_error = Some(AsmError::InvalidOperand);
1832                        return;
1833                    }
1834
1835                    st.opcode.reset(0b11010101001100000000000000000000);
1836                    st.opcode.add_imm(imm, 5);
1837                    st.opcode.add_reg(op0.id(), 0);
1838                    emit_op!();
1839                }
1840            }
1841
1842            Encoding::BaseMsr => {
1843                if isign4 == enc_ops!(Imm, Reg) {
1844                    if !op1.as_::<Reg>().is_gp64() {
1845                        self.last_error = Some(AsmError::InvalidInstruction);
1846                        return;
1847                    }
1848
1849                    if op0.as_::<Imm>().value() as u64 > 0xFFFF {
1850                        self.last_error = Some(AsmError::TooLarge);
1851                        return;
1852                    }
1853
1854                    let imm = op0.as_::<Imm>().value() as u32;
1855                    if (imm & (1 << 15)) == 0 {
1856                        self.last_error = Some(AsmError::InvalidOperand);
1857                        return;
1858                    }
1859
1860                    if !check_gp_id(op1, 63) {
1861                        self.last_error = Some(AsmError::InvalidOperand);
1862                        return;
1863                    }
1864
1865                    st.opcode.reset(0b11010101000100000000000000000000);
1866                    st.opcode.add_imm(imm, 5);
1867                    st.opcode.add_reg(op1.id(), 0);
1868                    emit_op!();
1869                }
1870
1871                if isign4 == enc_ops!(Imm, Imm) {
1872                    if op0.as_::<Imm>().value() as u64 > 0x1F {
1873                        self.last_error = Some(AsmError::TooLarge);
1874                        return;
1875                    }
1876
1877                    if op1.as_::<Imm>().value() as u64 > 0xF {
1878                        self.last_error = Some(AsmError::TooLarge);
1879                        return;
1880                    }
1881
1882                    let op = op0.as_::<Imm>().value() as u32;
1883                    let crm = op1.as_::<Imm>().value() as u32;
1884
1885                    let op1_val = op >> 3;
1886                    let op2_val = op & 0x7;
1887
1888                    st.opcode.reset(0b11010101000000000100000000011111);
1889                    st.opcode.add_imm(op1_val, 16);
1890                    st.opcode.add_imm(crm, 8);
1891                    st.opcode.add_imm(op2_val, 5);
1892                    emit_op!();
1893                }
1894            }
1895
1896            Encoding::BaseSys => {
1897                if isign4 == enc_ops!(Imm, Imm, Imm, Imm) {
1898                    if op0.as_::<Imm>().value() as u64 > 0x7
1899                        || op1.as_::<Imm>().value() as u64 > 0xF
1900                        || op2.as_::<Imm>().value() as u64 > 0xF
1901                        || op3.as_::<Imm>().value() as u64 > 0x7
1902                    {
1903                        self.last_error = Some(AsmError::TooLarge);
1904                        return;
1905                    }
1906
1907                    let op1_val = op0.as_::<Imm>().value() as u32;
1908                    let crn = op1.as_::<Imm>().value() as u32;
1909                    let crm = op2.as_::<Imm>().value() as u32;
1910                    let op2_val = op3.as_::<Imm>().value() as u32;
1911                    let mut rt = 31;
1912
1913                    let op4 = *ops.get(4).unwrap_or(&NOREG);
1914                    if op4.is_reg() {
1915                        if !op4.as_::<Reg>().is_gp64() {
1916                            self.last_error = Some(AsmError::InvalidInstruction);
1917                            return;
1918                        }
1919
1920                        if !check_gp_id(op4, 63) {
1921                            self.last_error = Some(AsmError::InvalidOperand);
1922                            return;
1923                        }
1924
1925                        rt = op4.id() & 31;
1926                    } else if !op4.is_none() {
1927                        self.last_error = Some(AsmError::InvalidInstruction);
1928                        return;
1929                    }
1930
1931                    st.opcode.reset(0b11010101000010000000000000000000);
1932                    st.opcode.add_imm(op1_val, 16);
1933                    st.opcode.add_imm(crn, 12);
1934                    st.opcode.add_imm(crm, 8);
1935                    st.opcode.add_imm(op2_val, 5);
1936                    st.opcode.add_reg(rt, 0);
1937                    emit_op!();
1938                }
1939            }
1940
1941            Encoding::BaseBranchReg => {
1942                let op_data = &BASE_BRANCH_REG[encoding_index];
1943                if isign4 == enc_ops!(Reg) {
1944                    if !op0.as_::<Reg>().is_gp64() {
1945                        self.last_error = Some(AsmError::InvalidInstruction);
1946                        return;
1947                    }
1948
1949                    if !check_gp_id(op0, 63) {
1950                        self.last_error = Some(AsmError::InvalidOperand);
1951                        return;
1952                    }
1953
1954                    st.opcode.reset(op_data.opcode);
1955                    st.opcode.add_reg(op0.id(), 5);
1956                    emit_op!();
1957                }
1958            }
1959
1960            Encoding::BaseBranchRel => {
1961                let op_data = &BASE_BRANCH_REL[encoding_index];
1962                if isign4 == enc_ops!(Label) || isign4 == enc_ops!(Imm) {
1963                    st.opcode.reset(op_data.opcode);
1964                    st.rm_rel = *op0;
1965
1966                    if inst_cc as u32 != 0 || (st.opcode.0 & (1 << 30)) != 0 {
1967                        if st.opcode.has_x() {
1968                            self.last_error = Some(AsmError::InvalidInstruction);
1969                            return;
1970                        }
1971
1972                        st.opcode.0 |= 1 << 30;
1973                        st.opcode
1974                            .add_imm(cond_code_to_opcode_field(inst_cc as u32), 0);
1975                        st.offset_format
1976                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
1977                        st.rm_rel = *op0;
1978                        emit_rel!();
1979                    }
1980
1981                    st.offset_format
1982                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 0, 26, 2);
1983                    st.rm_rel = *op0;
1984                    emit_rel!();
1985                }
1986            }
1987
1988            Encoding::BaseBranchCmp => {
1989                let op_data = &BASE_BRANCH_CMP[encoding_index];
1990                if isign4 == enc_ops!(Reg, Label) || isign4 == enc_ops!(Reg, Imm) {
1991                    let mut x = 0;
1992                    if !check_gp_typex(op0, 3, &mut x) {
1993                        self.last_error = Some(AsmError::InvalidInstruction);
1994                        return;
1995                    }
1996
1997                    if !check_gp_id(op0, 31) {
1998                        self.last_error = Some(AsmError::InvalidOperand);
1999                        return;
2000                    }
2001
2002                    st.opcode.reset(op_data.opcode);
2003                    st.opcode.add_imm(x, 31);
2004                    st.opcode.add_reg(op0.id(), 0);
2005                    st.offset_format
2006                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
2007
2008                    st.rm_rel = *op1;
2009                    emit_rel!();
2010                }
2011            }
2012
2013            Encoding::BaseBranchTst => {
2014                let op_data = &BASE_BRANCH_TST[encoding_index];
2015                if isign4 == enc_ops!(Reg, Imm, Label) || isign4 == enc_ops!(Reg, Imm, Imm) {
2016                    let mut x = 0;
2017                    if !check_gp_typex(op0, 3, &mut x) {
2018                        self.last_error = Some(AsmError::InvalidInstruction);
2019                        return;
2020                    }
2021
2022                    if !check_gp_id(op0, 31) {
2023                        self.last_error = Some(AsmError::InvalidOperand);
2024                        return;
2025                    }
2026
2027                    let mut imm = op1.as_::<Imm>().value() as u64;
2028
2029                    st.opcode.reset(op_data.opcode);
2030                    if imm >= 32 {
2031                        if x == 0 {
2032                            self.last_error = Some(AsmError::InvalidOperand);
2033                            return;
2034                        }
2035                        st.opcode.add_imm(x, 31);
2036                        imm &= 0x1F;
2037                    }
2038
2039                    st.opcode.add_reg(op0.id(), 0);
2040                    st.opcode.add_imm(imm as u32, 19);
2041                    st.offset_format
2042                        .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 14, 2);
2043
2044                    st.rm_rel = *op2;
2045                    emit_rel!();
2046                }
2047            }
2048
2049            Encoding::BasePrfm => {
2050                let op_data = &BASE_PRFM[encoding_index];
2051                if isign4 == enc_ops!(Imm, Mem) {
2052                    let m = op1.as_::<Mem>();
2053                    st.rm_rel = *op1;
2054
2055                    let imm_shift = 3u32;
2056
2057                    if op0.as_::<Imm>().value() as u64 > 0x1F {
2058                        self.last_error = Some(AsmError::TooLarge);
2059                        return;
2060                    }
2061
2062                    let offset = m.offset();
2063                    let prfop = op0.as_::<Imm>().value() as u32;
2064
2065                    if m.has_base_reg() {
2066                        if m.has_index() {
2067                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2068                            if opt == 0xFF {
2069                                self.last_error = Some(AsmError::InvalidOperand);
2070                                return;
2071                            }
2072
2073                            let shift = m.shift();
2074                            let s = if shift != 0 { 1 } else { 0 };
2075
2076                            if s != 0 && shift != imm_shift {
2077                                self.last_error = Some(AsmError::InvalidOperand);
2078                                return;
2079                            }
2080
2081                            st.opcode.reset((op_data.register_op as u32) << 21);
2082                            st.opcode.add_imm(opt as u32, 13);
2083                            st.opcode.add_imm(s, 12);
2084                            st.opcode.0 |= 1 << 11;
2085                            st.opcode.add_imm(prfop, 0);
2086                            st.opcode.add_reg(m.base_id(), 5);
2087                            st.opcode.add_reg(m.index_id(), 16);
2088                            emit_op!();
2089                        }
2090
2091                        let offset32 = offset as i32;
2092                        let imm12 = (offset32 as u32) >> imm_shift;
2093
2094                        if imm12 < (1 << 12) && ((imm12 << imm_shift) as i32) == offset32 {
2095                            st.opcode.reset((op_data.s_offset_op as u32) << 22);
2096                            st.opcode.add_imm(imm12, 10);
2097                            st.opcode.add_imm(prfop, 0);
2098                            st.opcode.add_reg(m.base_id(), 5);
2099                            emit_op!();
2100                        }
2101
2102                        if offset32 >= -256 && offset32 < 256 {
2103                            st.opcode.reset((op_data.u_offset_op as u32) << 21);
2104                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2105                            st.opcode.add_imm(prfop, 0);
2106                            st.opcode.add_reg(m.base_id(), 5);
2107                            emit_op!();
2108                        }
2109
2110                        self.last_error = Some(AsmError::InvalidOperand);
2111                        return;
2112                    } else {
2113                        st.opcode.reset((op_data.literal_op as u32) << 24);
2114                        st.opcode.add_imm(prfop, 0);
2115                        st.offset_format
2116                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
2117                        st.rm_rel = *op1;
2118                        emit_rel!();
2119                    }
2120                }
2121            }
2122
2123            Encoding::BaseLdSt => {
2124                let op_data = &BASE_LD_ST[encoding_index];
2125                if isign4 == enc_ops!(Reg, Mem) {
2126                    let m = op1.as_::<Mem>();
2127                    st.rm_rel = *op1;
2128
2129                    let mut x = 0;
2130                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2131                        self.last_error = Some(AsmError::InvalidOperand);
2132                        return;
2133                    }
2134
2135                    if !check_gp_id(op0, 31) {
2136                        self.last_error = Some(AsmError::InvalidOperand);
2137                        return;
2138                    }
2139
2140                    let x_shift_mask = if op_data.u_offset_shift == 2 { 1 } else { 0 };
2141                    let imm_shift = (op_data.u_offset_shift as u32) + (x & x_shift_mask);
2142
2143                    let offset = m.offset();
2144
2145                    if m.has_base_reg() {
2146                        if m.has_index() {
2147                            if m.is_pre_or_post() {
2148                                self.last_error = Some(AsmError::InvalidOperand);
2149                                return;
2150                            }
2151                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
2152                            if opt == 0xFF {
2153                                self.last_error = Some(AsmError::InvalidOperand);
2154                                return;
2155                            }
2156
2157                            let shift = m.shift();
2158                            let s = if shift != 0 { 1 } else { 0 };
2159
2160                            if s != 0 && shift != imm_shift {
2161                                self.last_error = Some(AsmError::InvalidOperand);
2162                                return;
2163                            }
2164
2165                            st.opcode.reset((op_data.register_op as u32) << 21);
2166                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2167                            st.opcode.add_imm(opt as u32, 13);
2168                            st.opcode.add_imm(s, 12);
2169                            st.opcode.0 |= 1 << 11;
2170                            st.opcode.add_reg(op0.id(), 0);
2171                            st.opcode.add_reg(m.base_id(), 5);
2172                            st.opcode.add_reg(m.index_id(), 16);
2173                            emit_op!();
2174                        }
2175
2176                        let offset32 = offset as i32;
2177                        let imm12 = (offset32 as u32) >> imm_shift;
2178
2179                        // Unsigned-offset form has no writeback: never use
2180                        // it for pre/post-indexed operands.
2181                        if m.is_fixed_offset()
2182                            && imm12 < (1 << 12)
2183                            && ((imm12 << imm_shift) as i32) == offset32
2184                        {
2185                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
2186                            st.opcode.xor_imm(x, op_data.x_offset as u32);
2187                            st.opcode.add_imm(imm12, 10);
2188                            st.opcode.add_reg(op0.id(), 0);
2189                            st.opcode.add_reg(m.base_id(), 5);
2190                            emit_op!();
2191                        }
2192
2193                        if offset32 >= -256 && offset32 < 256 {
2194                            // Pre/post-indexed forms share the base opcode
2195                            // with bit 24 clear and carry the mode in bits
2196                            // [11:10] (`11` pre, `01` post); the plain
2197                            // path below keeps its historical encoding.
2198                            let indexed = match m.offset_mode() {
2199                                OffsetMode::PreIndex => Some(0b11),
2200                                OffsetMode::PostIndex => Some(0b01),
2201                                _ => None,
2202                            };
2203                            if let Some(mode) = indexed {
2204                                st.opcode
2205                                    .reset(((op_data.u_offset_op as u32) << 22) & !(1 << 24));
2206                                st.opcode.xor_imm(x, op_data.x_offset as u32);
2207                                st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2208                                st.opcode.add_imm(mode, 10);
2209                                st.opcode.add_reg(op0.id(), 0);
2210                                st.opcode.add_reg(m.base_id(), 5);
2211                                emit_op!();
2212                            } else {
2213                                st.opcode.reset((op_data.u_offset_op as u32) << 22);
2214                                st.opcode.xor_imm(x, op_data.x_offset as u32);
2215                                st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2216                                st.opcode.add_reg(op0.id(), 0);
2217                                st.opcode.add_reg(m.base_id(), 5);
2218                                emit_op!();
2219                            }
2220                        }
2221
2222                        self.last_error = Some(AsmError::InvalidOperand);
2223                        return;
2224                    } else {
2225                        if op_data.literal_op == 0 {
2226                            self.last_error = Some(AsmError::InvalidInstruction);
2227                            return;
2228                        }
2229
2230                        st.opcode.reset((op_data.literal_op as u32) << 24);
2231                        st.opcode.xor_imm(x, op_data.x_offset);
2232                        st.opcode.add_reg(op0.id(), 0);
2233                        st.offset_format
2234                            .reset_to_imm_type(OffsetType::Ldr, 4, 5, 19, 2);
2235                        emit_rel!();
2236                    }
2237                }
2238            }
2239
2240            Encoding::BaseLdpStp => {
2241                let op_data = &BASE_LDP_STP[encoding_index];
2242                if isign4 == enc_ops!(Reg, Reg, Mem) {
2243                    let m = op2.as_::<Mem>();
2244                    st.rm_rel = *op2;
2245
2246                    let mut x = 0;
2247                    if !check_gp_typex2(op0, op1, op_data.reg_type, &mut x) {
2248                        self.last_error = Some(AsmError::InvalidOperand);
2249                        return;
2250                    }
2251
2252                    if !check_gp_id2(op0, op1, 31) {
2253                        self.last_error = Some(AsmError::InvalidOperand);
2254                        return;
2255                    }
2256
2257                    let offset_shift = op_data.offset_shift as u32 + x;
2258                    let offset32 = (m.offset_lo32() as i32) >> offset_shift;
2259
2260                    if (offset32 as u32) << offset_shift != m.offset_lo32() as u32 {
2261                        self.last_error = Some(AsmError::InvalidOperand);
2262                        return;
2263                    }
2264
2265                    const I7_MAX: i32 = (1 << 6) - 1;
2266                    const I7_MIN: i32 = -(1 << 6);
2267
2268                    if offset32 < I7_MIN || offset32 > I7_MAX {
2269                        self.last_error = Some(AsmError::InvalidOperand);
2270                        return;
2271                    }
2272
2273                    if m.is_pre_or_post() && offset32 != 0 {
2274                        if op_data.pre_post_op == 0 {
2275                            self.last_error = Some(AsmError::InvalidInstruction);
2276                            return;
2277                        }
2278
2279                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
2280                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
2281                    } else {
2282                        st.opcode.reset((op_data.offset_op as u32) << 22);
2283                    }
2284                    st.opcode.add_imm(x, op_data.x_offset as u32);
2285                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
2286                    st.opcode.add_reg(op1.id(), 10);
2287                    st.opcode.add_reg(op0.id(), 0);
2288                    st.opcode.add_reg(m.base_id(), 5);
2289                    emit_op!();
2290                }
2291            }
2292
2293            Encoding::BaseStx => {
2294                let op_data = &BASE_STX[encoding_index];
2295                if isign4 == enc_ops!(Reg, Reg, Mem) {
2296                    let m = op2.as_::<Mem>();
2297                    let mut x = 0;
2298                    if !op0.as_::<Reg>().is_gp32() || !check_gp_typex(op1, op_data.reg_type, &mut x)
2299                    {
2300                        self.last_error = Some(AsmError::InvalidOperand);
2301                        return;
2302                    }
2303                    if !check_gp_id2(op0, op1, 31) {
2304                        self.last_error = Some(AsmError::InvalidOperand);
2305                        return;
2306                    }
2307                    st.opcode.reset(op_data.opcode());
2308                    st.opcode.add_imm(x, op_data.x_offset as _);
2309                    st.opcode.add_reg(op0.id(), 16);
2310                    st.opcode.add_reg(op1.id(), 0);
2311                    st.rm_rel = *op2;
2312                    st.opcode.add_reg(m.base_id(), 5);
2313                    emit_op!();
2314                }
2315            }
2316
2317            Encoding::BaseLdxp => {
2318                let op_data = &BASE_LDXP[encoding_index];
2319                if isign4 == enc_ops!(Reg, Reg, Mem) {
2320                    let m = op2.as_::<Mem>();
2321                    let mut x = 0;
2322                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2323                    {
2324                        self.last_error = Some(AsmError::InvalidOperand);
2325                        return;
2326                    }
2327                    if !check_gp_id2(op0, op1, 31) {
2328                        self.last_error = Some(AsmError::InvalidOperand);
2329                        return;
2330                    }
2331                    st.opcode.reset(op_data.opcode());
2332                    st.opcode.add_imm(x, op_data.x_offset as _);
2333                    st.opcode.add_reg(op1.id(), 10);
2334                    st.opcode.add_reg(op0.id(), 0);
2335                    st.rm_rel = *op2;
2336                    st.opcode.add_reg(m.base_id(), 5);
2337                    emit_op!();
2338                }
2339            }
2340
2341            Encoding::BaseStxp => {
2342                let op_data = &BASE_STXP[encoding_index];
2343                if isign4 == enc_ops!(Reg, Reg, Reg, Mem) {
2344                    let m = op3.as_::<Mem>();
2345                    let mut x = 0;
2346                    if !op0.as_::<Reg>().is_gp32()
2347                        || !check_gp_typex(op1, op_data.reg_type, &mut x)
2348                        || !check_signature!(op1, op2)
2349                    {
2350                        self.last_error = Some(AsmError::InvalidOperand);
2351                        return;
2352                    }
2353                    if !check_gp_id3(op0, op1, op2, 31) {
2354                        self.last_error = Some(AsmError::InvalidOperand);
2355                        return;
2356                    }
2357                    st.opcode.reset(op_data.opcode());
2358                    st.opcode.add_imm(x, op_data.x_offset as _);
2359                    st.opcode.add_reg(op0.id(), 16);
2360                    st.opcode.add_reg(op2.id(), 10);
2361                    st.opcode.add_reg(op1.id(), 0);
2362                    st.rm_rel = *op3;
2363                    st.opcode.add_reg(m.base_id(), 5);
2364                    emit_op!();
2365                }
2366            }
2367
2368            Encoding::BaseRMNoImm => {
2369                let op_data = &BASE_RM_NO_IMM[encoding_index];
2370                if isign4 == enc_ops!(Reg, Mem) {
2371                    let m = op1.as_::<Mem>();
2372                    let mut x = 0;
2373                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2374                        self.last_error = Some(AsmError::InvalidOperand);
2375                        return;
2376                    }
2377                    if !check_gp_id(op0, op_data.reg_hi_id) {
2378                        self.last_error = Some(AsmError::InvalidOperand);
2379                        return;
2380                    }
2381                    st.opcode.reset(op_data.opcode());
2382                    st.opcode.add_imm(x, op_data.x_offset as _);
2383                    st.opcode.add_reg(op0.id(), 0);
2384                    st.rm_rel = *op1;
2385
2386                    emit_mem_base_no_imm_rn5!();
2387                }
2388            }
2389
2390            Encoding::BaseRMSImm9 => {
2391                let op_data = &BASE_RM_SIMM9[encoding_index];
2392                if isign4 == enc_ops!(Reg, Mem) {
2393                    let m = op1.as_::<Mem>();
2394                    let mut x = 0;
2395                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2396                        self.last_error = Some(AsmError::InvalidOperand);
2397                        return;
2398                    }
2399                    if !check_gp_id(op0, op_data.reg_hi_id) {
2400                        self.last_error = Some(AsmError::InvalidOperand);
2401                        return;
2402                    }
2403                    if m.has_base_reg() && !m.has_index() {
2404                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2405                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2406                            self.last_error = Some(AsmError::InvalidOperand);
2407                            return;
2408                        }
2409                        if offset32 < -256 || offset32 > 255 {
2410                            self.last_error = Some(AsmError::InvalidOperand);
2411                            return;
2412                        }
2413                        if m.is_fixed_offset() {
2414                            st.opcode.reset(op_data.offset_op());
2415                        } else {
2416                            st.opcode.reset(op_data.pre_post_op());
2417                            st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2418                        }
2419                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2420                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
2421                        st.opcode.add_reg(op0.id(), 0);
2422                        st.opcode.add_reg(m.base_id(), 5);
2423                        emit_op!();
2424                    }
2425                    self.last_error = Some(AsmError::InvalidOperand);
2426                    return;
2427                }
2428            }
2429
2430            Encoding::BaseRMSImm10 => {
2431                let op_data = &BASE_RM_SIMM10[encoding_index];
2432                if isign4 == enc_ops!(Reg, Mem) {
2433                    let m = op1.as_::<Mem>();
2434                    let mut x = 0;
2435                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2436                        self.last_error = Some(AsmError::InvalidOperand);
2437                        return;
2438                    }
2439                    if !check_gp_id(op0, op_data.reg_hi_id) {
2440                        self.last_error = Some(AsmError::InvalidOperand);
2441                        return;
2442                    }
2443                    if m.has_base_reg() && !m.has_index() {
2444                        let offset32 = m.offset() as i32 >> op_data.imm_shift;
2445                        if (offset32 << op_data.imm_shift) != m.offset() as i32 {
2446                            self.last_error = Some(AsmError::InvalidOperand);
2447                            return;
2448                        }
2449                        if offset32 < -512 || offset32 > 511 {
2450                            self.last_error = Some(AsmError::InvalidOperand);
2451                            return;
2452                        }
2453                        let offset32 = (offset32 as u32) & 0x3FF;
2454                        st.opcode.reset(op_data.opcode());
2455                        st.opcode.xor_imm(m.is_pre_index() as u32, 11);
2456                        st.opcode.xor_imm(x, op_data.x_offset as u32);
2457                        st.opcode.add_imm(offset32 >> 9, 22);
2458                        st.opcode.add_imm(offset32, 12);
2459                        st.opcode.add_reg(op0.id(), 0);
2460                        st.opcode.add_reg(m.base_id(), 5);
2461                        emit_op!();
2462                    }
2463                    self.last_error = Some(AsmError::InvalidOperand);
2464                    return;
2465                }
2466            }
2467
2468            Encoding::BaseAtomicOp => {
2469                let op_data = &BASE_ATOMIC_OP[encoding_index];
2470                if isign4 == enc_ops!(Reg, Reg, Mem) {
2471                    let m = op2.as_::<Mem>();
2472                    let mut x = 0;
2473                    if !check_gp_typex(op0, op_data.reg_type, &mut x) || !check_signature!(op0, op1)
2474                    {
2475                        self.last_error = Some(AsmError::InvalidOperand);
2476                        return;
2477                    }
2478                    if !check_gp_id2(op0, op1, 31) {
2479                        self.last_error = Some(AsmError::InvalidOperand);
2480                        return;
2481                    }
2482                    st.opcode.reset(op_data.opcode());
2483                    st.opcode.add_imm(x, op_data.x_offset as _);
2484                    st.opcode.add_reg(op0.id(), 16);
2485                    st.opcode.add_reg(op1.id(), 0);
2486                    st.rm_rel = *op2;
2487                    st.opcode.add_reg(m.base_id(), 5);
2488                    emit_op!();
2489                }
2490            }
2491
2492            Encoding::BaseAtomicSt => {
2493                let op_data = &BASE_ATOMIC_ST[encoding_index];
2494                if isign4 == enc_ops!(Reg, Mem) {
2495                    let m = op1.as_::<Mem>();
2496                    let mut x = 0;
2497                    if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2498                        self.last_error = Some(AsmError::InvalidOperand);
2499                        return;
2500                    }
2501                    if !check_gp_id(op0, 31) {
2502                        self.last_error = Some(AsmError::InvalidOperand);
2503                        return;
2504                    }
2505                    st.opcode.reset(op_data.opcode());
2506                    st.opcode.add_imm(x, op_data.x_offset as _);
2507                    st.opcode.add_reg(op0.id(), 16);
2508                    st.opcode.add_reg(31, 0);
2509                    st.rm_rel = *op1;
2510                    st.opcode.add_reg(m.base_id(), 5);
2511                    emit_op!();
2512                }
2513            }
2514
2515            Encoding::BaseAtomicCasp => {
2516                let op_data = &BASE_ATOMIC_CASP[encoding_index];
2517                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2518                    let op4 = *ops.get(4).unwrap_or(&NOREG);
2519                    if op4.is_mem() {
2520                        let m = op4.as_::<Mem>();
2521                        let mut x = 0;
2522                        if !check_gp_typex(op0, op_data.reg_type, &mut x) {
2523                            self.last_error = Some(AsmError::InvalidOperand);
2524                            return;
2525                        }
2526                        if !check_signature!(op0, op1, op2, op3) {
2527                            self.last_error = Some(AsmError::InvalidOperand);
2528                            return;
2529                        }
2530                        let id0 = op0.id();
2531                        let id2 = op2.id();
2532                        if (id0 & 1) != 0 || (id2 & 1) != 0 || id0 == id2 || id0 > 30 || id2 > 30 {
2533                            self.last_error = Some(AsmError::InvalidOperand);
2534                            return;
2535                        }
2536                        if (id0 + 1) != op1.id() || (id2 + 1) != op3.id() {
2537                            self.last_error = Some(AsmError::InvalidOperand);
2538                            return;
2539                        }
2540                        st.opcode.reset(op_data.opcode());
2541                        st.opcode.add_imm(x, op_data.x_offset as _);
2542                        st.opcode.add_reg(op0.id(), 16);
2543                        st.opcode.add_reg(op2.id(), 0);
2544                        st.rm_rel = *op4;
2545                        emit_mem_base_no_imm_rn5!();
2546                    }
2547                }
2548            }
2549
2550            Encoding::FSimdSV => {
2551                let op_data = &F_SIMD_SV[encoding_index];
2552
2553                if isign4 == enc_ops!(Reg, Reg) {
2554                    let q = op1.as_::<Reg>().typ() as u32;
2555                    let q = if q >= RegType::Vec64 as u32 {
2556                        q - RegType::Vec64 as u32
2557                    } else {
2558                        u32::MAX
2559                    };
2560                    if q > 1 {
2561                        self.last_error = Some(AsmError::InvalidInstruction);
2562                        return;
2563                    }
2564
2565                    if op0.as_::<Vec>().has_element_type() {
2566                        self.last_error = Some(AsmError::InvalidInstruction);
2567                        return;
2568                    }
2569
2570                    let sz = op0.as_::<Reg>().typ() as u32;
2571                    let sz = if sz >= RegType::Vec16 as u32 {
2572                        sz - RegType::Vec16 as u32
2573                    } else {
2574                        u32::MAX
2575                    };
2576                    let element_sz = op1.as_::<Vec>().element_type() as u32;
2577                    let element_sz = if element_sz >= VecElementType::H as u32 {
2578                        element_sz - VecElementType::H as u32
2579                    } else {
2580                        u32::MAX
2581                    };
2582
2583                    if (sz | element_sz) > 1 || sz != element_sz {
2584                        self.last_error = Some(AsmError::InvalidInstruction);
2585                        return;
2586                    }
2587
2588                    if sz != 0 && q == 0 {
2589                        self.last_error = Some(AsmError::InvalidInstruction);
2590                        return;
2591                    }
2592
2593                    st.opcode.reset((op_data.opcode as u32) << 10);
2594                    if sz == 0 {
2595                        st.opcode.0 ^= 1 << 29;
2596                    }
2597                    st.opcode.add_imm(q, 30);
2598                    st.opcode.add_reg(op0.id(), 0);
2599                    st.opcode.add_reg(op1.id(), 5);
2600                    emit_op!();
2601                }
2602            }
2603
2604            Encoding::FSimdVV => {
2605                let op_data = &F_SIMD_VV[encoding_index];
2606
2607                if isign4 == enc_ops!(Reg, Reg) {
2608                    if !match_signature2(op0, op1, inst_flags as u32) {
2609                        self.last_error = Some(AsmError::InvalidInstruction);
2610                        return;
2611                    }
2612
2613                    if let Some(fp_opcode) = pick_fp_opcode(
2614                        op0.as_::<Vec>(),
2615                        op_data.scalar_op(),
2616                        op_data.scalar_hf(),
2617                        op_data.vector_op(),
2618                        op_data.vector_hf(),
2619                        &mut 0,
2620                    ) {
2621                        st.opcode.reset(fp_opcode.0);
2622                        emit_rd0_rn5!();
2623                    }
2624
2625                    self.last_error = Some(AsmError::InvalidInstruction);
2626                    return;
2627                }
2628            }
2629
2630            Encoding::FSimdVVV => {
2631                let op_data = &F_SIMD_VVV[encoding_index];
2632
2633                if isign4 == enc_ops!(Reg, Reg, Reg) {
2634                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2635                        self.last_error = Some(AsmError::InvalidInstruction);
2636                        return;
2637                    }
2638
2639                    if let Some(fp_opcode) = pick_fp_opcode(
2640                        op0.as_::<Vec>(),
2641                        op_data.scalar_op(),
2642                        op_data.scalar_hf(),
2643                        op_data.vector_op(),
2644                        op_data.vector_hf(),
2645                        &mut 0,
2646                    ) {
2647                        st.opcode.reset(fp_opcode.0);
2648                        emit_rd0_rn5_rm16!();
2649                    }
2650
2651                    self.last_error = Some(AsmError::InvalidInstruction);
2652                    return;
2653                }
2654            }
2655
2656            Encoding::FSimdVVVe => {
2657                let op_data = &F_SIMD_VVVE[encoding_index];
2658
2659                if isign4 == enc_ops!(Reg, Reg, Reg) {
2660                    if !op2.as_::<Vec>().has_element_index() {
2661                        if !match_signature3(op0, op1, op2, inst_flags as u32) {
2662                            self.last_error = Some(AsmError::InvalidInstruction);
2663                            return;
2664                        }
2665
2666                        if let Some(fp_opcode) = pick_fp_opcode(
2667                            op0.as_::<Vec>(),
2668                            op_data.scalar_op(),
2669                            op_data.scalar_hf(),
2670                            op_data.vector_op(),
2671                            op_data.vector_hf(),
2672                            &mut 0,
2673                        ) {
2674                            st.opcode.reset(fp_opcode.0);
2675
2676                            emit_rd0_rn5_rm16!();
2677                        }
2678
2679                        self.last_error = Some(AsmError::InvalidInstruction);
2680                        return;
2681                    } else {
2682                        if !match_signature2(op0, op1, inst_flags as u32) {
2683                            self.last_error = Some(AsmError::InvalidInstruction);
2684                            return;
2685                        }
2686
2687                        let q = op1.as_::<Reg>().is_vec128() as u32;
2688                        let mut sz = 0;
2689                        if let Some((fp_opcode)) = pick_fp_opcode(
2690                            op0.as_::<Vec>(),
2691                            op_data.element_scalar_op(),
2692                            5,
2693                            op_data.element_vector_op(),
2694                            5,
2695                            &mut sz,
2696                        ) {
2697                            if sz == 0 && op2.as_::<Reg>().id() > 15 {
2698                                self.last_error = Some(AsmError::InvalidOperand);
2699                                return;
2700                            }
2701
2702                            let element_index = op2.as_::<Vec>().element_index();
2703                            if element_index > (7u32 >> sz) {
2704                                self.last_error = Some(AsmError::InvalidOperand);
2705                                return;
2706                            }
2707
2708                            let hlm = element_index << sz;
2709                            st.opcode.reset(fp_opcode.0);
2710                            st.opcode.add_imm(q, 30);
2711                            st.opcode.add_imm(hlm & 3, 20);
2712                            st.opcode.add_imm(hlm >> 2, 11);
2713                            emit_rd0_rn5_rm16!();
2714                        }
2715
2716                        self.last_error = Some(AsmError::InvalidInstruction);
2717                        return;
2718                    }
2719                }
2720            }
2721
2722            Encoding::FSimdVVVV => {
2723                let op_data = &F_SIMD_VVVV[encoding_index];
2724
2725                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
2726                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
2727                        self.last_error = Some(AsmError::InvalidInstruction);
2728                        return;
2729                    }
2730
2731                    if let Some(fp_opcode) = pick_fp_opcode(
2732                        op0.as_::<Vec>(),
2733                        op_data.scalar_op(),
2734                        op_data.scalar_hf(),
2735                        op_data.vector_op(),
2736                        op_data.vector_hf(),
2737                        &mut 0,
2738                    ) {
2739                        st.opcode.reset(fp_opcode.0);
2740                        emit_rd0_rn5_rm16_ra10!();
2741                    }
2742
2743                    self.last_error = Some(AsmError::InvalidInstruction);
2744                    return;
2745                }
2746            }
2747
2748            Encoding::SimdFcadd => {
2749                let op_data = &SIMD_FCADD[encoding_index];
2750
2751                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2752                    if !check_signature!(op0, op1, op2) || op0.as_::<Vec>().has_element_index() {
2753                        self.last_error = Some(AsmError::InvalidInstruction);
2754                        return;
2755                    }
2756
2757                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2758                    if q > 1 {
2759                        self.last_error = Some(AsmError::InvalidInstruction);
2760                        return;
2761                    }
2762
2763                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2764                    sz = sz.wrapping_sub(1);
2765                    if sz == 0 || sz > 3 {
2766                        self.last_error = Some(AsmError::InvalidInstruction);
2767                        return;
2768                    }
2769
2770                    let mut rot = 0u32;
2771                    let imm_val = op3.as_::<Imm>().value();
2772                    if imm_val == 270 {
2773                        rot = 1;
2774                    } else if imm_val != 90 {
2775                        self.last_error = Some(AsmError::InvalidOperand);
2776                        return;
2777                    }
2778
2779                    st.opcode.reset(op_data.opcode());
2780                    st.opcode.add_imm(q, 30);
2781                    st.opcode.add_imm(sz, 22);
2782                    st.opcode.add_imm(rot, 12);
2783                    emit_rd0_rn5_rm16!();
2784                }
2785            }
2786
2787            Encoding::SimdFccmpFccmpe => {
2788                let op_data = &SIMD_FCCMP_FCCMPE[encoding_index];
2789
2790                if isign4 == enc_ops!(Reg, Reg, Imm, Imm) {
2791                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2792                    if sz > 2 {
2793                        self.last_error = Some(AsmError::InvalidInstruction);
2794                        return;
2795                    }
2796
2797                    if !check_signature!(op0, op1) || op0.as_::<Vec>().has_element_type() {
2798                        self.last_error = Some(AsmError::InvalidInstruction);
2799                        return;
2800                    }
2801
2802                    let nzcv = op2.as_::<Imm>().value() as u64;
2803                    let cond = op3.as_::<Imm>().value() as u64;
2804
2805                    if (nzcv | cond) > 0xF {
2806                        self.last_error = Some(AsmError::InvalidOperand);
2807                        return;
2808                    }
2809
2810                    let type_field = sz.wrapping_sub(1) & 0x3;
2811
2812                    st.opcode.reset(op_data.opcode());
2813                    st.opcode.add_imm(type_field, 22);
2814                    st.opcode
2815                        .add_imm(cond_code_to_opcode_field(cond as u32), 12);
2816                    st.opcode.add_imm(nzcv as u32, 0);
2817                    emit_rn5_rm16!();
2818                }
2819            }
2820
2821            Encoding::SimdFcm => {
2822                let op_data = &SIMD_FCM[encoding_index];
2823
2824                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.has_register_op() {
2825                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
2826                        self.last_error = Some(AsmError::InvalidInstruction);
2827                        return;
2828                    }
2829
2830                    if let Some(fp_opcode) = pick_fp_opcode(
2831                        op0.as_::<Vec>(),
2832                        op_data.register_scalar_op(),
2833                        op_data.register_scalar_hf(),
2834                        op_data.register_vector_op(),
2835                        op_data.register_vector_hf(),
2836                        &mut 0,
2837                    ) {
2838                        st.opcode.reset(fp_opcode.0);
2839                        emit_rd0_rn5_rm16!();
2840                    }
2841
2842                    self.last_error = Some(AsmError::InvalidInstruction);
2843                    return;
2844                }
2845
2846                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.has_zero_op() {
2847                    if !check_signature!(op0, op1) {
2848                        self.last_error = Some(AsmError::InvalidInstruction);
2849                        return;
2850                    }
2851
2852                    if op2.as_::<Imm>().value() != 0 {
2853                        self.last_error = Some(AsmError::InvalidOperand);
2854                        return;
2855                    }
2856
2857                    if let Some(fp_opcode) = pick_fp_opcode(
2858                        op0.as_::<Vec>(),
2859                        op_data.zero_scalar_op(),
2860                        5,
2861                        op_data.zero_vector_op(),
2862                        5,
2863                        &mut 0,
2864                    ) {
2865                        st.opcode.reset(fp_opcode.0);
2866                        emit_rd0_rn5!();
2867                    }
2868
2869                    self.last_error = Some(AsmError::InvalidInstruction);
2870                    return;
2871                }
2872            }
2873
2874            Encoding::SimdFcmla => {
2875                let op_data = &SIMD_FCMLA[encoding_index];
2876
2877                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2878                    if !check_signature!(op0, op1) {
2879                        self.last_error = Some(AsmError::InvalidInstruction);
2880                        return;
2881                    }
2882
2883                    let q = (op0.as_::<Reg>().is_vec128() as u32).wrapping_sub(1);
2884                    if q > 1 {
2885                        self.last_error = Some(AsmError::InvalidInstruction);
2886                        return;
2887                    }
2888
2889                    let mut sz = op0.as_::<Vec>().element_type() as u32;
2890                    sz = sz.wrapping_sub(1);
2891                    if sz == 0 || sz > 3 {
2892                        self.last_error = Some(AsmError::InvalidInstruction);
2893                        return;
2894                    }
2895
2896                    let mut rot = 0u32;
2897                    match op3.as_::<Imm>().value() {
2898                        0 => rot = 0,
2899                        90 => rot = 1,
2900                        180 => rot = 2,
2901                        270 => rot = 3,
2902                        _ => {
2903                            self.last_error = Some(AsmError::InvalidOperand);
2904                            return;
2905                        }
2906                    }
2907
2908                    if !op2.as_::<Vec>().has_element_index() {
2909                        if !check_signature!(op1, op2) {
2910                            self.last_error = Some(AsmError::InvalidInstruction);
2911                            return;
2912                        }
2913
2914                        st.opcode.reset(op_data.regular_op());
2915                        st.opcode.add_imm(q, 30);
2916                        st.opcode.add_imm(sz, 22);
2917                        st.opcode.add_imm(rot, 11);
2918                        emit_rd0_rn5_rm16!();
2919                    } else {
2920                        if op0.as_::<Vec>().element_type() != op2.as_::<Vec>().element_type() {
2921                            self.last_error = Some(AsmError::InvalidOperand);
2922                            return;
2923                        }
2924
2925                        if !((sz == 1) || (q == 1 && sz == 2)) {
2926                            self.last_error = Some(AsmError::InvalidOperand);
2927                            return;
2928                        }
2929
2930                        let element_index = op2.as_::<Vec>().element_index();
2931                        let hl_field_shift = if sz == 1 { 0u32 } else { 1u32 };
2932                        let max_element_index = if q == 1 && sz == 1 { 3u32 } else { 1u32 };
2933
2934                        if element_index > max_element_index {
2935                            self.last_error = Some(AsmError::InvalidOperand);
2936                            return;
2937                        }
2938
2939                        let hl = element_index << hl_field_shift;
2940
2941                        st.opcode.reset(op_data.element_op());
2942                        st.opcode.add_imm(q, 30);
2943                        st.opcode.add_imm(sz, 22);
2944                        st.opcode.add_imm(hl & 1u32, 21);
2945                        st.opcode.add_imm(hl >> 1, 11);
2946                        st.opcode.add_imm(rot, 13);
2947                        emit_rd0_rn5_rm16!();
2948                    }
2949                }
2950            }
2951
2952            Encoding::SimdFcmpFcmpe => {
2953                let op_data = &SIMD_FCMP_FCMPE[encoding_index];
2954
2955                let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2956                let type_field = sz.wrapping_sub(1) & 0x3u32;
2957
2958                if sz > 2 {
2959                    self.last_error = Some(AsmError::InvalidInstruction);
2960                    return;
2961                }
2962
2963                if op0.as_::<Vec>().has_element_type() {
2964                    self.last_error = Some(AsmError::InvalidInstruction);
2965                    return;
2966                }
2967
2968                st.opcode.reset(op_data.opcode());
2969                st.opcode.add_imm(type_field, 22);
2970
2971                if isign4 == enc_ops!(Reg, Reg) {
2972                    if !check_signature!(op0, op1) {
2973                        self.last_error = Some(AsmError::InvalidInstruction);
2974                        return;
2975                    }
2976
2977                    st.opcode.add_reg(op0.id(), 5);
2978                    st.opcode.add_reg(op1.id(), 16);
2979                    emit_op!();
2980                } else if isign4 == enc_ops!(Reg, Imm) {
2981                    if op1.as_::<Imm>().value() != 0 {
2982                        self.last_error = Some(AsmError::InvalidOperand);
2983                        return;
2984                    }
2985
2986                    st.opcode.0 |= 0x8;
2987                    emit_rd0_rn5!();
2988                }
2989            }
2990
2991            Encoding::SimdFcsel => {
2992                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
2993                    if !check_signature!(op0, op1, op2) {
2994                        self.last_error = Some(AsmError::InvalidInstruction);
2995                        return;
2996                    }
2997
2998                    let sz = (op0.as_::<Reg>().typ() as u32).wrapping_sub(RegType::Vec16 as u32);
2999                    let type_field = sz.wrapping_sub(1) & 0x3u32;
3000
3001                    if sz > 2 || op0.as_::<Vec>().has_element_type() {
3002                        self.last_error = Some(AsmError::InvalidInstruction);
3003                        return;
3004                    }
3005
3006                    let cond = op3.as_::<Imm>().value() as u32;
3007                    if cond > 0xFu32 {
3008                        self.last_error = Some(AsmError::InvalidImmediate);
3009                        return;
3010                    }
3011
3012                    st.opcode.reset(0b00011110001000000000110000000000u32);
3013                    st.opcode.add_imm(type_field, 22);
3014                    st.opcode.add_imm(cond, 12);
3015                    emit_rd0_rn5_rm16!();
3016                }
3017            }
3018
3019            Encoding::SimdFcvt => {
3020                if isign4 == enc_ops!(Reg, Reg) {
3021                    let dst_sz =
3022                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3023                    let src_sz =
3024                        (op1.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3025
3026                    if (dst_sz | src_sz) > 3 {
3027                        self.last_error = Some(AsmError::InvalidInstruction);
3028                        return;
3029                    }
3030
3031                    if op0.as_::<Vec>().has_element_type() || op1.as_::<Vec>().has_element_type() {
3032                        self.last_error = Some(AsmError::InvalidInstruction);
3033                        return;
3034                    }
3035
3036                    // Table that provides 'type' and 'opc' according to the dst/src combination.
3037                    let table: [u8; 16] = [
3038                        0xFFu8, // H <- H (Invalid).
3039                        0x03u8, // H <- S (type=00 opc=11).
3040                        0x13u8, // H <- D (type=01 opc=11).
3041                        0xFFu8, // H <- Q (Invalid).
3042                        0x30u8, // S <- H (type=11 opc=00).
3043                        0xFFu8, // S <- S (Invalid).
3044                        0x10u8, // S <- D (type=01 opc=00).
3045                        0xFFu8, // S <- Q (Invalid).
3046                        0x31u8, // D <- H (type=11 opc=01).
3047                        0x01u8, // D <- S (type=00 opc=01).
3048                        0xFFu8, // D <- D (Invalid).
3049                        0xFFu8, // D <- Q (Invalid).
3050                        0xFFu8, // Q <- H (Invalid).
3051                        0xFFu8, // Q <- S (Invalid).
3052                        0xFFu8, // Q <- D (Invalid).
3053                        0xFFu8, // Q <- Q (Invalid).
3054                    ];
3055
3056                    let type_opc = table[((dst_sz << 2) | src_sz) as usize];
3057                    if type_opc == 0xFFu8 {
3058                        self.last_error = Some(AsmError::InvalidInstruction);
3059                        return;
3060                    }
3061
3062                    st.opcode.reset(0b0001111000100010010000 << 10);
3063                    st.opcode.add_imm((type_opc as u32) >> 4, 22);
3064                    st.opcode.add_imm((type_opc as u32) & 15, 15);
3065                    emit_rd0_rn5!();
3066                }
3067            }
3068
3069            Encoding::SimdFcvtLN => {
3070                let op_data = &SIMD_FCVT_LN[encoding_index];
3071
3072                if isign4 == enc_ops!(Reg, Reg) {
3073                    // Scalar form - only FCVTXN.
3074                    if op0.as_::<Vec>().is_vec32() && op1.as_::<Vec>().is_vec64() {
3075                        if op_data.has_scalar() == 0 {
3076                            self.last_error = Some(AsmError::InvalidInstruction);
3077                            return;
3078                        }
3079
3080                        if op0.as_::<Vec>().has_element_type()
3081                            || op1.as_::<Vec>().has_element_type()
3082                        {
3083                            self.last_error = Some(AsmError::InvalidInstruction);
3084                            return;
3085                        }
3086
3087                        st.opcode.reset(op_data.scalar_op());
3088                        st.opcode.0 |= 0x400000; // sz bit must be 1
3089                        emit_rd0_rn5!();
3090                        return;
3091                    }
3092
3093                    st.opcode.reset(op_data.vector_op());
3094
3095                    let is_long = (inst_flags & InstFlag::Long as u16) != 0;
3096                    let (rl, rn) = if is_long {
3097                        (op0.as_::<Vec>(), op1.as_::<Vec>())
3098                    } else {
3099                        (op1.as_::<Vec>(), op0.as_::<Vec>())
3100                    };
3101
3102                    let q = (rn.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3103                    if (st.opcode.has_q() as u32) != q {
3104                        self.last_error = Some(AsmError::InvalidInstruction);
3105                        return;
3106                    }
3107
3108                    if rl.is_vec_s4()
3109                        && rn.element_type() == VecElementType::H
3110                        && op_data.is_cvtxn() == 0
3111                    {
3112                        emit_rd0_rn5!();
3113                        return;
3114                    }
3115
3116                    if rl.is_vec_d2() && rn.element_type() == VecElementType::S {
3117                        st.opcode.0 |= 0x400000;
3118                        emit_rd0_rn5!();
3119                        return;
3120                    }
3121
3122                    self.last_error = Some(AsmError::InvalidInstruction);
3123                    return;
3124                }
3125            }
3126
3127            Encoding::SimdFcvtSV => {
3128                let op_data = &SIMD_FCVT_SV[encoding_index];
3129
3130                // So we can support both IntToFloat and FloatToInt conversions.
3131                let is_float_to_int = op_data.is_float_to_int();
3132                let (op_gp, op_vec) = if is_float_to_int != 0 {
3133                    (&op0, &op1)
3134                } else {
3135                    (&op1, &op0)
3136                };
3137
3138                if isign4 == enc_ops!(Reg, Reg) {
3139                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3140                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3141                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3142                            .wrapping_sub(RegType::Vec16 as u32);
3143
3144                        if type_field > 2u32 {
3145                            self.last_error = Some(AsmError::InvalidInstruction);
3146                            return;
3147                        }
3148
3149                        let type_val = (type_field - 1u32) & 0x3;
3150                        st.opcode.reset(op_data.general_op());
3151                        st.opcode.add_imm(type_val, 22);
3152                        st.opcode.add_imm(x, 31);
3153                        emit_rd0_rn5!();
3154                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3155                        if !check_signature!(op0, op1) {
3156                            self.last_error = Some(AsmError::InvalidInstruction);
3157                            return;
3158                        }
3159
3160                        if let Some(fp_opcode) = pick_fp_opcode(
3161                            op0.as_::<Vec>(),
3162                            op_data.scalar_int_op(),
3163                            5,
3164                            op_data.vector_int_op(),
3165                            5,
3166                            &mut 0,
3167                        ) {
3168                            st.opcode.reset(fp_opcode.0);
3169                            emit_rd0_rn5!();
3170                        } else {
3171                            self.last_error = Some(AsmError::InvalidInstruction);
3172                            return;
3173                        }
3174                    }
3175                } else if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.is_fixed_point() {
3176                    let scale_val = op2.as_::<Imm>().value() as u32;
3177                    if scale_val >= 64 {
3178                        self.last_error = Some(AsmError::InvalidImmediate);
3179                        return;
3180                    }
3181
3182                    if scale_val == 0 {
3183                        self.last_error = Some(AsmError::InvalidOperand);
3184                        return;
3185                    }
3186
3187                    if op_gp.as_::<Reg>().is_gp() && op_vec.as_::<Reg>().is_vec() {
3188                        let x = op_gp.as_::<Reg>().is_gp64() as u32;
3189                        let type_field = (op_vec.as_::<Reg>().reg_type() as u32)
3190                            .wrapping_sub(RegType::Vec16 as u32);
3191
3192                        let scale_limit = 32u32 << x;
3193                        if scale_val > scale_limit {
3194                            self.last_error = Some(AsmError::InvalidOperand);
3195                            return;
3196                        }
3197
3198                        let type_val = (type_field - 1u32) & 0x3;
3199                        st.opcode.reset(op_data.general_op() ^ 0x200000);
3200                        st.opcode.add_imm(type_val, 22);
3201                        st.opcode.add_imm(x, 31);
3202                        st.opcode.add_imm(64u32 - scale_val, 10);
3203                        emit_rd0_rn5!();
3204                    } else if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
3205                        if !check_signature!(op0, op1) {
3206                            self.last_error = Some(AsmError::InvalidInstruction);
3207                            return;
3208                        }
3209
3210                        let mut sz = 0u32;
3211                        if let Some(fp_opcode) = pick_fp_opcode(
3212                            op0.as_::<Vec>(),
3213                            op_data.scalar_fp_op(),
3214                            5,
3215                            op_data.vector_fp_op(),
3216                            5,
3217                            &mut sz,
3218                        ) {
3219                            let scale_limit = 16u32 << sz;
3220                            if scale_val > scale_limit {
3221                                self.last_error = Some(AsmError::InvalidOperand);
3222                                return;
3223                            }
3224
3225                            let imm = (!(scale_val) + 1) & ((1u32 << (sz + 4 + 1)) - 1);
3226                            st.opcode.reset(fp_opcode.0);
3227                            st.opcode.add_imm(imm, 16);
3228                            emit_rd0_rn5!();
3229                        } else {
3230                            self.last_error = Some(AsmError::InvalidInstruction);
3231                            return;
3232                        }
3233                    }
3234                }
3235            }
3236
3237            Encoding::SimdFmlal => {
3238                let op_data = &SIMD_FMLAL[encoding_index];
3239
3240                if isign4 == enc_ops!(Reg, Reg, Reg) {
3241                    let mut q =
3242                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3243                    let q_is_optional = op_data.optional_q() != 0;
3244
3245                    if q_is_optional {
3246                        if q > 1 {
3247                            self.last_error = Some(AsmError::InvalidInstruction);
3248                            return;
3249                        }
3250                    } else {
3251                        if q != 1 {
3252                            self.last_error = Some(AsmError::InvalidInstruction);
3253                            return;
3254                        }
3255
3256                        q = 0;
3257                    }
3258
3259                    if (op0.as_::<Reg>().reg_type() as u32)
3260                        != (op1.as_::<Reg>().reg_type() as u32) + if q_is_optional { 1 } else { 0 }
3261                        || (op0.as_::<Vec>().element_type() as u32) != op_data.ta as u32
3262                        || (op1.as_::<Vec>().element_type() as u32) != op_data.tb as u32
3263                    {
3264                        self.last_error = Some(AsmError::InvalidInstruction);
3265                        return;
3266                    }
3267
3268                    if !op2.as_::<Vec>().has_element_index() {
3269                        if !check_signature!(&op1, &op2) {
3270                            self.last_error = Some(AsmError::InvalidInstruction);
3271                            return;
3272                        }
3273
3274                        st.opcode.reset(op_data.vector_op());
3275                        st.opcode.add_imm(q, 30);
3276                        emit_rd0_rn5_rm16!();
3277                    } else {
3278                        if (op2.as_::<Vec>().element_type() as u32) != op_data.t_element as u32 {
3279                            self.last_error = Some(AsmError::InvalidInstruction);
3280                            return;
3281                        }
3282
3283                        if op2.as_::<Reg>().id() > 15 {
3284                            self.last_error = Some(AsmError::InvalidOperand);
3285                            return;
3286                        }
3287
3288                        let element_index = op2.as_::<Vec>().element_index();
3289                        if element_index > 7u32 {
3290                            self.last_error = Some(AsmError::InvalidOperand);
3291                            return;
3292                        }
3293
3294                        st.opcode.reset(op_data.element_op());
3295                        st.opcode.add_imm(q, 30);
3296                        st.opcode.add_imm(element_index & 3u32, 20);
3297                        st.opcode.add_imm(element_index >> 2, 11);
3298                        emit_rd0_rn5_rm16!();
3299                    }
3300                }
3301            }
3302
3303            Encoding::SimdFmov => {
3304                if isign4 == enc_ops!(Reg, Reg) {
3305                    // FMOV Gp <-> Vec st.opcode:
3306                    st.opcode.reset(0b00011110001001100000000000000000);
3307
3308                    if (op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec()) {
3309                        // FMOV Wd, Hn      (sf=0 type=11 rmode=00 op=110)
3310                        // FMOV Xd, Hn      (sf=1 type=11 rmode=00 op=110)
3311                        // FMOV Wd, Sn      (sf=0 type=00 rmode=00 op=110)
3312                        // FMOV Xd, Dn      (sf=1 type=11 rmode=00 op=110)
3313                        // FMOV Xd, Vn.d[1] (sf=1 type=10 rmode=01 op=110)
3314                        let x = op0.as_::<Reg>().is_gp64();
3315                        let sz = (op1.as_::<Reg>().reg_type() as u32)
3316                            .wrapping_sub(RegType::Vec16 as u32);
3317
3318                        let mut typ = sz.wrapping_sub(1) & 0x3;
3319                        let mut r_mode_op = 0b00110;
3320
3321                        if (op1.as_::<Vec>().has_element_index()) {
3322                            // Special case.
3323                            if (!x
3324                                || !op1.as_::<Vec>().is_vec_d2()
3325                                || op1.as_::<Vec>().element_index() != 1)
3326                            {
3327                                self.last_error = Some(AsmError::InvalidInstruction);
3328                                return;
3329                            }
3330                            typ = 0b10;
3331                            r_mode_op = 0b01110;
3332                        } else {
3333                            // Must be scalar.
3334                            if (sz > 2) {
3335                                self.last_error = Some(AsmError::InvalidOperand);
3336                                return;
3337                            }
3338
3339                            if (op1.as_::<Vec>().has_element_type()) {
3340                                self.last_error = Some(AsmError::InvalidInstruction);
3341                                return;
3342                            }
3343
3344                            if (op1.as_::<Vec>().is_vec32() && x) {
3345                                self.last_error = Some(AsmError::InvalidInstruction);
3346                                return;
3347                            }
3348
3349                            if (op1.as_::<Vec>().is_vec64() && !x) {
3350                                self.last_error = Some(AsmError::InvalidInstruction);
3351                                return;
3352                            }
3353                        }
3354
3355                        st.opcode.add_imm(x as u32, 31);
3356                        st.opcode.add_imm(typ, 22);
3357                        st.opcode.add_imm(r_mode_op, 16);
3358
3359                        emit_rd0_rn5!();
3360                    }
3361
3362                    if (op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp()) {
3363                        // FMOV Hd, Wn      (sf=0 type=11 rmode=00 op=111)
3364                        // FMOV Hd, Xn      (sf=1 type=11 rmode=00 op=111)
3365                        // FMOV Sd, Wn      (sf=0 type=00 rmode=00 op=111)
3366                        // FMOV Dd, Xn      (sf=1 type=11 rmode=00 op=111)
3367                        // FMOV Vd.d[1], Xn (sf=1 type=10 rmode=01 op=111)
3368                        let x = op1.as_::<Reg>().is_gp64();
3369                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3370                            .wrapping_sub(RegType::Vec16 as u32);
3371
3372                        let mut typ = sz.wrapping_sub(1) & 0x3;
3373                        let mut r_mode_op = 0b00111;
3374
3375                        if (op0.as_::<Vec>().has_element_index()) {
3376                            // Special case.
3377                            if (!x
3378                                || !op0.as_::<Vec>().is_vec_d2()
3379                                || op0.as_::<Vec>().element_index() != 1)
3380                            {
3381                                self.last_error = Some(AsmError::InvalidInstruction);
3382                                return;
3383                            }
3384                            typ = 0b10;
3385                            r_mode_op = 0b01111;
3386                        } else {
3387                            // Must be scalar.
3388                            if (sz > 2) {
3389                                self.last_error = Some(AsmError::InvalidInstruction);
3390                                return;
3391                            }
3392
3393                            if (op0.as_::<Vec>().has_element_type()) {
3394                                self.last_error = Some(AsmError::InvalidInstruction);
3395                                return;
3396                            }
3397
3398                            if (op0.as_::<Vec>().is_vec32() && x) {
3399                                self.last_error = Some(AsmError::InvalidInstruction);
3400                                return;
3401                            }
3402
3403                            if (op0.as_::<Vec>().is_vec64() && !x) {
3404                                self.last_error = Some(AsmError::InvalidInstruction);
3405                                return;
3406                            }
3407                        }
3408
3409                        st.opcode.add_imm(x as u32, 31);
3410                        st.opcode.add_imm(typ, 22);
3411                        st.opcode.add_imm(r_mode_op, 16);
3412                        emit_rd0_rn5!();
3413                    }
3414
3415                    if check_signature!(op0, op1) {
3416                        let sz = (op0.as_::<Reg>().reg_type() as u32)
3417                            .wrapping_sub(RegType::Vec16 as u32);
3418                        if sz > 2 {
3419                            self.last_error = Some(AsmError::InvalidInstruction);
3420                            return;
3421                        }
3422
3423                        if op0.as_::<Vec>().has_element_type() {
3424                            self.last_error = Some(AsmError::InvalidInstruction);
3425                            return;
3426                        }
3427
3428                        let typ = sz.wrapping_sub(1) & 0x3;
3429                        st.opcode.reset(0b00011110001000000100000000000000);
3430                        st.opcode.add_imm(typ, 22);
3431                        emit_rd0_rn5!();
3432                    }
3433                }
3434
3435                if isign4 == enc_ops!(Reg, Imm) {
3436                    if op0.as_::<Reg>().is_vec() {
3437                        let fp_value = if op1.as_::<Imm>().is_double() {
3438                            op1.as_::<Imm>().value_f64()
3439                        } else if op1.as_::<Imm>().is_int32() {
3440                            op1.as_::<Imm>().value() as i32 as f64
3441                        } else {
3442                            self.last_error = Some(AsmError::InvalidOperand);
3443                            return;
3444                        };
3445
3446                        if !is_fp64_imm8(fp_value.to_bits()) {
3447                            self.last_error = Some(AsmError::InvalidOperand);
3448                            return;
3449                        }
3450
3451                        let imm8 = encode_fp64_to_imm8(fp_value.to_bits());
3452
3453                        if !op0.as_::<Vec>().has_element_type() {
3454                            let sz = (op0.as_::<Reg>().reg_type() as u32)
3455                                .wrapping_sub(RegType::Vec16 as u32);
3456                            let typ = sz.wrapping_sub(1) & 0x3;
3457                            if sz > 2 {
3458                                self.last_error = Some(AsmError::InvalidInstruction);
3459                                return;
3460                            }
3461
3462                            st.opcode.reset(0b00011110001000000001000000000000);
3463                            st.opcode.add_imm(typ, 22);
3464                            st.opcode.add_imm(imm8, 13);
3465                            emit_rd0!();
3466                        } else {
3467                            let q = (op0.as_::<Reg>().reg_type() as u32)
3468                                .wrapping_sub(RegType::Vec64 as u32);
3469                            let sz = (op0.as_::<Vec>().element_type() as u32)
3470                                .wrapping_sub(VecElementType::H as u32);
3471
3472                            if q > 1 || sz > 2 {
3473                                self.last_error = Some(AsmError::InvalidInstruction);
3474                                return;
3475                            }
3476
3477                            const SZ_BITS_TABLE: [u32; 3] = [1 << 11, 0, 1 << 29];
3478                            st.opcode.reset(0b00001111000000001111010000000000);
3479                            st.opcode ^= SZ_BITS_TABLE[sz as usize];
3480                            st.opcode.add_imm(q, 30);
3481                            st.opcode.add_imm(imm8 >> 5, 16);
3482                            st.opcode.add_imm(imm8 & 31, 5);
3483                            emit_rd0!();
3484                        }
3485                    }
3486                }
3487            }
3488
3489            Encoding::FSimdPair => {
3490                let op_data = &F_SIMD_PAIR[encoding_index];
3491
3492                if isign4 == enc_ops!(Reg, Reg) {
3493                    // This operation is only defined for:
3494                    //   hD, vS.2h (16-bit)
3495                    //   sD, vS.2s (32-bit)
3496                    //   dD, vS.2d (64-bit)
3497                    let sz =
3498                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec16 as u32);
3499                    if sz > 2 {
3500                        self.last_error = Some(AsmError::InvalidInstruction);
3501                        return;
3502                    }
3503
3504                    const SZ_SIGNATURES: [u32; 3] = [
3505                        A64VecS::SIGNATURE | (Vec::SIGNATURE_ELEMENT_H as u32),
3506                        A64VecD::SIGNATURE | (Vec::SIGNATURE_ELEMENT_S as u32),
3507                        A64VecQ::SIGNATURE | (Vec::SIGNATURE_ELEMENT_D as u32),
3508                    ];
3509
3510                    if op0.signature().bits() != SZ_SIGNATURES[sz as usize] {
3511                        self.last_error = Some(AsmError::InvalidInstruction);
3512                        return;
3513                    }
3514
3515                    const SZ_BITS_TABLE: [u32; 3] = [1 << 29, 0, 1 << 22];
3516
3517                    st.opcode.reset(op_data.scalar_op());
3518                    st.opcode ^= SZ_BITS_TABLE[sz as usize];
3519                    emit_rd0_rn5!();
3520                }
3521
3522                if isign4 == enc_ops!(Reg, Reg, Reg) {
3523                    if !check_signature!(op0, op1, op2) {
3524                        self.last_error = Some(AsmError::InvalidInstruction);
3525                        return;
3526                    }
3527
3528                    let q =
3529                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3530                    if q > 1 {
3531                        self.last_error = Some(AsmError::InvalidInstruction);
3532                        return;
3533                    }
3534
3535                    const SZ_BITS_TABLE: [u32; 3] =
3536                        [(1 << 22) | (1 << 21) | (1 << 15) | (1 << 14), 0, 1 << 22];
3537                    st.opcode.reset(op_data.scalar_op());
3538                    st.opcode ^= SZ_BITS_TABLE[q as usize];
3539                    st.opcode.add_imm(q, 30);
3540                    emit_rd0_rn5_rm16!();
3541                }
3542            }
3543
3544            Encoding::ISimdSV => {
3545                let op_data = &I_SIMD_SV[encoding_index];
3546
3547                if isign4 == enc_ops!(Reg, Reg) {
3548                    let l = (inst_flags & InstFlag::Long as u16) != 0;
3549                    if (op0.as_::<Vec>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32)
3550                        != (op1.as_::<Vec>().element_type() as u32)
3551                            .wrapping_sub(VecElementType::B as u32)
3552                            .wrapping_add(l as u32)
3553                    {
3554                        self.last_error = Some(AsmError::InvalidInstruction);
3555                        return;
3556                    }
3557                    let size_op = element_type_to_size_op(
3558                        op_data.vec_op_type,
3559                        op1.as_::<Reg>().reg_type(),
3560                        op1.as_::<Vec>().element_type(),
3561                    );
3562
3563                    if !size_op.is_valid() {
3564                        self.last_error = Some(AsmError::InvalidInstruction);
3565                        return;
3566                    }
3567
3568                    st.opcode.reset(op_data.opcode());
3569                    st.opcode.add_imm(size_op.q(), 30);
3570                    st.opcode.add_imm(size_op.size(), 22);
3571                    emit_rd0_rn5!();
3572                }
3573            }
3574
3575            Encoding::ISimdVV => {
3576                let op_data = &I_SIMD_VV[encoding_index];
3577
3578                if isign4 == enc_ops!(Reg, Reg) {
3579                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3580                    if !match_signature2(op0, op1, inst_flags as u32) {
3581                        self.last_error = Some(AsmError::InvalidInstruction);
3582                        return;
3583                    }
3584
3585                    let size_op = element_type_to_size_op(
3586                        op_data.vec_op_type,
3587                        sop.as_::<Reg>().reg_type(),
3588                        sop.as_::<Vec>().element_type(),
3589                    );
3590                    if !size_op.is_valid() {
3591                        self.last_error = Some(AsmError::InvalidInstruction);
3592                        return;
3593                    }
3594
3595                    st.opcode.reset(op_data.opcode());
3596                    st.opcode.add_imm(size_op.qs(), 30);
3597                    st.opcode.add_imm(size_op.scalar(), 28);
3598                    st.opcode.add_imm(size_op.size(), 22);
3599                    emit_rd0_rn5!();
3600                }
3601            }
3602
3603            Encoding::ISimdVVx => {
3604                let op_data = &I_SIMD_VVX[encoding_index];
3605                if isign4 == enc_ops!(Reg, Reg) {
3606                    if op0.signature().bits() != op_data.op0_signature
3607                        || op1.signature().bits() != op_data.op1_signature
3608                    {
3609                        self.last_error = Some(AsmError::InvalidInstruction);
3610                        return;
3611                    }
3612                    st.opcode.reset(op_data.opcode());
3613                    emit_rd0_rn5!();
3614                }
3615            }
3616
3617            Encoding::ISimdVVV => {
3618                let op_data = &I_SIMD_VVV[encoding_index];
3619
3620                if isign4 == enc_ops!(Reg, Reg, Reg) {
3621                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3622                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3623                        self.last_error = Some(AsmError::InvalidInstruction);
3624                        return;
3625                    }
3626
3627                    let size_op = element_type_to_size_op(
3628                        op_data.vec_op_type,
3629                        sop.as_::<Reg>().reg_type(),
3630                        sop.as_::<Vec>().element_type(),
3631                    );
3632                    if !size_op.is_valid() {
3633                        self.last_error = Some(AsmError::InvalidInstruction);
3634                        return;
3635                    }
3636
3637                    st.opcode.reset(op_data.opcode());
3638                    st.opcode.add_imm(size_op.qs(), 30);
3639                    st.opcode.add_imm(size_op.scalar(), 28);
3640                    st.opcode.add_imm(size_op.size(), 22);
3641                    emit_rd0_rn5_rm16!();
3642                }
3643            }
3644
3645            Encoding::ISimdVVVx => {
3646                let op_data = &I_SIMD_VVVX[encoding_index];
3647
3648                if isign4 == enc_ops!(Reg, Reg, Reg) {
3649                    if op0.signature().bits() != op_data.op0_signature
3650                        || op1.signature().bits() != op_data.op1_signature
3651                        || op2.signature().bits() != op_data.op2_signature
3652                    {
3653                        self.last_error = Some(AsmError::InvalidInstruction);
3654                        return;
3655                    }
3656
3657                    st.opcode.reset(op_data.opcode());
3658                    emit_rd0_rn5_rm16!();
3659                }
3660            }
3661
3662            Encoding::ISimdWWV => {
3663                let op_data = &I_SIMD_WWV[encoding_index];
3664                if isign4 == enc_ops!(Reg, Reg, Reg) {
3665                    let size_op = element_type_to_size_op(
3666                        op_data.vec_op_type,
3667                        op2.as_::<Reg>().reg_type(),
3668                        op2.as_::<Vec>().element_type(),
3669                    );
3670                    if !size_op.is_valid() {
3671                        self.last_error = Some(AsmError::InvalidInstruction);
3672                        return;
3673                    }
3674                    if !check_signature!(op0, op1)
3675                        || !op0.as_::<Reg>().is_vec128()
3676                        || (op0.as_::<Vec>().element_type() as u32)
3677                            != (op2.as_::<Vec>().element_type() as u32 + 1)
3678                    {
3679                        self.last_error = Some(AsmError::InvalidInstruction);
3680                        return;
3681                    }
3682                    st.opcode.reset(op_data.opcode());
3683                    st.opcode.add_imm(size_op.qs(), 30);
3684                    st.opcode.add_imm(size_op.scalar(), 28);
3685                    st.opcode.add_imm(size_op.size(), 22);
3686                    emit_rd0_rn5_rm16!();
3687                }
3688            }
3689
3690            Encoding::ISimdVVVe => {
3691                let op_data = &I_SIMD_VVVE[encoding_index];
3692                if isign4 == enc_ops!(Reg, Reg, Reg) {
3693                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3694                    if !match_signature2(op0, op1, inst_flags as u32) {
3695                        self.last_error = Some(AsmError::InvalidInstruction);
3696                        return;
3697                    }
3698                    if !op2.as_::<Vec>().has_element_index() {
3699                        let size_op = element_type_to_size_op(
3700                            op_data.regular_vec_type,
3701                            sop.as_::<Reg>().reg_type(),
3702                            sop.as_::<Vec>().element_type(),
3703                        );
3704                        if !size_op.is_valid() {
3705                            self.last_error = Some(AsmError::InvalidInstruction);
3706                            return;
3707                        }
3708                        if !check_signature!(op1, op2) {
3709                            self.last_error = Some(AsmError::InvalidInstruction);
3710                            return;
3711                        }
3712                        st.opcode.reset((op_data.regular_op as u32) << 10);
3713                        st.opcode.add_imm(size_op.qs(), 30);
3714                        st.opcode.add_imm(size_op.scalar(), 28);
3715                        st.opcode.add_imm(size_op.size(), 22);
3716                        emit_rd0_rn5_rm16!();
3717                    } else {
3718                        let size_op = element_type_to_size_op(
3719                            op_data.element_vec_type,
3720                            sop.as_::<Reg>().reg_type(),
3721                            sop.as_::<Vec>().element_type(),
3722                        );
3723                        if !size_op.is_valid() {
3724                            self.last_error = Some(AsmError::InvalidInstruction);
3725                            return;
3726                        }
3727                        let element_index = op2.as_::<Vec>().element_index();
3728                        let mut lmh = LMHImm {
3729                            lm: 0,
3730                            h: 0,
3731                            max_rm_id: 0,
3732                        };
3733                        if !encode_lmh(size_op.size(), element_index, &mut lmh) {
3734                            self.last_error = Some(AsmError::InvalidOperand);
3735                            return;
3736                        }
3737                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
3738                            self.last_error = Some(AsmError::InvalidOperand);
3739                            return;
3740                        }
3741                        st.opcode.reset((op_data.element_op as u32) << 10);
3742                        st.opcode.add_imm(size_op.q(), 30);
3743                        st.opcode.add_imm(size_op.size(), 22);
3744                        st.opcode.add_imm(lmh.lm, 20);
3745                        st.opcode.add_imm(lmh.h, 11);
3746                        emit_rd0_rn5_rm16!();
3747                    }
3748                }
3749            }
3750
3751            Encoding::ISimdVVVI => {
3752                let op_data = &I_SIMD_VVVI[encoding_index];
3753                if isign4 == enc_ops!(Reg, Reg, Reg, Imm) {
3754                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3755                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3756                        self.last_error = Some(AsmError::InvalidInstruction);
3757                        return;
3758                    }
3759                    let size_op = element_type_to_size_op(
3760                        op_data.vec_op_type,
3761                        sop.as_::<Reg>().reg_type(),
3762                        sop.as_::<Vec>().element_type(),
3763                    );
3764                    if !size_op.is_valid() {
3765                        self.last_error = Some(AsmError::InvalidInstruction);
3766                        return;
3767                    }
3768                    let imm_value = op3.as_::<Imm>().value() as u64;
3769                    let mut imm_size = op_data.imm_size;
3770                    if op_data.imm64_has_one_bit_less != 0 && size_op.q() == 0 {
3771                        imm_size -= 1;
3772                    }
3773                    let imm_max = 1u64 << imm_size;
3774                    if imm_value >= imm_max {
3775                        self.last_error = Some(AsmError::InvalidImmediate);
3776                        return;
3777                    }
3778                    st.opcode.reset(op_data.opcode());
3779                    st.opcode.add_imm(size_op.qs(), 30);
3780                    st.opcode.add_imm(size_op.scalar(), 28);
3781                    st.opcode.add_imm(size_op.size(), 22);
3782                    st.opcode.add_imm(imm_value as u32, op_data.imm_shift);
3783                    emit_rd0_rn5_rm16!();
3784                }
3785            }
3786
3787            Encoding::ISimdVVVV => {
3788                let op_data = &I_SIMD_VVVV[encoding_index];
3789                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3790                    let sop = significant_simd_op(op0, op1, inst_flags as u32);
3791                    if !match_signature4(op0, op1, op2, op3, inst_flags as u32) {
3792                        self.last_error = Some(AsmError::InvalidInstruction);
3793                        return;
3794                    }
3795                    let size_op = element_type_to_size_op(
3796                        op_data.vec_op_type,
3797                        sop.as_::<Reg>().reg_type(),
3798                        sop.as_::<Vec>().element_type(),
3799                    );
3800                    if !size_op.is_valid() {
3801                        self.last_error = Some(AsmError::InvalidInstruction);
3802                        return;
3803                    }
3804                    st.opcode.reset((op_data.opcode as u32) << 10);
3805                    st.opcode.add_imm(size_op.qs(), 30);
3806                    st.opcode.add_imm(size_op.scalar(), 28);
3807                    st.opcode.add_imm(size_op.size(), 22);
3808                    emit_rd0_rn5_rm16_ra10!();
3809                }
3810            }
3811
3812            Encoding::ISimdVVVVx => {
3813                let op_data = &I_SIMD_VVVVX[encoding_index];
3814                if isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
3815                    if op0.signature().bits() != op_data.op0_signature
3816                        || op1.signature().bits() != op_data.op1_signature
3817                        || op2.signature().bits() != op_data.op2_signature
3818                        || op3.signature().bits() != op_data.op3_signature
3819                    {
3820                        self.last_error = Some(AsmError::InvalidInstruction);
3821                        return;
3822                    }
3823                    st.opcode.reset((op_data.opcode as u32) << 10);
3824                    emit_rd0_rn5_rm16_ra10!();
3825                }
3826            }
3827
3828            Encoding::ISimdPair => {
3829                let op_data = &I_SIMD_PAIR[encoding_index];
3830                if isign4 == enc_ops!(Reg, Reg) && op_data.opcode2 != 0 {
3831                    if op0.as_::<Vec>().is_vec_d1() && op1.as_::<Vec>().is_vec_d2() {
3832                        st.opcode.reset((op_data.opcode2 as u32) << 10);
3833                        st.opcode.add_imm(0x3, 22);
3834                        emit_rd0_rn5!();
3835                    }
3836                }
3837                if isign4 == enc_ops!(Reg, Reg, Reg) {
3838                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3839                        self.last_error = Some(AsmError::InvalidInstruction);
3840                        return;
3841                    }
3842                    let size_op = element_type_to_size_op(
3843                        op_data.op_type3,
3844                        op0.as_::<Reg>().reg_type(),
3845                        op0.as_::<Vec>().element_type(),
3846                    );
3847                    if !size_op.is_valid() {
3848                        self.last_error = Some(AsmError::InvalidInstruction);
3849                        return;
3850                    }
3851                    st.opcode.reset((op_data.opcode3 as u32) << 10);
3852                    st.opcode.add_imm(size_op.qs(), 30);
3853                    st.opcode.add_imm(size_op.scalar(), 28);
3854                    st.opcode.add_imm(size_op.size(), 22);
3855                    emit_rd0_rn5_rm16!();
3856                }
3857            }
3858
3859            Encoding::SimdBicOrr => {
3860                let op_data = &SIMD_BIC_ORR[encoding_index];
3861                if isign4 == enc_ops!(Reg, Reg, Reg) {
3862                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3863                        self.last_error = Some(AsmError::InvalidInstruction);
3864                        return;
3865                    }
3866                    let size_op = element_type_to_size_op(
3867                        0, // kVO_V_B
3868                        op0.as_::<Reg>().reg_type(),
3869                        op0.as_::<Vec>().element_type(),
3870                    );
3871                    if !size_op.is_valid() {
3872                        self.last_error = Some(AsmError::InvalidInstruction);
3873                        return;
3874                    }
3875                    st.opcode.reset((op_data.register_op as u32) << 10);
3876                    st.opcode.add_imm(size_op.q(), 30);
3877                    emit_rd0_rn5_rm16!();
3878                }
3879                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
3880                    let size_op = element_type_to_size_op(
3881                        5, // kVO_V_HS
3882                        op0.as_::<Reg>().reg_type(),
3883                        op0.as_::<Vec>().element_type(),
3884                    );
3885                    if !size_op.is_valid() {
3886                        self.last_error = Some(AsmError::InvalidInstruction);
3887                        return;
3888                    }
3889                    if op1.as_::<Imm>().value() as u64 > 0xFFFFFFFF {
3890                        self.last_error = Some(AsmError::InvalidImmediate);
3891                        return;
3892                    }
3893                    let mut imm = op1.as_::<Imm>().value() as u32;
3894                    let mut shift = 0u32;
3895                    let max_shift = (8u32 << size_op.size()) - 8u32;
3896                    if isign4 == enc_ops!(Reg, Imm, Imm) {
3897                        if op2.as_::<Imm>().predicate() != ShiftOp::LSL as u32 {
3898                            self.last_error = Some(AsmError::InvalidImmediate);
3899                            return;
3900                        }
3901                        if imm > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
3902                            self.last_error = Some(AsmError::InvalidImmediate);
3903                            return;
3904                        }
3905                        shift = op2.as_::<Imm>().value() as u32;
3906                        if (shift & 0x7) != 0 {
3907                            self.last_error = Some(AsmError::InvalidImmediate);
3908                            return;
3909                        }
3910                    } else if imm != 0 {
3911                        shift = imm.trailing_zeros() & !0x7;
3912                        imm >>= shift;
3913                        if imm > 0xFF || shift > max_shift {
3914                            self.last_error = Some(AsmError::InvalidImmediate);
3915                            return;
3916                        }
3917                    }
3918                    let mut cmode = 0x1 | ((shift / 8) << 1);
3919                    if size_op.size() == 1 {
3920                        cmode |= 1 << 3;
3921                    }
3922                    let abc = (imm >> 5) & 0x7;
3923                    let defgh = imm & 0x1F;
3924                    st.opcode.reset((op_data.immediate_op as u32) << 10);
3925                    st.opcode.add_imm(size_op.q(), 30);
3926                    st.opcode.add_imm(abc, 16);
3927                    st.opcode.add_imm(cmode, 12);
3928                    st.opcode.add_imm(defgh, 5);
3929                    emit_rd0!();
3930                }
3931            }
3932
3933            Encoding::SimdCmp => {
3934                let op_data = &SIMD_CMP[encoding_index];
3935
3936                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
3937                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
3938                        self.last_error = Some(AsmError::InvalidInstruction);
3939                        return;
3940                    }
3941
3942                    let size_op = element_type_to_size_op(
3943                        op_data.vec_op_type,
3944                        op0.as_::<Reg>().reg_type(),
3945                        op0.as_::<Vec>().element_type(),
3946                    );
3947                    if !size_op.is_valid() {
3948                        self.last_error = Some(AsmError::InvalidInstruction);
3949                        return;
3950                    }
3951
3952                    st.opcode.reset((op_data.register_op as u32) << 10);
3953                    st.opcode.add_imm(size_op.qs(), 30);
3954                    st.opcode.add_imm(size_op.scalar(), 28);
3955                    st.opcode.add_imm(size_op.size(), 22);
3956                    emit_rd0_rn5_rm16!();
3957                }
3958
3959                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.zero_op != 0 {
3960                    if !match_signature2(op0, op1, inst_flags as u32) {
3961                        self.last_error = Some(AsmError::InvalidInstruction);
3962                        return;
3963                    }
3964
3965                    if op2.as_::<Imm>().value() != 0 {
3966                        self.last_error = Some(AsmError::InvalidImmediate);
3967                        return;
3968                    }
3969
3970                    let size_op = element_type_to_size_op(
3971                        op_data.vec_op_type,
3972                        op0.as_::<Reg>().reg_type(),
3973                        op0.as_::<Vec>().element_type(),
3974                    );
3975                    if !size_op.is_valid() {
3976                        self.last_error = Some(AsmError::InvalidInstruction);
3977                        return;
3978                    }
3979
3980                    st.opcode.reset((op_data.zero_op as u32) << 10);
3981                    st.opcode.add_imm(size_op.qs(), 30);
3982                    st.opcode.add_imm(size_op.scalar(), 28);
3983                    st.opcode.add_imm(size_op.size(), 22);
3984                    emit_rd0_rn5!();
3985                }
3986            }
3987
3988            Encoding::SimdDot => {
3989                let op_data = &SIMD_DOT[encoding_index];
3990
3991                if isign4 == enc_ops!(Reg, Reg, Reg) {
3992                    let q =
3993                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
3994                    let size = 2u32;
3995
3996                    if q > 1 {
3997                        self.last_error = Some(AsmError::InvalidInstruction);
3998                        return;
3999                    }
4000
4001                    if !op2.as_::<Vec>().has_element_index() {
4002                        if op_data.vector_op == 0 {
4003                            self.last_error = Some(AsmError::InvalidInstruction);
4004                            return;
4005                        }
4006
4007                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
4008                            || op1.as_::<Reg>().reg_type() != op2.as_::<Reg>().reg_type()
4009                        {
4010                            self.last_error = Some(AsmError::InvalidInstruction);
4011                            return;
4012                        }
4013
4014                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
4015                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4016                            || op2.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4017                        {
4018                            self.last_error = Some(AsmError::InvalidInstruction);
4019                            return;
4020                        }
4021
4022                        st.opcode.reset((op_data.vector_op as u32) << 10);
4023                        st.opcode.add_imm(q, 30);
4024                        emit_rd0_rn5_rm16!();
4025                    } else {
4026                        if op_data.element_op == 0 {
4027                            self.last_error = Some(AsmError::InvalidInstruction);
4028                            return;
4029                        }
4030
4031                        if op0.as_::<Reg>().reg_type() != op1.as_::<Reg>().reg_type()
4032                            || !op2.as_::<Reg>().is_vec128()
4033                        {
4034                            self.last_error = Some(AsmError::InvalidInstruction);
4035                            return;
4036                        }
4037
4038                        if op0.as_::<Vec>().element_type() as u32 != op_data.ta as u32
4039                            || op1.as_::<Vec>().element_type() as u32 != op_data.tb as u32
4040                            || op2.as_::<Vec>().element_type() as u32 != op_data.t_element as u32
4041                        {
4042                            self.last_error = Some(AsmError::InvalidInstruction);
4043                            return;
4044                        }
4045
4046                        let element_index = op2.as_::<Vec>().element_index();
4047                        let mut lmh = LMHImm {
4048                            lm: 0,
4049                            h: 0,
4050                            max_rm_id: 0,
4051                        };
4052                        if !encode_lmh(size, element_index, &mut lmh) {
4053                            self.last_error = Some(AsmError::InvalidOperand);
4054                            return;
4055                        }
4056
4057                        if op2.as_::<Reg>().id() > lmh.max_rm_id {
4058                            self.last_error = Some(AsmError::InvalidOperand);
4059                            return;
4060                        }
4061
4062                        st.opcode.reset((op_data.element_op as u32) << 10);
4063                        st.opcode.add_imm(q, 30);
4064                        st.opcode.add_imm(lmh.lm, 20);
4065                        st.opcode.add_imm(lmh.h, 11);
4066                        emit_rd0_rn5_rm16!();
4067                    }
4068                }
4069            }
4070
4071            Encoding::SimdDup => {
4072                simd_dup!();
4073            }
4074
4075            Encoding::SimdIns => {
4076                simd_insn!();
4077            }
4078
4079            Encoding::SimdMov => {
4080                if isign4 == enc_ops!(Reg, Reg) {
4081                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_vec() {
4082                        // INS v.x[index], v.x[index].
4083                        if op0.as_::<Vec>().has_element_index()
4084                            && op1.as_::<Vec>().has_element_index()
4085                        {
4086                            // SimdIns encoding.
4087
4088                            encoding = Encoding::SimdIns;
4089                            // Recurse to SimdIns.
4090                            simd_insn!();
4091                            return;
4092                        }
4093                        // DUP {b|h|s|d}, v.{b|h|s|d}[index].
4094                        if op1.as_::<Vec>().has_element_index() {
4095                            encoding = Encoding::SimdDup;
4096                            simd_dup!();
4097                            return;
4098                        }
4099                        if !check_signature!(op0, op1) {
4100                            self.last_error = Some(AsmError::InvalidInstruction);
4101                            return;
4102                        }
4103                        let q = (op0.as_::<Reg>().reg_type() as u32)
4104                            .wrapping_sub(RegType::Vec64 as u32);
4105                        if q > 1 {
4106                            self.last_error = Some(AsmError::InvalidInstruction);
4107                            return;
4108                        }
4109                        st.opcode.reset(0b0000111010100000000111 << 10);
4110                        st.opcode.add_imm(q, 30);
4111                        st.opcode.add_reg(op1.id(), 16);
4112                        emit_rd0_rn5!();
4113                        return;
4114                    }
4115                    if op0.as_::<Reg>().is_vec() && op1.as_::<Reg>().is_gp() {
4116                        // INS v.x[index], Rn.
4117                        if op0.as_::<Vec>().has_element_index() {
4118                            encoding = Encoding::SimdIns;
4119                            simd_insn!();
4120                            return;
4121                        }
4122                        self.last_error = Some(AsmError::InvalidInstruction);
4123                        return;
4124                    }
4125                    if op0.as_::<Reg>().is_gp() && op1.as_::<Reg>().is_vec() {
4126                        // UMOV Rd, V.{s|d}[index].
4127                        encoding_index = 1;
4128                        encoding = Encoding::SimdSmovUmov;
4129                        simd_umov!();
4130                        return;
4131                    }
4132                }
4133            }
4134
4135            Encoding::SimdMoviMvni => {
4136                let op_data = &SIMD_MOVI_MVNI[encoding_index];
4137                if isign4 == enc_ops!(Reg, Imm) || isign4 == enc_ops!(Reg, Imm, Imm) {
4138                    let mut size_op = element_type_to_size_op(
4139                        20,
4140                        op0.as_::<Reg>().reg_type(),
4141                        op0.as_::<Vec>().element_type(),
4142                    );
4143                    if !size_op.is_valid() {
4144                        self.last_error = Some(AsmError::InvalidInstruction);
4145                        return;
4146                    }
4147                    let mut imm64 = op1.as_::<Imm>().value() as u64;
4148                    let mut imm8 = 0u32;
4149                    let mut cmode = 0u32;
4150                    let inverted = op_data.inverted;
4151                    let mut op = 0u32;
4152                    let mut shift = 0u32;
4153                    let mut shift_op = ShiftOp::LSL as u32;
4154                    if size_op.size() == 3 {
4155                        if op2.is_imm() && op2.as_::<Imm>().value() != 0 {
4156                            self.last_error = Some(AsmError::InvalidImmediate);
4157                            return;
4158                        }
4159                        if is_byte_mask_imm(imm64) {
4160                            imm8 = encode_imm64_byte_mask_to_imm8(imm64);
4161                        } else {
4162                            if (imm64 >> 32) == (imm64 & 0xFFFFFFFF) {
4163                                imm64 &= 0xFFFFFFFF;
4164                                size_op.decrement_size();
4165                            } else {
4166                                self.last_error = Some(AsmError::InvalidImmediate);
4167                                return;
4168                            }
4169                        }
4170                    }
4171                    if size_op.size() < 3 {
4172                        if imm64 > 0xFFFFFFFF {
4173                            self.last_error = Some(AsmError::InvalidImmediate);
4174                            return;
4175                        }
4176                        imm8 = imm64 as u32;
4177                        if size_op.size() == 2 {
4178                            if (imm8 >> 16) == (imm8 & 0xFFFF) {
4179                                imm8 >>= 16;
4180                                size_op.decrement_size();
4181                            }
4182                        }
4183                        if size_op.size() == 1 {
4184                            if imm8 > 0xFFFF {
4185                                self.last_error = Some(AsmError::InvalidImmediate);
4186                                return;
4187                            }
4188                            if (imm8 >> 8) == (imm8 & 0xFF) {
4189                                imm8 >>= 8;
4190                                size_op.decrement_size();
4191                            }
4192                        }
4193                        let max_shift = (8u32 << size_op.size()) - 8u32;
4194                        if op2.is_imm() {
4195                            if imm8 > 0xFF || op2.as_::<Imm>().value() as u64 > max_shift as u64 {
4196                                self.last_error = Some(AsmError::InvalidImmediate);
4197                                return;
4198                            }
4199                            shift = op2.as_::<Imm>().value() as u32;
4200                            shift_op = op2.as_::<Imm>().predicate();
4201                        } else if imm8 != 0 {
4202                            shift = imm8.trailing_zeros() & !0x7;
4203                            imm8 >>= shift;
4204                            if imm8 > 0xFF || shift > max_shift {
4205                                self.last_error = Some(AsmError::InvalidImmediate);
4206                                return;
4207                            }
4208                        }
4209                        if (shift & 0x7) != 0 {
4210                            self.last_error = Some(AsmError::InvalidImmediate);
4211                            return;
4212                        }
4213                    }
4214                    shift /= 8;
4215                    match size_op.size() {
4216                        0 => {
4217                            if shift_op != ShiftOp::LSL as u32 {
4218                                self.last_error = Some(AsmError::InvalidImmediate);
4219                                return;
4220                            }
4221                            if inverted != 0 {
4222                                imm8 = !imm8 & 0xFF;
4223                            }
4224                            cmode = B!(3) | B!(2) | B!(1);
4225                        }
4226                        1 => {
4227                            if shift_op != ShiftOp::LSL as u32 {
4228                                self.last_error = Some(AsmError::InvalidImmediate);
4229                                return;
4230                            }
4231                            cmode = B!(3) | (shift << 1);
4232                            op = inverted;
4233                        }
4234                        2 => {
4235                            if shift_op == ShiftOp::LSL as u32 {
4236                                cmode = shift << 1;
4237                            } else if shift_op == ShiftOp::MSL as u32 {
4238                                if shift == 0 || shift > 2 {
4239                                    self.last_error = Some(AsmError::InvalidImmediate);
4240                                    return;
4241                                }
4242                                cmode = B!(3) | B!(2) | (shift - 1);
4243                            } else {
4244                                self.last_error = Some(AsmError::InvalidImmediate);
4245                                return;
4246                            }
4247                            op = inverted;
4248                        }
4249                        3 => {
4250                            if inverted != 0 {
4251                                imm8 = !imm8 & 0xFF;
4252                            }
4253                            op = 1;
4254                            cmode = B!(3) | B!(2) | B!(1);
4255                        }
4256                        _ => {}
4257                    }
4258                    let abc = (imm8 >> 5) & 0x7;
4259                    let defgh = imm8 & 0x1F;
4260                    st.opcode.reset((op_data.opcode as u32) << 10);
4261                    st.opcode.add_imm(size_op.q(), 30);
4262                    st.opcode.add_imm(op, 29);
4263                    st.opcode.add_imm(abc, 16);
4264                    st.opcode.add_imm(cmode, 12);
4265                    st.opcode.add_imm(defgh, 5);
4266                    emit_rd0!();
4267                    return;
4268                }
4269            }
4270
4271            Encoding::SimdShift => {
4272                let op_data = &SIMD_SHIFT[encoding_index];
4273                let sop = significant_simd_op(op0, op1, inst_flags as u32);
4274                let size_op = element_type_to_size_op(
4275                    op_data.vec_op_type,
4276                    sop.as_::<Reg>().reg_type(),
4277                    sop.as_::<Vec>().element_type(),
4278                );
4279                if !size_op.is_valid() {
4280                    self.last_error = Some(AsmError::InvalidInstruction);
4281                    return;
4282                }
4283                if isign4 == enc_ops!(Reg, Reg, Imm) && op_data.immediate_op != 0 {
4284                    if !match_signature2(op0, op1, inst_flags as u32) {
4285                        self.last_error = Some(AsmError::InvalidInstruction);
4286                        return;
4287                    }
4288                    if op2.as_::<Imm>().value() as u64 > 63 {
4289                        self.last_error = Some(AsmError::InvalidImmediate);
4290                        return;
4291                    }
4292                    let lsb_shift = size_op.size() + 3;
4293                    let lsb_mask = (1u32 << lsb_shift) - 1;
4294                    let mut imm = op2.as_::<Imm>().value() as u32;
4295                    if op_data.inverted_imm != 0 {
4296                        if imm == 0 || imm > (1u32 << lsb_shift) {
4297                            self.last_error = Some(AsmError::InvalidImmediate);
4298                            return;
4299                        }
4300                        imm = (!imm + 1) & lsb_mask;
4301                    }
4302                    if imm > lsb_mask {
4303                        self.last_error = Some(AsmError::InvalidImmediate);
4304                        return;
4305                    }
4306                    imm |= 1u32 << lsb_shift;
4307                    st.opcode.reset((op_data.immediate_op as u32) << 10);
4308                    st.opcode.add_imm(size_op.qs(), 30);
4309                    st.opcode.add_imm(size_op.scalar(), 28);
4310                    st.opcode.add_imm(imm, 16);
4311                    emit_rd0_rn5!();
4312                    return;
4313                }
4314                if isign4 == enc_ops!(Reg, Reg, Reg) && op_data.register_op != 0 {
4315                    if !match_signature3(op0, op1, op2, inst_flags as u32) {
4316                        self.last_error = Some(AsmError::InvalidInstruction);
4317                        return;
4318                    }
4319                    st.opcode.reset((op_data.register_op as u32) << 10);
4320                    st.opcode.add_imm(size_op.qs(), 30);
4321                    st.opcode.add_imm(size_op.scalar(), 28);
4322                    st.opcode.add_imm(size_op.size(), 22);
4323                    emit_rd0_rn5_rm16!();
4324                    return;
4325                }
4326            }
4327
4328            Encoding::SimdShiftES => {
4329                let op_data = &SIMD_SHIFT_ES[encoding_index];
4330                if isign4 == enc_ops!(Reg, Reg, Imm) {
4331                    let size_op = element_type_to_size_op(
4332                        op_data.vec_op_type,
4333                        op1.as_::<Reg>().reg_type(),
4334                        op1.as_::<Vec>().element_type(),
4335                    );
4336                    if !size_op.is_valid() {
4337                        self.last_error = Some(AsmError::InvalidInstruction);
4338                        return;
4339                    }
4340                    if !match_signature2(op0, op1, inst_flags as u32) {
4341                        self.last_error = Some(AsmError::InvalidInstruction);
4342                        return;
4343                    }
4344                    let shift = op2.as_::<Imm>().value() as u64;
4345                    let shift_op = op2.as_::<Imm>().predicate();
4346                    if shift != (8u64 << size_op.size()) || shift_op != ShiftOp::LSL as u32 {
4347                        self.last_error = Some(AsmError::InvalidImmediate);
4348                        return;
4349                    }
4350                    st.opcode.reset((op_data.opcode as u32) << 10);
4351                    st.opcode.add_imm(size_op.q(), 30);
4352                    st.opcode.add_imm(size_op.size(), 22);
4353                    emit_rd0_rn5!();
4354                    return;
4355                }
4356            }
4357
4358            Encoding::SimdSm3tt => {
4359                let op_data = &SIMD_SM3TT[encoding_index];
4360                if isign4 == enc_ops!(Reg, Reg, Reg) {
4361                    if op0.as_::<Vec>().is_vec_s4()
4362                        && op1.as_::<Vec>().is_vec_s4()
4363                        && op2.as_::<Vec>().is_vec_s4()
4364                        && op2.as_::<Vec>().has_element_index()
4365                    {
4366                        let imm2 = op2.as_::<Vec>().element_index();
4367                        if imm2 > 3 {
4368                            self.last_error = Some(AsmError::InvalidOperand);
4369                            return;
4370                        }
4371                        st.opcode.reset((op_data.opcode as u32) << 10);
4372                        st.opcode.add_imm(imm2, 12);
4373                        emit_rd0_rn5_rm16!();
4374                        return;
4375                    }
4376                }
4377            }
4378
4379            Encoding::SimdSmovUmov => {
4380                simd_umov!();
4381            }
4382
4383            Encoding::SimdSxtlUxtl => {
4384                let op_data = &SIMD_SXTL_UXTL[encoding_index];
4385                if isign4 == enc_ops!(Reg, Reg) {
4386                    let size_op = element_type_to_size_op(
4387                        op_data.vec_op_type,
4388                        op1.as_::<Reg>().reg_type(),
4389                        op1.as_::<Vec>().element_type(),
4390                    );
4391                    if !size_op.is_valid() {
4392                        self.last_error = Some(AsmError::InvalidInstruction);
4393                        return;
4394                    }
4395                    if !match_signature2(op0, op1, inst_flags as u32) {
4396                        self.last_error = Some(AsmError::InvalidInstruction);
4397                        return;
4398                    }
4399                    st.opcode.reset((op_data.opcode as u32) << 10);
4400                    st.opcode.add_imm(size_op.q(), 30);
4401                    st.opcode.add_imm(1u32, size_op.size() + 19);
4402                    emit_rd0_rn5!();
4403                    return;
4404                }
4405            }
4406
4407            Encoding::SimdTblTbx => {
4408                let op_data = &SIMD_TBL_TBX[encoding_index];
4409                if isign4 == enc_ops!(Reg, Reg, Reg) || isign4 == enc_ops!(Reg, Reg, Reg, Reg) {
4410                    st.opcode.reset((op_data.opcode as u32) << 10);
4411
4412                    let q =
4413                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4414                    if q > 1 || op0.as_::<Vec>().has_element_index() {
4415                        self.last_error = Some(AsmError::InvalidInstruction);
4416                        return;
4417                    }
4418                    if !op1.as_::<Vec>().is_vec_b16() || op1.as_::<Vec>().has_element_index() {
4419                        self.last_error = Some(AsmError::InvalidInstruction);
4420                        return;
4421                    }
4422                    let len =
4423                        (!op3.is_none() as u32) + (!op4.is_none() as u32) + (!op5.is_none() as u32);
4424                    st.opcode.add_imm(q, 30);
4425                    st.opcode.add_imm(len, 13);
4426
4427                    match len {
4428                        0 => {
4429                            if !check_signature!(op0, op2) {
4430                                self.last_error = Some(AsmError::InvalidInstruction);
4431                                return;
4432                            }
4433                            if op2.id() > 31 {
4434                                self.last_error = Some(AsmError::InvalidOperand);
4435                                return;
4436                            }
4437                            st.opcode.add_reg(op2.id(), 16);
4438                            emit_rd0_rn5!();
4439                            return;
4440                        }
4441                        1 => {
4442                            if !check_signature!(op0, op3) {
4443                                self.last_error = Some(AsmError::InvalidInstruction);
4444                                return;
4445                            }
4446                            if op3.id() > 31 {
4447                                self.last_error = Some(AsmError::InvalidOperand);
4448                                return;
4449                            }
4450                            st.opcode.add_reg(op3.id(), 16);
4451                            emit_rd0_rn5!();
4452                            return;
4453                        }
4454                        2 => {
4455                            if !check_signature!(op0, op4) {
4456                                self.last_error = Some(AsmError::InvalidInstruction);
4457                                return;
4458                            }
4459                            if op4.id() > 31 {
4460                                self.last_error = Some(AsmError::InvalidOperand);
4461                                return;
4462                            }
4463                            st.opcode.add_reg(op4.id(), 16);
4464                            emit_rd0_rn5!();
4465                            return;
4466                        }
4467                        3 => {
4468                            if !check_signature!(op0, op5) {
4469                                self.last_error = Some(AsmError::InvalidInstruction);
4470                                return;
4471                            }
4472                            if op5.id() > 31 {
4473                                self.last_error = Some(AsmError::InvalidOperand);
4474                                return;
4475                            }
4476                            st.opcode.add_reg(op5.id(), 16);
4477                            emit_rd0_rn5!();
4478                            return;
4479                        }
4480                        _ => {
4481                            self.last_error = Some(AsmError::InvalidInstruction);
4482                            return;
4483                        }
4484                    }
4485                }
4486            }
4487
4488            Encoding::SimdLdSt => {
4489                let op_data = &SIMD_LD_ST[encoding_index];
4490                if isign4 == enc_ops!(Reg, Mem) {
4491                    let m = op1.as_::<Mem>();
4492                    st.rm_rel = *op1;
4493
4494                    let xsz =
4495                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4496                    if xsz > 4 || op0.as_::<Vec>().has_element_index() {
4497                        self.last_error = Some(AsmError::InvalidOperand);
4498                        return;
4499                    }
4500
4501                    if !check_vec_id(op0) {
4502                        self.last_error = Some(AsmError::InvalidOperand);
4503                        return;
4504                    }
4505
4506                    // TODO: check_mem_base_index_rel(m)
4507                    let offset = m.offset();
4508                    if m.has_base_reg() {
4509                        if m.has_index() {
4510                            let opt = SHIFT_OP_TO_LD_ST_OP_MAP[m.shift_op() as usize];
4511                            if opt == 0xFF {
4512                                self.last_error = Some(AsmError::InvalidOperand);
4513                                return;
4514                            }
4515                            let shift = m.shift();
4516                            let s = if shift != 0 { 1 } else { 0 };
4517                            if s != 0 && shift != xsz {
4518                                self.last_error = Some(AsmError::InvalidOperand);
4519                                return;
4520                            }
4521                            st.opcode.reset((op_data.register_op as u32) << 21);
4522                            st.opcode.add_imm(xsz & 3, 30);
4523                            st.opcode.add_imm(xsz >> 2, 23);
4524                            st.opcode.add_imm(opt as u32, 13);
4525                            st.opcode.add_imm(s, 12);
4526                            st.opcode.0 |= 1 << 11;
4527                            st.opcode.add_reg(op0.id(), 0);
4528                            st.opcode.add_reg(m.base_id(), 5);
4529                            st.opcode.add_reg(m.index_id(), 16);
4530                            emit_op!();
4531                        }
4532
4533                        let offset32 = offset as i32;
4534                        if m.is_pre_or_post() {
4535                            if offset32 < -256 || offset32 > 255 {
4536                                self.last_error = Some(AsmError::InvalidOperand);
4537                                return;
4538                            }
4539                            st.opcode.reset((op_data.pre_post_op as u32) << 21);
4540                            st.opcode.add_imm(xsz & 3, 30);
4541                            st.opcode.add_imm(xsz >> 2, 23);
4542                            st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4543                            st.opcode.add_imm(m.is_pre_index() as u32, 11);
4544                            st.opcode.0 |= 1 << 10;
4545                            st.opcode.add_reg(op0.id(), 0);
4546                            st.opcode.add_reg(m.base_id(), 5);
4547                            emit_op!();
4548                        } else {
4549                            let imm12 = (offset32 as u32) >> xsz;
4550                            if imm12 >= (1 << 12) || ((imm12 << xsz) as i32) != offset32 {
4551                                // Fallback to SimdLdurStur
4552                                let op_data_ldur = &SIMD_LDUR_STUR[encoding_index];
4553                                if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4554                                    if offset32 < -256 || offset32 > 255 {
4555                                        self.last_error = Some(AsmError::InvalidOperand);
4556                                        return;
4557                                    }
4558                                    st.opcode.reset((op_data_ldur.opcode as u32) << 10);
4559                                    st.opcode.add_imm(xsz & 3, 30);
4560                                    st.opcode.add_imm(xsz >> 2, 23);
4561                                    st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4562                                    st.opcode.add_reg(op0.id(), 0);
4563                                    st.opcode.add_reg(m.base_id(), 5);
4564                                    emit_op!();
4565                                }
4566                                self.last_error = Some(AsmError::InvalidOperand);
4567                                return;
4568                            }
4569                            st.opcode.reset((op_data.u_offset_op as u32) << 22);
4570                            st.opcode.add_imm(xsz & 3, 30);
4571                            st.opcode.add_imm(xsz >> 2, 23);
4572                            st.opcode.add_imm(imm12, 10);
4573                            st.opcode.add_reg(op0.id(), 0);
4574                            st.opcode.add_reg(m.base_id(), 5);
4575                            emit_op!();
4576                        }
4577                    } else {
4578                        if op_data.literal_op == 0 {
4579                            self.last_error = Some(AsmError::InvalidOperand);
4580                            return;
4581                        }
4582                        if xsz < 2 {
4583                            self.last_error = Some(AsmError::InvalidOperand);
4584                            return;
4585                        }
4586                        let opc = xsz - 2;
4587                        st.opcode.reset((op_data.literal_op as u32) << 24);
4588                        st.opcode.add_imm(opc, 30);
4589                        st.opcode.add_reg(op0.id(), 0);
4590                        st.offset_format
4591                            .reset_to_imm_type(OffsetType::SignedOffset, 4, 5, 19, 2);
4592                        st.rm_rel = *op1;
4593                        emit_rel!();
4594                    }
4595                }
4596            }
4597
4598            Encoding::SimdLdpStp => {
4599                let op_data = &SIMD_LDP_STP[encoding_index];
4600                if isign4 == enc_ops!(Reg, Reg, Mem) {
4601                    let m = op2.as_::<Mem>();
4602                    st.rm_rel = *op2;
4603
4604                    let opc =
4605                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec32 as u32);
4606                    if opc > 2
4607                        || op0.as_::<Vec>().has_element_type()
4608                        || op0.as_::<Vec>().has_element_index()
4609                    {
4610                        self.last_error = Some(AsmError::InvalidInstruction);
4611                        return;
4612                    }
4613                    if !check_signature!(op0, op1) {
4614                        self.last_error = Some(AsmError::InvalidInstruction);
4615                        return;
4616                    }
4617                    if !check_vec_id2(op0, op1) {
4618                        self.last_error = Some(AsmError::InvalidOperand);
4619                        return;
4620                    }
4621                    if m.base_type() != RegType::Gp64 || m.has_index() {
4622                        self.last_error = Some(AsmError::InvalidOperand);
4623                        return;
4624                    }
4625                    let offset_shift = 2 + opc;
4626                    let offset32 = m.offset() as i32 >> offset_shift;
4627                    if ((offset32 << offset_shift) as i32) != m.offset() as i32 {
4628                        self.last_error = Some(AsmError::InvalidOperand);
4629                        return;
4630                    }
4631                    if offset32 < -64 || offset32 > 63 {
4632                        self.last_error = Some(AsmError::InvalidOperand);
4633                        return;
4634                    }
4635                    if m.is_pre_or_post() && offset32 != 0 {
4636                        if op_data.pre_post_op == 0 {
4637                            self.last_error = Some(AsmError::InvalidOperand);
4638                            return;
4639                        }
4640                        st.opcode.reset((op_data.pre_post_op as u32) << 22);
4641                        st.opcode.add_imm(m.is_pre_index() as u32, 24);
4642                    } else {
4643                        st.opcode.reset((op_data.offset_op as u32) << 22);
4644                    }
4645                    st.opcode.add_imm(opc, 30);
4646                    st.opcode.add_imm((offset32 as u32) & 0x7F, 15);
4647                    st.opcode.add_reg(op1.id(), 10);
4648                    st.opcode.add_reg(op0.id(), 0);
4649                    st.opcode.add_reg(m.base_id(), 5);
4650                    emit_op!();
4651                }
4652            }
4653
4654            Encoding::SimdLdurStur => {
4655                let op_data = &SIMD_LDUR_STUR[encoding_index];
4656                if isign4 == enc_ops!(Reg, Mem) {
4657                    let m = op1.as_::<Mem>();
4658                    st.rm_rel = *op1;
4659
4660                    let sz =
4661                        (op0.as_::<Reg>().reg_type() as u32).wrapping_sub(RegType::Vec8 as u32);
4662                    if sz > 4
4663                        || op0.as_::<Vec>().has_element_type()
4664                        || op0.as_::<Vec>().has_element_index()
4665                    {
4666                        self.last_error = Some(AsmError::InvalidInstruction);
4667                        return;
4668                    }
4669                    if !check_vec_id(op0) {
4670                        self.last_error = Some(AsmError::InvalidOperand);
4671                        return;
4672                    }
4673                    if m.has_base_reg() && !m.has_index() && !m.is_pre_or_post() {
4674                        let offset32 = m.offset() as i32;
4675                        if offset32 < -256 || offset32 > 255 {
4676                            self.last_error = Some(AsmError::InvalidOperand);
4677                            return;
4678                        }
4679                        st.opcode.reset((op_data.opcode as u32) << 10);
4680                        st.opcode.add_imm(sz & 3, 30);
4681                        st.opcode.add_imm(sz >> 2, 23);
4682                        st.opcode.add_imm((offset32 as u32) & 0x1FF, 12);
4683                        st.opcode.add_reg(op0.id(), 0);
4684                        st.opcode.add_reg(m.base_id(), 5);
4685                        emit_op!();
4686                    }
4687                    self.last_error = Some(AsmError::InvalidOperand);
4688                    return;
4689                }
4690            }
4691
4692            Encoding::SimdLdNStN => {
4693                let op_data = &SIMD_LD_N_ST_N[encoding_index];
4694                let o4 = *ops.get(4).unwrap_or(&NOREG);
4695
4696                let mut n = 1;
4697
4698                if isign4 == enc_ops!(Reg, Mem) {
4699                    if op_data.n != 1 {
4700                        self.last_error = Some(AsmError::InvalidInstruction);
4701                        return;
4702                    }
4703                    st.rm_rel = *op1;
4704                } else if isign4 == enc_ops!(Reg, Reg, Mem) {
4705                    if op_data.n != 1 && op_data.n != 2 {
4706                        self.last_error = Some(AsmError::InvalidInstruction);
4707                        return;
4708                    }
4709                    if !check_signature!(op0, op1) || op0.id() + 1 != op1.id() {
4710                        self.last_error = Some(AsmError::InvalidInstruction);
4711                        return;
4712                    }
4713                    n = 2;
4714                    st.rm_rel = *op2;
4715                } else if isign4 == enc_ops!(Reg, Reg, Reg, Mem) && o4.is_none() {
4716                    if op_data.n != 1 && op_data.n != 3 {
4717                        self.last_error = Some(AsmError::InvalidInstruction);
4718                        return;
4719                    }
4720                    if !check_signature!(op0, op1, op2)
4721                        || op0.id() + 1 != op1.id()
4722                        || op1.id() + 1 != op2.id()
4723                    {
4724                        self.last_error = Some(AsmError::InvalidInstruction);
4725                        return;
4726                    }
4727                    n = 3;
4728                    st.rm_rel = *op3;
4729                } else if isign4 == enc_ops!(Reg, Reg, Reg, Reg) && o4.is_mem() {
4730                    if op_data.n != 1 && op_data.n != 4 {
4731                        self.last_error = Some(AsmError::InvalidInstruction);
4732                        return;
4733                    }
4734                    if !check_signature!(op0, op1, op2, op3)
4735                        || op0.id() + 1 != op1.id()
4736                        || op1.id() + 1 != op2.id()
4737                        || op2.id() + 1 != op3.id()
4738                    {
4739                        self.last_error = Some(AsmError::InvalidInstruction);
4740                        return;
4741                    }
4742                    n = 4;
4743                    st.rm_rel = *o4;
4744                } else {
4745                    self.last_error = Some(AsmError::InvalidInstruction);
4746                    return;
4747                }
4748
4749                let v = op0.as_::<Vec>();
4750                let m = st.rm_rel.as_::<Mem>();
4751
4752                let mut q = 0u32;
4753                let mut rm = 0u32;
4754                let mut rn = m.base_id();
4755                let sz = (v.element_type() as u32).wrapping_sub(VecElementType::B as u32);
4756                let mut opc_s_size = sz;
4757                let mut offset_possibility = 0u32;
4758
4759                if sz > 3 {
4760                    self.last_error = Some(AsmError::InvalidInstruction);
4761                    return;
4762                }
4763
4764                if m.base_type() != RegType::Gp64 {
4765                    self.last_error = Some(AsmError::InvalidOperand);
4766                    return;
4767                }
4768
4769                if rn > 30 && rn != Gp::ID_SP {
4770                    self.last_error = Some(AsmError::InvalidOperand);
4771                    return;
4772                }
4773
4774                rn &= 31;
4775
4776                if op_data.replicate != 0 {
4777                    if n != op_data.n {
4778                        self.last_error = Some(AsmError::InvalidInstruction);
4779                        return;
4780                    }
4781                    if v.has_element_index() {
4782                        self.last_error = Some(AsmError::InvalidInstruction);
4783                        return;
4784                    }
4785                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4786                    if q > 1 {
4787                        self.last_error = Some(AsmError::InvalidInstruction);
4788                        return;
4789                    }
4790                    st.opcode.reset((op_data.single_op as u32) << 10);
4791                    offset_possibility = (1u32 << sz) * n;
4792                } else if v.has_element_index() {
4793                    if n != op_data.n {
4794                        self.last_error = Some(AsmError::InvalidInstruction);
4795                        return;
4796                    }
4797                    const OPC_S_SIZE_BY_SZ_TABLE: [u32; 4] =
4798                        [0u32 << 3, 2u32 << 3, 4u32 << 3, (4u32 << 3) | 1u32];
4799                    st.opcode.reset((op_data.single_op as u32) << 10);
4800                    opc_s_size = OPC_S_SIZE_BY_SZ_TABLE[sz as usize];
4801                    offset_possibility = (1u32 << sz) * op_data.n;
4802                    let element_index = v.element_index();
4803                    let max_element_index = 15u32 >> sz;
4804                    if element_index > max_element_index {
4805                        self.last_error = Some(AsmError::InvalidOperand);
4806                        return;
4807                    }
4808                    let element_index_shifted = element_index << sz;
4809                    q = element_index_shifted >> 3;
4810                    opc_s_size |= element_index_shifted & 0x7;
4811                } else {
4812                    const OPC_S_SIZE_BY_N_TABLE: [u32; 5] =
4813                        [0u32, 0x7u32 << 2, 0xAu32 << 2, 0x6u32 << 2, 0x2u32 << 2];
4814                    q = (v.reg_type() as u32).wrapping_sub(RegType::Vec64 as u32);
4815                    if q > 1 {
4816                        self.last_error = Some(AsmError::InvalidInstruction);
4817                        return;
4818                    }
4819                    if op_data.n == 1 {
4820                        opc_s_size |= OPC_S_SIZE_BY_N_TABLE[n as usize];
4821                    }
4822                    st.opcode.reset((op_data.multiple_op as u32) << 10);
4823                    offset_possibility = (8u32 << q) * n;
4824                }
4825
4826                if m.has_index() {
4827                    if m.has_offset() || !m.is_post_index() {
4828                        self.last_error = Some(AsmError::InvalidOperand);
4829                        return;
4830                    }
4831                    rm = m.index_id();
4832                    if rm > 30 {
4833                        self.last_error = Some(AsmError::InvalidOperand);
4834                        return;
4835                    }
4836                    st.opcode.0 |= 1 << 23;
4837                } else {
4838                    if m.has_offset() {
4839                        if m.offset() != offset_possibility as i64 || !m.is_post_index() {
4840                            self.last_error = Some(AsmError::InvalidOperand);
4841                            return;
4842                        }
4843                        rm = 31;
4844                        st.opcode.0 |= 1 << 23;
4845                    }
4846                }
4847
4848                st.opcode.add_imm(q, 30);
4849                st.opcode.add_imm(rm, 16);
4850                st.opcode.add_imm(opc_s_size, 10);
4851                st.opcode.add_imm(rn, 5);
4852
4853                st.opcode.add_reg(op0.id(), 0);
4854                emit_op!();
4855            }
4856
4857            Encoding::None | Encoding::Count => (),
4858        }
4859
4860        self.last_error = Some(AsmError::UnsupportedInstruction {
4861            reason: "Unsupported instruction encoding or operand types",
4862        });
4863    }
4864}
4865
4866// @generated AArch64 target features begin
4867/// AArch64 architectural features present in the pinned AsmJit ISA metadata.
4868#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)]
4869#[repr(u8)]
4870pub enum CpuFeature {
4871    Aes,
4872    Asimd,
4873    Bf16,
4874    Bti,
4875    Chk,
4876    Clrbhb,
4877    Crc32,
4878    Cssc,
4879    Dgh,
4880    Dotprod,
4881    Fcma,
4882    Fhm,
4883    Flagm,
4884    Flagm2,
4885    Fp16,
4886    Fp8,
4887    Frintts,
4888    I8Mm,
4889    Jscvt,
4890    Lor,
4891    Lse,
4892    Mte,
4893    Mte2,
4894    Pauth,
4895    Ras,
4896    Rdm,
4897    Sha1,
4898    Sha256,
4899    Sha3,
4900    Sha512,
4901    Sm3,
4902    Sm4,
4903}
4904
4905pub const CPU_FEATURE_COUNT: usize = 32;
4906pub const CPU_FEATURE_NAMES: [&str; CPU_FEATURE_COUNT] = [
4907    "AES", "ASIMD", "BF16", "BTI", "CHK", "CLRBHB", "CRC32", "CSSC", "DGH", "DOTPROD", "FCMA",
4908    "FHM", "FLAGM", "FLAGM2", "FP16", "FP8", "FRINTTS", "I8MM", "JSCVT", "LOR", "LSE", "MTE",
4909    "MTE2", "PAUTH", "RAS", "RDM", "SHA1", "SHA256", "SHA3", "SHA512", "SM3", "SM4",
4910];
4911
4912pub const ALL_CPU_FEATURES: [CpuFeature; CPU_FEATURE_COUNT] = [
4913    CpuFeature::Aes,
4914    CpuFeature::Asimd,
4915    CpuFeature::Bf16,
4916    CpuFeature::Bti,
4917    CpuFeature::Chk,
4918    CpuFeature::Clrbhb,
4919    CpuFeature::Crc32,
4920    CpuFeature::Cssc,
4921    CpuFeature::Dgh,
4922    CpuFeature::Dotprod,
4923    CpuFeature::Fcma,
4924    CpuFeature::Fhm,
4925    CpuFeature::Flagm,
4926    CpuFeature::Flagm2,
4927    CpuFeature::Fp16,
4928    CpuFeature::Fp8,
4929    CpuFeature::Frintts,
4930    CpuFeature::I8Mm,
4931    CpuFeature::Jscvt,
4932    CpuFeature::Lor,
4933    CpuFeature::Lse,
4934    CpuFeature::Mte,
4935    CpuFeature::Mte2,
4936    CpuFeature::Pauth,
4937    CpuFeature::Ras,
4938    CpuFeature::Rdm,
4939    CpuFeature::Sha1,
4940    CpuFeature::Sha256,
4941    CpuFeature::Sha3,
4942    CpuFeature::Sha512,
4943    CpuFeature::Sm3,
4944    CpuFeature::Sm4,
4945];
4946
4947impl CpuFeature {
4948    pub const fn name(self) -> &'static str {
4949        CPU_FEATURE_NAMES[self as usize]
4950    }
4951}
4952
4953const FEATURE_FORM_SIGNATURE_MASK: u32 = OperandSignature::OP_TYPE_MASK
4954    | OperandSignature::REG_TYPE_MASK
4955    | Vec::SIGNATURE_REG_ELEMENT_TYPE_MASK
4956    | Vec::SIGNATURE_REG_ELEMENT_FLAG_MASK;
4957
4958const fn feature_reg_signature(
4959    reg_type: RegType,
4960    element_type: VecElementType,
4961    element_access: bool,
4962) -> u32 {
4963    OperandType::Reg as u32
4964        | (reg_type as u32) << OperandSignature::REG_TYPE_SHIFT
4965        | (element_type as u32) << Vec::SIGNATURE_REG_ELEMENT_TYPE_SHIFT
4966        | (element_access as u32) << Vec::SIGNATURE_REG_ELEMENT_FLAG_SHIFT
4967}
4968
4969struct InstFeatureForm {
4970    opcode_mask: u32,
4971    opcode_value: u32,
4972    operand_signatures: [u32; 6],
4973    required: u64,
4974    context: &'static str,
4975}
4976
4977impl InstFeatureForm {
4978    fn matches(&self, opcode: u32, ops: &[&Operand]) -> bool {
4979        if opcode & self.opcode_mask != self.opcode_value {
4980            return false;
4981        }
4982        self.operand_signatures
4983            .iter()
4984            .enumerate()
4985            .all(|(index, expected)| {
4986                let actual = ops.get(index).map_or(0, |op| op.signature.bits());
4987                actual & FEATURE_FORM_SIGNATURE_MASK == *expected
4988            })
4989    }
4990}
4991
4992/// Conservative required-feature masks, indexed by `InstId as usize`.
4993pub static INST_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
4994    0x0000000000000000, // None
4995    0x0000000000000080, // Abs
4996    0x0000000000000000, // Adc
4997    0x0000000000000000, // Adcs
4998    0x0000000000000000, // Add
4999    0x0000000000200000, // Addg
5000    0x0000000000000000, // Adds
5001    0x0000000000000000, // Adr
5002    0x0000000000000000, // Adrp
5003    0x0000000000000000, // And
5004    0x0000000000000000, // Ands
5005    0x0000000000000000, // Asr
5006    0x0000000000000000, // Asrv
5007    0x0000000000000000, // At
5008    0x0000000000800000, // Autda
5009    0x0000000000800000, // Autdza
5010    0x0000000000800000, // Autdb
5011    0x0000000000800000, // Autdzb
5012    0x0000000000800000, // Autia
5013    0x0000000000800000, // Autia1716
5014    0x0000000000800000, // Autiasp
5015    0x0000000000800000, // Autiaz
5016    0x0000000000800000, // Autib
5017    0x0000000000800000, // Autib1716
5018    0x0000000000800000, // Autibsp
5019    0x0000000000800000, // Autibz
5020    0x0000000000800000, // Autiza
5021    0x0000000000800000, // Autizb
5022    0x0000000000002000, // Axflag
5023    0x0000000000000000, // B
5024    0x0000000000000000, // Bc
5025    0x0000000000000000, // Bfc
5026    0x0000000000000000, // Bfi
5027    0x0000000000000000, // Bfm
5028    0x0000000000000000, // Bfxil
5029    0x0000000000000000, // Bic
5030    0x0000000000000000, // Bics
5031    0x0000000000000000, // Bl
5032    0x0000000000000000, // Blr
5033    0x0000000000000000, // Br
5034    0x0000000000000000, // Brk
5035    0x0000000000000008, // Bti
5036    0x0000000000100000, // Cas
5037    0x0000000000100000, // Casa
5038    0x0000000000100000, // Casab
5039    0x0000000000100000, // Casah
5040    0x0000000000100000, // Casal
5041    0x0000000000100000, // Casalb
5042    0x0000000000100000, // Casalh
5043    0x0000000000100000, // Casb
5044    0x0000000000100000, // Cash
5045    0x0000000000100000, // Casl
5046    0x0000000000100000, // Caslb
5047    0x0000000000100000, // Caslh
5048    0x0000000000100000, // Casp
5049    0x0000000000100000, // Caspa
5050    0x0000000000100000, // Caspal
5051    0x0000000000100000, // Caspl
5052    0x0000000000000000, // Cbnz
5053    0x0000000000000000, // Cbz
5054    0x0000000000000000, // Ccmn
5055    0x0000000000000000, // Ccmp
5056    0x0000000000001000, // Cfinv
5057    0x0000000000000010, // Chkfeat
5058    0x0000000000000000, // Cinc
5059    0x0000000000000000, // Cinv
5060    0x0000000000000020, // Clrbhb
5061    0x0000000000000000, // Clrex
5062    0x0000000000000000, // Cls
5063    0x0000000000000000, // Clz
5064    0x0000000000000000, // Cmn
5065    0x0000000000000000, // Cmp
5066    0x0000000000200000, // Cmpp
5067    0x0000000000000000, // Cneg
5068    0x0000000000000080, // Cnt
5069    0x0000000000000040, // Crc32b
5070    0x0000000000000040, // Crc32cb
5071    0x0000000000000040, // Crc32ch
5072    0x0000000000000040, // Crc32cw
5073    0x0000000000000040, // Crc32cx
5074    0x0000000000000040, // Crc32h
5075    0x0000000000000040, // Crc32w
5076    0x0000000000000040, // Crc32x
5077    0x0000000000000000, // Csdb
5078    0x0000000000000000, // Csel
5079    0x0000000000000000, // Cset
5080    0x0000000000000000, // Csetm
5081    0x0000000000000000, // Csinc
5082    0x0000000000000000, // Csinv
5083    0x0000000000000000, // Csneg
5084    0x0000000000000080, // Ctz
5085    0x0000000000000000, // Dc
5086    0x0000000000000000, // Dcps1
5087    0x0000000000000000, // Dcps2
5088    0x0000000000000000, // Dcps3
5089    0x0000000000000100, // Dgh
5090    0x0000000000000000, // Dmb
5091    0x0000000000000000, // Drps
5092    0x0000000000000000, // Dsb
5093    0x0000000000000000, // Eon
5094    0x0000000000000000, // Eor
5095    0x0000000001000000, // Esb
5096    0x0000000000000000, // Extr
5097    0x0000000000000000, // Eret
5098    0x0000000000200000, // Gmi
5099    0x0000000000000000, // Hint
5100    0x0000000000000000, // Hlt
5101    0x0000000000000000, // Hvc
5102    0x0000000000000000, // Ic
5103    0x0000000000000000, // Isb
5104    0x0000000000100000, // Ldadd
5105    0x0000000000100000, // Ldadda
5106    0x0000000000100000, // Ldaddab
5107    0x0000000000100000, // Ldaddah
5108    0x0000000000100000, // Ldaddal
5109    0x0000000000100000, // Ldaddalb
5110    0x0000000000100000, // Ldaddalh
5111    0x0000000000100000, // Ldaddb
5112    0x0000000000100000, // Ldaddh
5113    0x0000000000100000, // Ldaddl
5114    0x0000000000100000, // Ldaddlb
5115    0x0000000000100000, // Ldaddlh
5116    0x0000000000000000, // Ldar
5117    0x0000000000000000, // Ldarb
5118    0x0000000000000000, // Ldarh
5119    0x0000000000000000, // Ldaxp
5120    0x0000000000000000, // Ldaxr
5121    0x0000000000000000, // Ldaxrb
5122    0x0000000000000000, // Ldaxrh
5123    0x0000000000100000, // Ldclr
5124    0x0000000000100000, // Ldclra
5125    0x0000000000100000, // Ldclrab
5126    0x0000000000100000, // Ldclrah
5127    0x0000000000100000, // Ldclral
5128    0x0000000000100000, // Ldclralb
5129    0x0000000000100000, // Ldclralh
5130    0x0000000000100000, // Ldclrb
5131    0x0000000000100000, // Ldclrh
5132    0x0000000000100000, // Ldclrl
5133    0x0000000000100000, // Ldclrlb
5134    0x0000000000100000, // Ldclrlh
5135    0x0000000000100000, // Ldeor
5136    0x0000000000100000, // Ldeora
5137    0x0000000000100000, // Ldeorab
5138    0x0000000000100000, // Ldeorah
5139    0x0000000000100000, // Ldeoral
5140    0x0000000000100000, // Ldeoralb
5141    0x0000000000100000, // Ldeoralh
5142    0x0000000000100000, // Ldeorb
5143    0x0000000000100000, // Ldeorh
5144    0x0000000000100000, // Ldeorl
5145    0x0000000000100000, // Ldeorlb
5146    0x0000000000100000, // Ldeorlh
5147    0x0000000000200000, // Ldg
5148    0x0000000000400000, // Ldgm
5149    0x0000000000080000, // Ldlar
5150    0x0000000000080000, // Ldlarb
5151    0x0000000000080000, // Ldlarh
5152    0x0000000000000000, // Ldnp
5153    0x0000000000000000, // Ldp
5154    0x0000000000000000, // Ldpsw
5155    0x0000000000000000, // Ldr
5156    0x0000000000800000, // Ldraa
5157    0x0000000000800000, // Ldrab
5158    0x0000000000000000, // Ldrb
5159    0x0000000000000000, // Ldrh
5160    0x0000000000000000, // Ldrsb
5161    0x0000000000000000, // Ldrsh
5162    0x0000000000000000, // Ldrsw
5163    0x0000000000100000, // Ldset
5164    0x0000000000100000, // Ldseta
5165    0x0000000000100000, // Ldsetab
5166    0x0000000000100000, // Ldsetah
5167    0x0000000000100000, // Ldsetal
5168    0x0000000000100000, // Ldsetalb
5169    0x0000000000100000, // Ldsetalh
5170    0x0000000000100000, // Ldsetb
5171    0x0000000000100000, // Ldseth
5172    0x0000000000100000, // Ldsetl
5173    0x0000000000100000, // Ldsetlb
5174    0x0000000000100000, // Ldsetlh
5175    0x0000000000100000, // Ldsmax
5176    0x0000000000100000, // Ldsmaxa
5177    0x0000000000100000, // Ldsmaxab
5178    0x0000000000100000, // Ldsmaxah
5179    0x0000000000100000, // Ldsmaxal
5180    0x0000000000100000, // Ldsmaxalb
5181    0x0000000000100000, // Ldsmaxalh
5182    0x0000000000100000, // Ldsmaxb
5183    0x0000000000100000, // Ldsmaxh
5184    0x0000000000100000, // Ldsmaxl
5185    0x0000000000100000, // Ldsmaxlb
5186    0x0000000000100000, // Ldsmaxlh
5187    0x0000000000100000, // Ldsmin
5188    0x0000000000100000, // Ldsmina
5189    0x0000000000100000, // Ldsminab
5190    0x0000000000100000, // Ldsminah
5191    0x0000000000100000, // Ldsminal
5192    0x0000000000100000, // Ldsminalb
5193    0x0000000000100000, // Ldsminalh
5194    0x0000000000100000, // Ldsminb
5195    0x0000000000100000, // Ldsminh
5196    0x0000000000100000, // Ldsminl
5197    0x0000000000100000, // Ldsminlb
5198    0x0000000000100000, // Ldsminlh
5199    0x0000000000000000, // Ldtr
5200    0x0000000000000000, // Ldtrb
5201    0x0000000000000000, // Ldtrh
5202    0x0000000000000000, // Ldtrsb
5203    0x0000000000000000, // Ldtrsh
5204    0x0000000000000000, // Ldtrsw
5205    0x0000000000100000, // Ldumax
5206    0x0000000000100000, // Ldumaxa
5207    0x0000000000100000, // Ldumaxab
5208    0x0000000000100000, // Ldumaxah
5209    0x0000000000100000, // Ldumaxal
5210    0x0000000000100000, // Ldumaxalb
5211    0x0000000000100000, // Ldumaxalh
5212    0x0000000000100000, // Ldumaxb
5213    0x0000000000100000, // Ldumaxh
5214    0x0000000000100000, // Ldumaxl
5215    0x0000000000100000, // Ldumaxlb
5216    0x0000000000100000, // Ldumaxlh
5217    0x0000000000100000, // Ldumin
5218    0x0000000000100000, // Ldumina
5219    0x0000000000100000, // Lduminab
5220    0x0000000000100000, // Lduminah
5221    0x0000000000100000, // Lduminal
5222    0x0000000000100000, // Lduminalb
5223    0x0000000000100000, // Lduminalh
5224    0x0000000000100000, // Lduminb
5225    0x0000000000100000, // Lduminh
5226    0x0000000000100000, // Lduminl
5227    0x0000000000100000, // Lduminlb
5228    0x0000000000100000, // Lduminlh
5229    0x0000000000000000, // Ldur
5230    0x0000000000000000, // Ldurb
5231    0x0000000000000000, // Ldurh
5232    0x0000000000000000, // Ldursb
5233    0x0000000000000000, // Ldursh
5234    0x0000000000000000, // Ldursw
5235    0x0000000000000000, // Ldxp
5236    0x0000000000000000, // Ldxr
5237    0x0000000000000000, // Ldxrb
5238    0x0000000000000000, // Ldxrh
5239    0x0000000000000000, // Lsl
5240    0x0000000000000000, // Lslv
5241    0x0000000000000000, // Lsr
5242    0x0000000000000000, // Lsrv
5243    0x0000000000000000, // Madd
5244    0x0000000000000000, // Mneg
5245    0x0000000000000000, // Mov
5246    0x0000000000000000, // Movk
5247    0x0000000000000000, // Movn
5248    0x0000000000000000, // Movz
5249    0x0000000000000000, // Mrs
5250    0x0000000000000000, // Msr
5251    0x0000000000000000, // Msub
5252    0x0000000000000000, // Mul
5253    0x0000000000000000, // Mvn
5254    0x0000000000000000, // Neg
5255    0x0000000000000000, // Negs
5256    0x0000000000000000, // Ngc
5257    0x0000000000000000, // Ngcs
5258    0x0000000000000000, // Nop
5259    0x0000000000000000, // Orn
5260    0x0000000000000000, // Orr
5261    0x0000000000800000, // Pacda
5262    0x0000000000800000, // Pacdb
5263    0x0000000000800000, // Pacdza
5264    0x0000000000800000, // Pacdzb
5265    0x0000000000800000, // Pacga
5266    0x0000000000000000, // Prfm
5267    0x0000000000000000, // Pssbb
5268    0x0000000000000000, // Rbit
5269    0x0000000000000000, // Ret
5270    0x0000000000000000, // Rev
5271    0x0000000000000000, // Rev16
5272    0x0000000000000000, // Rev32
5273    0x0000000000000000, // Rev64
5274    0x0000000000000000, // Ror
5275    0x0000000000000000, // Rorv
5276    0x0000000000000000, // Sbc
5277    0x0000000000000000, // Sbcs
5278    0x0000000000000000, // Sbfiz
5279    0x0000000000000000, // Sbfm
5280    0x0000000000000000, // Sbfx
5281    0x0000000000000000, // Sdiv
5282    0x0000000000001000, // Setf8
5283    0x0000000000001000, // Setf16
5284    0x0000000000000000, // Sev
5285    0x0000000000000000, // Sevl
5286    0x0000000000000000, // Smaddl
5287    0x0000000000000080, // Smax
5288    0x0000000000000000, // Smc
5289    0x0000000000000080, // Smin
5290    0x0000000000000000, // Smnegl
5291    0x0000000000000000, // Smsubl
5292    0x0000000000000000, // Smulh
5293    0x0000000000000000, // Smull
5294    0x0000000000000000, // Ssbb
5295    0x0000000000200000, // St2g
5296    0x0000000000100000, // Stadd
5297    0x0000000000100000, // Staddl
5298    0x0000000000100000, // Staddb
5299    0x0000000000100000, // Staddlb
5300    0x0000000000100000, // Staddh
5301    0x0000000000100000, // Staddlh
5302    0x0000000000100000, // Stclr
5303    0x0000000000100000, // Stclrl
5304    0x0000000000100000, // Stclrb
5305    0x0000000000100000, // Stclrlb
5306    0x0000000000100000, // Stclrh
5307    0x0000000000100000, // Stclrlh
5308    0x0000000000100000, // Steor
5309    0x0000000000100000, // Steorl
5310    0x0000000000100000, // Steorb
5311    0x0000000000100000, // Steorlb
5312    0x0000000000100000, // Steorh
5313    0x0000000000100000, // Steorlh
5314    0x0000000000200000, // Stg
5315    0x0000000000400000, // Stgm
5316    0x0000000000200000, // Stgp
5317    0x0000000000080000, // Stllr
5318    0x0000000000080000, // Stllrb
5319    0x0000000000080000, // Stllrh
5320    0x0000000000000000, // Stlr
5321    0x0000000000000000, // Stlrb
5322    0x0000000000000000, // Stlrh
5323    0x0000000000000000, // Stlxp
5324    0x0000000000000000, // Stlxr
5325    0x0000000000000000, // Stlxrb
5326    0x0000000000000000, // Stlxrh
5327    0x0000000000000000, // Stnp
5328    0x0000000000000000, // Stp
5329    0x0000000000000000, // Str
5330    0x0000000000000000, // Strb
5331    0x0000000000000000, // Strh
5332    0x0000000000100000, // Stset
5333    0x0000000000100000, // Stsetl
5334    0x0000000000100000, // Stsetb
5335    0x0000000000100000, // Stsetlb
5336    0x0000000000100000, // Stseth
5337    0x0000000000100000, // Stsetlh
5338    0x0000000000100000, // Stsmax
5339    0x0000000000100000, // Stsmaxl
5340    0x0000000000100000, // Stsmaxb
5341    0x0000000000100000, // Stsmaxlb
5342    0x0000000000100000, // Stsmaxh
5343    0x0000000000100000, // Stsmaxlh
5344    0x0000000000100000, // Stsmin
5345    0x0000000000100000, // Stsminl
5346    0x0000000000100000, // Stsminb
5347    0x0000000000100000, // Stsminlb
5348    0x0000000000100000, // Stsminh
5349    0x0000000000100000, // Stsminlh
5350    0x0000000000000000, // Sttr
5351    0x0000000000000000, // Sttrb
5352    0x0000000000000000, // Sttrh
5353    0x0000000000100000, // Stumax
5354    0x0000000000100000, // Stumaxl
5355    0x0000000000100000, // Stumaxb
5356    0x0000000000100000, // Stumaxlb
5357    0x0000000000100000, // Stumaxh
5358    0x0000000000100000, // Stumaxlh
5359    0x0000000000100000, // Stumin
5360    0x0000000000100000, // Stuminl
5361    0x0000000000100000, // Stuminb
5362    0x0000000000100000, // Stuminlb
5363    0x0000000000100000, // Stuminh
5364    0x0000000000100000, // Stuminlh
5365    0x0000000000000000, // Stur
5366    0x0000000000000000, // Sturb
5367    0x0000000000000000, // Sturh
5368    0x0000000000000000, // Stxp
5369    0x0000000000000000, // Stxr
5370    0x0000000000000000, // Stxrb
5371    0x0000000000000000, // Stxrh
5372    0x0000000000200000, // Stz2g
5373    0x0000000000200000, // Stzg
5374    0x0000000000400000, // Stzgm
5375    0x0000000000000000, // Sub
5376    0x0000000000200000, // Subg
5377    0x0000000000200000, // Subp
5378    0x0000000000200000, // Subps
5379    0x0000000000000000, // Subs
5380    0x0000000000000000, // Svc
5381    0x0000000000100000, // Swp
5382    0x0000000000100000, // Swpa
5383    0x0000000000100000, // Swpab
5384    0x0000000000100000, // Swpah
5385    0x0000000000100000, // Swpal
5386    0x0000000000100000, // Swpalb
5387    0x0000000000100000, // Swpalh
5388    0x0000000000100000, // Swpb
5389    0x0000000000100000, // Swph
5390    0x0000000000100000, // Swpl
5391    0x0000000000100000, // Swplb
5392    0x0000000000100000, // Swplh
5393    0x0000000000000000, // Sxtb
5394    0x0000000000000000, // Sxth
5395    0x0000000000000000, // Sxtw
5396    0x0000000000000000, // Sys
5397    0x0000000000000000, // Tlbi
5398    0x0000000000000000, // Tst
5399    0x0000000000000000, // Tbnz
5400    0x0000000000000000, // Tbz
5401    0x0000000000000000, // Ubfiz
5402    0x0000000000000000, // Ubfm
5403    0x0000000000000000, // Ubfx
5404    0x0000000000000000, // Udf
5405    0x0000000000000000, // Udiv
5406    0x0000000000000000, // Umaddl
5407    0x0000000000000080, // Umax
5408    0x0000000000000080, // Umin
5409    0x0000000000000000, // Umnegl
5410    0x0000000000000000, // Umull
5411    0x0000000000000000, // Umulh
5412    0x0000000000000000, // Umsubl
5413    0x0000000000000000, // Uxtb
5414    0x0000000000000000, // Uxth
5415    0x0000000000000000, // Wfe
5416    0x0000000000000000, // Wfi
5417    0x0000000000002000, // Xaflag
5418    0x0000000000800000, // Xpacd
5419    0x0000000000800000, // Xpaci
5420    0x0000000000800000, // Xpaclri
5421    0x0000000000000000, // Yield
5422    0x0000000000000002, // Abs_v
5423    0x0000000000000002, // Add_v
5424    0x0000000000000002, // Addhn_v
5425    0x0000000000000002, // Addhn2_v
5426    0x0000000000000002, // Addp_v
5427    0x0000000000000002, // Addv_v
5428    0x0000000000000003, // Aesd_v
5429    0x0000000000000003, // Aese_v
5430    0x0000000000000003, // Aesimc_v
5431    0x0000000000000003, // Aesmc_v
5432    0x0000000000000002, // And_v
5433    0x0000000010000002, // Bcax_v
5434    0x0000000000000006, // Bfcvt_v
5435    0x0000000000000006, // Bfcvtn_v
5436    0x0000000000000006, // Bfcvtn2_v
5437    0x0000000000000006, // Bfdot_v
5438    0x0000000000000006, // Bfmlalb_v
5439    0x0000000000000006, // Bfmlalt_v
5440    0x0000000000000006, // Bfmmla_v
5441    0x0000000000000002, // Bic_v
5442    0x0000000000000002, // Bif_v
5443    0x0000000000000002, // Bit_v
5444    0x0000000000000002, // Bsl_v
5445    0x0000000000000002, // Cls_v
5446    0x0000000000000002, // Clz_v
5447    0x0000000000000002, // Cmeq_v
5448    0x0000000000000002, // Cmge_v
5449    0x0000000000000002, // Cmgt_v
5450    0x0000000000000002, // Cmhi_v
5451    0x0000000000000002, // Cmhs_v
5452    0x0000000000000002, // Cmle_v
5453    0x0000000000000002, // Cmlt_v
5454    0x0000000000000002, // Cmtst_v
5455    0x0000000000000002, // Cnt_v
5456    0x0000000000000002, // Dup_v
5457    0x0000000000000002, // Eor_v
5458    0x0000000010000002, // Eor3_v
5459    0x0000000000000002, // Ext_v
5460    0x0000000000004002, // Fabd_v
5461    0x0000000000004002, // Fabs_v
5462    0x0000000000004002, // Facge_v
5463    0x0000000000004002, // Facgt_v
5464    0x0000000000004002, // Fadd_v
5465    0x0000000000004002, // Faddp_v
5466    0x0000000000000402, // Fcadd_v
5467    0x0000000000004002, // Fccmp_v
5468    0x0000000000004002, // Fccmpe_v
5469    0x0000000000004002, // Fcmeq_v
5470    0x0000000000004002, // Fcmge_v
5471    0x0000000000004002, // Fcmgt_v
5472    0x0000000000000402, // Fcmla_v
5473    0x0000000000004002, // Fcmle_v
5474    0x0000000000004002, // Fcmlt_v
5475    0x0000000000004002, // Fcmp_v
5476    0x0000000000004002, // Fcmpe_v
5477    0x0000000000004002, // Fcsel_v
5478    0x0000000000000002, // Fcvt_v
5479    0x0000000000004002, // Fcvtas_v
5480    0x0000000000004002, // Fcvtau_v
5481    0x0000000000000002, // Fcvtl_v
5482    0x0000000000000002, // Fcvtl2_v
5483    0x0000000000004002, // Fcvtms_v
5484    0x0000000000004002, // Fcvtmu_v
5485    0x0000000000008002, // Fcvtn_v
5486    0x0000000000008002, // Fcvtn2_v
5487    0x0000000000004002, // Fcvtns_v
5488    0x0000000000004002, // Fcvtnu_v
5489    0x0000000000004002, // Fcvtps_v
5490    0x0000000000004002, // Fcvtpu_v
5491    0x0000000000000000, // Fcvtxn_v
5492    0x0000000000000000, // Fcvtxn2_v
5493    0x0000000000004002, // Fcvtzs_v
5494    0x0000000000004002, // Fcvtzu_v
5495    0x0000000000004002, // Fdiv_v
5496    0x0000000000040002, // Fjcvtzs_v
5497    0x0000000000004002, // Fmadd_v
5498    0x0000000000004002, // Fmax_v
5499    0x0000000000004002, // Fmaxnm_v
5500    0x0000000000004002, // Fmaxnmp_v
5501    0x0000000000004002, // Fmaxnmv_v
5502    0x0000000000004002, // Fmaxp_v
5503    0x0000000000004002, // Fmaxv_v
5504    0x0000000000004002, // Fmin_v
5505    0x0000000000004002, // Fminnm_v
5506    0x0000000000004002, // Fminnmp_v
5507    0x0000000000004002, // Fminnmv_v
5508    0x0000000000004002, // Fminp_v
5509    0x0000000000004002, // Fminv_v
5510    0x0000000000004002, // Fmla_v
5511    0x0000000000000802, // Fmlal_v
5512    0x0000000000000802, // Fmlal2_v
5513    0x0000000000004002, // Fmls_v
5514    0x0000000000000802, // Fmlsl_v
5515    0x0000000000000802, // Fmlsl2_v
5516    0x0000000000004002, // Fmov_v
5517    0x0000000000004002, // Fmsub_v
5518    0x0000000000004002, // Fmul_v
5519    0x0000000000004002, // Fmulx_v
5520    0x0000000000004002, // Fneg_v
5521    0x0000000000004002, // Fnmadd_v
5522    0x0000000000004002, // Fnmsub_v
5523    0x0000000000004002, // Fnmul_v
5524    0x0000000000004002, // Frecpe_v
5525    0x0000000000004002, // Frecps_v
5526    0x0000000000004002, // Frecpx_v
5527    0x0000000000010002, // Frint32x_v
5528    0x0000000000010002, // Frint32z_v
5529    0x0000000000010002, // Frint64x_v
5530    0x0000000000010002, // Frint64z_v
5531    0x0000000000004002, // Frinta_v
5532    0x0000000000004002, // Frinti_v
5533    0x0000000000004002, // Frintm_v
5534    0x0000000000004002, // Frintn_v
5535    0x0000000000004002, // Frintp_v
5536    0x0000000000004002, // Frintx_v
5537    0x0000000000004002, // Frintz_v
5538    0x0000000000004002, // Frsqrte_v
5539    0x0000000000004002, // Frsqrts_v
5540    0x0000000000004002, // Fsqrt_v
5541    0x0000000000004002, // Fsub_v
5542    0x0000000000000002, // Ins_v
5543    0x0000000000000002, // Ld1_v
5544    0x0000000000000002, // Ld1r_v
5545    0x0000000000000002, // Ld2_v
5546    0x0000000000000002, // Ld2r_v
5547    0x0000000000000002, // Ld3_v
5548    0x0000000000000002, // Ld3r_v
5549    0x0000000000000002, // Ld4_v
5550    0x0000000000000002, // Ld4r_v
5551    0x0000000000000002, // Ldnp_v
5552    0x0000000000000002, // Ldp_v
5553    0x0000000000000002, // Ldr_v
5554    0x0000000000000002, // Ldur_v
5555    0x0000000000000002, // Mla_v
5556    0x0000000000000002, // Mls_v
5557    0x0000000000000002, // Mov_v
5558    0x0000000000000002, // Movi_v
5559    0x0000000000000002, // Mul_v
5560    0x0000000000000002, // Mvn_v
5561    0x0000000000000002, // Mvni_v
5562    0x0000000000000002, // Neg_v
5563    0x0000000000000002, // Not_v
5564    0x0000000000000002, // Orn_v
5565    0x0000000000000002, // Orr_v
5566    0x0000000000000002, // Pmul_v
5567    0x0000000000000002, // Pmull_v
5568    0x0000000000000002, // Pmull2_v
5569    0x0000000000000002, // Raddhn_v
5570    0x0000000000000002, // Raddhn2_v
5571    0x0000000010000002, // Rax1_v
5572    0x0000000000000002, // Rbit_v
5573    0x0000000000000002, // Rev16_v
5574    0x0000000000000002, // Rev32_v
5575    0x0000000000000002, // Rev64_v
5576    0x0000000000000002, // Rshrn_v
5577    0x0000000000000002, // Rshrn2_v
5578    0x0000000000000002, // Rsubhn_v
5579    0x0000000000000002, // Rsubhn2_v
5580    0x0000000000000002, // Saba_v
5581    0x0000000000000002, // Sabal_v
5582    0x0000000000000002, // Sabal2_v
5583    0x0000000000000002, // Sabd_v
5584    0x0000000000000002, // Sabdl_v
5585    0x0000000000000002, // Sabdl2_v
5586    0x0000000000000002, // Sadalp_v
5587    0x0000000000000002, // Saddl_v
5588    0x0000000000000002, // Saddl2_v
5589    0x0000000000000002, // Saddlp_v
5590    0x0000000000000002, // Saddlv_v
5591    0x0000000000000002, // Saddw_v
5592    0x0000000000000002, // Saddw2_v
5593    0x0000000000004002, // Scvtf_v
5594    0x0000000000000202, // Sdot_v
5595    0x0000000004000002, // Sha1c_v
5596    0x0000000004000002, // Sha1h_v
5597    0x0000000004000002, // Sha1m_v
5598    0x0000000004000002, // Sha1p_v
5599    0x0000000004000002, // Sha1su0_v
5600    0x0000000004000002, // Sha1su1_v
5601    0x0000000008000002, // Sha256h_v
5602    0x0000000008000002, // Sha256h2_v
5603    0x0000000008000002, // Sha256su0_v
5604    0x0000000008000002, // Sha256su1_v
5605    0x0000000020000002, // Sha512h_v
5606    0x0000000020000002, // Sha512h2_v
5607    0x0000000020000002, // Sha512su0_v
5608    0x0000000020000002, // Sha512su1_v
5609    0x0000000000000002, // Shadd_v
5610    0x0000000000000002, // Shl_v
5611    0x0000000000000002, // Shll_v
5612    0x0000000000000002, // Shll2_v
5613    0x0000000000000002, // Shrn_v
5614    0x0000000000000002, // Shrn2_v
5615    0x0000000000000002, // Shsub_v
5616    0x0000000000000002, // Sli_v
5617    0x0000000040000002, // Sm3partw1_v
5618    0x0000000040000002, // Sm3partw2_v
5619    0x0000000040000002, // Sm3ss1_v
5620    0x0000000040000002, // Sm3tt1a_v
5621    0x0000000040000002, // Sm3tt1b_v
5622    0x0000000040000002, // Sm3tt2a_v
5623    0x0000000040000002, // Sm3tt2b_v
5624    0x0000000080000002, // Sm4e_v
5625    0x0000000080000002, // Sm4ekey_v
5626    0x0000000000000002, // Smax_v
5627    0x0000000000000002, // Smaxp_v
5628    0x0000000000000002, // Smaxv_v
5629    0x0000000000000002, // Smin_v
5630    0x0000000000000002, // Sminp_v
5631    0x0000000000000002, // Sminv_v
5632    0x0000000000000002, // Smlal_v
5633    0x0000000000000002, // Smlal2_v
5634    0x0000000000000002, // Smlsl_v
5635    0x0000000000000002, // Smlsl2_v
5636    0x0000000000020002, // Smmla_v
5637    0x0000000000000002, // Smov_v
5638    0x0000000000000002, // Smull_v
5639    0x0000000000000002, // Smull2_v
5640    0x0000000000000002, // Sqabs_v
5641    0x0000000000000002, // Sqadd_v
5642    0x0000000000000002, // Sqdmlal_v
5643    0x0000000000000002, // Sqdmlal2_v
5644    0x0000000000000002, // Sqdmlsl_v
5645    0x0000000000000002, // Sqdmlsl2_v
5646    0x0000000000000002, // Sqdmulh_v
5647    0x0000000000000002, // Sqdmull_v
5648    0x0000000000000002, // Sqdmull2_v
5649    0x0000000000000002, // Sqneg_v
5650    0x0000000002000002, // Sqrdmlah_v
5651    0x0000000002000002, // Sqrdmlsh_v
5652    0x0000000000000002, // Sqrdmulh_v
5653    0x0000000000000002, // Sqrshl_v
5654    0x0000000000000002, // Sqrshrn_v
5655    0x0000000000000002, // Sqrshrn2_v
5656    0x0000000000000002, // Sqrshrun_v
5657    0x0000000000000002, // Sqrshrun2_v
5658    0x0000000000000002, // Sqshl_v
5659    0x0000000000000002, // Sqshlu_v
5660    0x0000000000000002, // Sqshrn_v
5661    0x0000000000000002, // Sqshrn2_v
5662    0x0000000000000002, // Sqshrun_v
5663    0x0000000000000002, // Sqshrun2_v
5664    0x0000000000000002, // Sqsub_v
5665    0x0000000000000002, // Sqxtn_v
5666    0x0000000000000002, // Sqxtn2_v
5667    0x0000000000000002, // Sqxtun_v
5668    0x0000000000000002, // Sqxtun2_v
5669    0x0000000000000002, // Srhadd_v
5670    0x0000000000000002, // Sri_v
5671    0x0000000000000002, // Srshl_v
5672    0x0000000000000002, // Srshr_v
5673    0x0000000000000002, // Srsra_v
5674    0x0000000000000002, // Sshl_v
5675    0x0000000000000002, // Sshll_v
5676    0x0000000000000002, // Sshll2_v
5677    0x0000000000000002, // Sshr_v
5678    0x0000000000000002, // Ssra_v
5679    0x0000000000000002, // Ssubl_v
5680    0x0000000000000002, // Ssubl2_v
5681    0x0000000000000002, // Ssubw_v
5682    0x0000000000000002, // Ssubw2_v
5683    0x0000000000000002, // St1_v
5684    0x0000000000000002, // St2_v
5685    0x0000000000000002, // St3_v
5686    0x0000000000000002, // St4_v
5687    0x0000000000000002, // Stnp_v
5688    0x0000000000000002, // Stp_v
5689    0x0000000000000002, // Str_v
5690    0x0000000000000002, // Stur_v
5691    0x0000000000000002, // Sub_v
5692    0x0000000000000002, // Subhn_v
5693    0x0000000000000002, // Subhn2_v
5694    0x0000000000020002, // Sudot_v
5695    0x0000000000000002, // Suqadd_v
5696    0x0000000000000002, // Sxtl_v
5697    0x0000000000000002, // Sxtl2_v
5698    0x0000000000000002, // Tbl_v
5699    0x0000000000000002, // Tbx_v
5700    0x0000000000000002, // Trn1_v
5701    0x0000000000000002, // Trn2_v
5702    0x0000000000000002, // Uaba_v
5703    0x0000000000000002, // Uabal_v
5704    0x0000000000000002, // Uabal2_v
5705    0x0000000000000002, // Uabd_v
5706    0x0000000000000002, // Uabdl_v
5707    0x0000000000000002, // Uabdl2_v
5708    0x0000000000000002, // Uadalp_v
5709    0x0000000000000002, // Uaddl_v
5710    0x0000000000000002, // Uaddl2_v
5711    0x0000000000000002, // Uaddlp_v
5712    0x0000000000000002, // Uaddlv_v
5713    0x0000000000000002, // Uaddw_v
5714    0x0000000000000002, // Uaddw2_v
5715    0x0000000000004002, // Ucvtf_v
5716    0x0000000000000202, // Udot_v
5717    0x0000000000000002, // Uhadd_v
5718    0x0000000000000002, // Uhsub_v
5719    0x0000000000000002, // Umax_v
5720    0x0000000000000002, // Umaxp_v
5721    0x0000000000000002, // Umaxv_v
5722    0x0000000000000002, // Umin_v
5723    0x0000000000000002, // Uminp_v
5724    0x0000000000000002, // Uminv_v
5725    0x0000000000000002, // Umlal_v
5726    0x0000000000000002, // Umlal2_v
5727    0x0000000000000002, // Umlsl_v
5728    0x0000000000000002, // Umlsl2_v
5729    0x0000000000020002, // Ummla_v
5730    0x0000000000000002, // Umov_v
5731    0x0000000000000002, // Umull_v
5732    0x0000000000000002, // Umull2_v
5733    0x0000000000000002, // Uqadd_v
5734    0x0000000000000002, // Uqrshl_v
5735    0x0000000000000002, // Uqrshrn_v
5736    0x0000000000000002, // Uqrshrn2_v
5737    0x0000000000000002, // Uqshl_v
5738    0x0000000000000002, // Uqshrn_v
5739    0x0000000000000002, // Uqshrn2_v
5740    0x0000000000000002, // Uqsub_v
5741    0x0000000000000002, // Uqxtn_v
5742    0x0000000000000002, // Uqxtn2_v
5743    0x0000000000000002, // Urecpe_v
5744    0x0000000000000002, // Urhadd_v
5745    0x0000000000000002, // Urshl_v
5746    0x0000000000000002, // Urshr_v
5747    0x0000000000000002, // Ursqrte_v
5748    0x0000000000000002, // Ursra_v
5749    0x0000000000020002, // Usdot_v
5750    0x0000000000000002, // Ushl_v
5751    0x0000000000000002, // Ushll_v
5752    0x0000000000000002, // Ushll2_v
5753    0x0000000000000002, // Ushr_v
5754    0x0000000000020002, // Usmmla_v
5755    0x0000000000000002, // Usqadd_v
5756    0x0000000000000002, // Usra_v
5757    0x0000000000000002, // Usubl_v
5758    0x0000000000000002, // Usubl2_v
5759    0x0000000000000002, // Usubw_v
5760    0x0000000000000002, // Usubw2_v
5761    0x0000000000000002, // Uxtl_v
5762    0x0000000000000002, // Uxtl2_v
5763    0x0000000000000002, // Uzp1_v
5764    0x0000000000000002, // Uzp2_v
5765    0x0000000010000002, // Xar_v
5766    0x0000000000000002, // Xtn_v
5767    0x0000000000000002, // Xtn2_v
5768    0x0000000000000002, // Zip1_v
5769    0x0000000000000002, // Zip2_v
5770];
5771
5772/// Requirements common to every form, indexed by `InstId as usize`.
5773static INST_BASE_FEATURE_MASKS: [u64; InstId::_Count as usize] = [
5774    0x0000000000000000, // None
5775    0x0000000000000080, // Abs
5776    0x0000000000000000, // Adc
5777    0x0000000000000000, // Adcs
5778    0x0000000000000000, // Add
5779    0x0000000000200000, // Addg
5780    0x0000000000000000, // Adds
5781    0x0000000000000000, // Adr
5782    0x0000000000000000, // Adrp
5783    0x0000000000000000, // And
5784    0x0000000000000000, // Ands
5785    0x0000000000000000, // Asr
5786    0x0000000000000000, // Asrv
5787    0x0000000000000000, // At
5788    0x0000000000800000, // Autda
5789    0x0000000000800000, // Autdza
5790    0x0000000000800000, // Autdb
5791    0x0000000000800000, // Autdzb
5792    0x0000000000800000, // Autia
5793    0x0000000000800000, // Autia1716
5794    0x0000000000800000, // Autiasp
5795    0x0000000000800000, // Autiaz
5796    0x0000000000800000, // Autib
5797    0x0000000000800000, // Autib1716
5798    0x0000000000800000, // Autibsp
5799    0x0000000000800000, // Autibz
5800    0x0000000000800000, // Autiza
5801    0x0000000000800000, // Autizb
5802    0x0000000000002000, // Axflag
5803    0x0000000000000000, // B
5804    0x0000000000000000, // Bc
5805    0x0000000000000000, // Bfc
5806    0x0000000000000000, // Bfi
5807    0x0000000000000000, // Bfm
5808    0x0000000000000000, // Bfxil
5809    0x0000000000000000, // Bic
5810    0x0000000000000000, // Bics
5811    0x0000000000000000, // Bl
5812    0x0000000000000000, // Blr
5813    0x0000000000000000, // Br
5814    0x0000000000000000, // Brk
5815    0x0000000000000008, // Bti
5816    0x0000000000100000, // Cas
5817    0x0000000000100000, // Casa
5818    0x0000000000100000, // Casab
5819    0x0000000000100000, // Casah
5820    0x0000000000100000, // Casal
5821    0x0000000000100000, // Casalb
5822    0x0000000000100000, // Casalh
5823    0x0000000000100000, // Casb
5824    0x0000000000100000, // Cash
5825    0x0000000000100000, // Casl
5826    0x0000000000100000, // Caslb
5827    0x0000000000100000, // Caslh
5828    0x0000000000100000, // Casp
5829    0x0000000000100000, // Caspa
5830    0x0000000000100000, // Caspal
5831    0x0000000000100000, // Caspl
5832    0x0000000000000000, // Cbnz
5833    0x0000000000000000, // Cbz
5834    0x0000000000000000, // Ccmn
5835    0x0000000000000000, // Ccmp
5836    0x0000000000001000, // Cfinv
5837    0x0000000000000010, // Chkfeat
5838    0x0000000000000000, // Cinc
5839    0x0000000000000000, // Cinv
5840    0x0000000000000020, // Clrbhb
5841    0x0000000000000000, // Clrex
5842    0x0000000000000000, // Cls
5843    0x0000000000000000, // Clz
5844    0x0000000000000000, // Cmn
5845    0x0000000000000000, // Cmp
5846    0x0000000000200000, // Cmpp
5847    0x0000000000000000, // Cneg
5848    0x0000000000000080, // Cnt
5849    0x0000000000000040, // Crc32b
5850    0x0000000000000040, // Crc32cb
5851    0x0000000000000040, // Crc32ch
5852    0x0000000000000040, // Crc32cw
5853    0x0000000000000040, // Crc32cx
5854    0x0000000000000040, // Crc32h
5855    0x0000000000000040, // Crc32w
5856    0x0000000000000040, // Crc32x
5857    0x0000000000000000, // Csdb
5858    0x0000000000000000, // Csel
5859    0x0000000000000000, // Cset
5860    0x0000000000000000, // Csetm
5861    0x0000000000000000, // Csinc
5862    0x0000000000000000, // Csinv
5863    0x0000000000000000, // Csneg
5864    0x0000000000000080, // Ctz
5865    0x0000000000000000, // Dc
5866    0x0000000000000000, // Dcps1
5867    0x0000000000000000, // Dcps2
5868    0x0000000000000000, // Dcps3
5869    0x0000000000000100, // Dgh
5870    0x0000000000000000, // Dmb
5871    0x0000000000000000, // Drps
5872    0x0000000000000000, // Dsb
5873    0x0000000000000000, // Eon
5874    0x0000000000000000, // Eor
5875    0x0000000001000000, // Esb
5876    0x0000000000000000, // Extr
5877    0x0000000000000000, // Eret
5878    0x0000000000200000, // Gmi
5879    0x0000000000000000, // Hint
5880    0x0000000000000000, // Hlt
5881    0x0000000000000000, // Hvc
5882    0x0000000000000000, // Ic
5883    0x0000000000000000, // Isb
5884    0x0000000000100000, // Ldadd
5885    0x0000000000100000, // Ldadda
5886    0x0000000000100000, // Ldaddab
5887    0x0000000000100000, // Ldaddah
5888    0x0000000000100000, // Ldaddal
5889    0x0000000000100000, // Ldaddalb
5890    0x0000000000100000, // Ldaddalh
5891    0x0000000000100000, // Ldaddb
5892    0x0000000000100000, // Ldaddh
5893    0x0000000000100000, // Ldaddl
5894    0x0000000000100000, // Ldaddlb
5895    0x0000000000100000, // Ldaddlh
5896    0x0000000000000000, // Ldar
5897    0x0000000000000000, // Ldarb
5898    0x0000000000000000, // Ldarh
5899    0x0000000000000000, // Ldaxp
5900    0x0000000000000000, // Ldaxr
5901    0x0000000000000000, // Ldaxrb
5902    0x0000000000000000, // Ldaxrh
5903    0x0000000000100000, // Ldclr
5904    0x0000000000100000, // Ldclra
5905    0x0000000000100000, // Ldclrab
5906    0x0000000000100000, // Ldclrah
5907    0x0000000000100000, // Ldclral
5908    0x0000000000100000, // Ldclralb
5909    0x0000000000100000, // Ldclralh
5910    0x0000000000100000, // Ldclrb
5911    0x0000000000100000, // Ldclrh
5912    0x0000000000100000, // Ldclrl
5913    0x0000000000100000, // Ldclrlb
5914    0x0000000000100000, // Ldclrlh
5915    0x0000000000100000, // Ldeor
5916    0x0000000000100000, // Ldeora
5917    0x0000000000100000, // Ldeorab
5918    0x0000000000100000, // Ldeorah
5919    0x0000000000100000, // Ldeoral
5920    0x0000000000100000, // Ldeoralb
5921    0x0000000000100000, // Ldeoralh
5922    0x0000000000100000, // Ldeorb
5923    0x0000000000100000, // Ldeorh
5924    0x0000000000100000, // Ldeorl
5925    0x0000000000100000, // Ldeorlb
5926    0x0000000000100000, // Ldeorlh
5927    0x0000000000200000, // Ldg
5928    0x0000000000400000, // Ldgm
5929    0x0000000000080000, // Ldlar
5930    0x0000000000080000, // Ldlarb
5931    0x0000000000080000, // Ldlarh
5932    0x0000000000000000, // Ldnp
5933    0x0000000000000000, // Ldp
5934    0x0000000000000000, // Ldpsw
5935    0x0000000000000000, // Ldr
5936    0x0000000000800000, // Ldraa
5937    0x0000000000800000, // Ldrab
5938    0x0000000000000000, // Ldrb
5939    0x0000000000000000, // Ldrh
5940    0x0000000000000000, // Ldrsb
5941    0x0000000000000000, // Ldrsh
5942    0x0000000000000000, // Ldrsw
5943    0x0000000000100000, // Ldset
5944    0x0000000000100000, // Ldseta
5945    0x0000000000100000, // Ldsetab
5946    0x0000000000100000, // Ldsetah
5947    0x0000000000100000, // Ldsetal
5948    0x0000000000100000, // Ldsetalb
5949    0x0000000000100000, // Ldsetalh
5950    0x0000000000100000, // Ldsetb
5951    0x0000000000100000, // Ldseth
5952    0x0000000000100000, // Ldsetl
5953    0x0000000000100000, // Ldsetlb
5954    0x0000000000100000, // Ldsetlh
5955    0x0000000000100000, // Ldsmax
5956    0x0000000000100000, // Ldsmaxa
5957    0x0000000000100000, // Ldsmaxab
5958    0x0000000000100000, // Ldsmaxah
5959    0x0000000000100000, // Ldsmaxal
5960    0x0000000000100000, // Ldsmaxalb
5961    0x0000000000100000, // Ldsmaxalh
5962    0x0000000000100000, // Ldsmaxb
5963    0x0000000000100000, // Ldsmaxh
5964    0x0000000000100000, // Ldsmaxl
5965    0x0000000000100000, // Ldsmaxlb
5966    0x0000000000100000, // Ldsmaxlh
5967    0x0000000000100000, // Ldsmin
5968    0x0000000000100000, // Ldsmina
5969    0x0000000000100000, // Ldsminab
5970    0x0000000000100000, // Ldsminah
5971    0x0000000000100000, // Ldsminal
5972    0x0000000000100000, // Ldsminalb
5973    0x0000000000100000, // Ldsminalh
5974    0x0000000000100000, // Ldsminb
5975    0x0000000000100000, // Ldsminh
5976    0x0000000000100000, // Ldsminl
5977    0x0000000000100000, // Ldsminlb
5978    0x0000000000100000, // Ldsminlh
5979    0x0000000000000000, // Ldtr
5980    0x0000000000000000, // Ldtrb
5981    0x0000000000000000, // Ldtrh
5982    0x0000000000000000, // Ldtrsb
5983    0x0000000000000000, // Ldtrsh
5984    0x0000000000000000, // Ldtrsw
5985    0x0000000000100000, // Ldumax
5986    0x0000000000100000, // Ldumaxa
5987    0x0000000000100000, // Ldumaxab
5988    0x0000000000100000, // Ldumaxah
5989    0x0000000000100000, // Ldumaxal
5990    0x0000000000100000, // Ldumaxalb
5991    0x0000000000100000, // Ldumaxalh
5992    0x0000000000100000, // Ldumaxb
5993    0x0000000000100000, // Ldumaxh
5994    0x0000000000100000, // Ldumaxl
5995    0x0000000000100000, // Ldumaxlb
5996    0x0000000000100000, // Ldumaxlh
5997    0x0000000000100000, // Ldumin
5998    0x0000000000100000, // Ldumina
5999    0x0000000000100000, // Lduminab
6000    0x0000000000100000, // Lduminah
6001    0x0000000000100000, // Lduminal
6002    0x0000000000100000, // Lduminalb
6003    0x0000000000100000, // Lduminalh
6004    0x0000000000100000, // Lduminb
6005    0x0000000000100000, // Lduminh
6006    0x0000000000100000, // Lduminl
6007    0x0000000000100000, // Lduminlb
6008    0x0000000000100000, // Lduminlh
6009    0x0000000000000000, // Ldur
6010    0x0000000000000000, // Ldurb
6011    0x0000000000000000, // Ldurh
6012    0x0000000000000000, // Ldursb
6013    0x0000000000000000, // Ldursh
6014    0x0000000000000000, // Ldursw
6015    0x0000000000000000, // Ldxp
6016    0x0000000000000000, // Ldxr
6017    0x0000000000000000, // Ldxrb
6018    0x0000000000000000, // Ldxrh
6019    0x0000000000000000, // Lsl
6020    0x0000000000000000, // Lslv
6021    0x0000000000000000, // Lsr
6022    0x0000000000000000, // Lsrv
6023    0x0000000000000000, // Madd
6024    0x0000000000000000, // Mneg
6025    0x0000000000000000, // Mov
6026    0x0000000000000000, // Movk
6027    0x0000000000000000, // Movn
6028    0x0000000000000000, // Movz
6029    0x0000000000000000, // Mrs
6030    0x0000000000000000, // Msr
6031    0x0000000000000000, // Msub
6032    0x0000000000000000, // Mul
6033    0x0000000000000000, // Mvn
6034    0x0000000000000000, // Neg
6035    0x0000000000000000, // Negs
6036    0x0000000000000000, // Ngc
6037    0x0000000000000000, // Ngcs
6038    0x0000000000000000, // Nop
6039    0x0000000000000000, // Orn
6040    0x0000000000000000, // Orr
6041    0x0000000000800000, // Pacda
6042    0x0000000000800000, // Pacdb
6043    0x0000000000800000, // Pacdza
6044    0x0000000000800000, // Pacdzb
6045    0x0000000000800000, // Pacga
6046    0x0000000000000000, // Prfm
6047    0x0000000000000000, // Pssbb
6048    0x0000000000000000, // Rbit
6049    0x0000000000000000, // Ret
6050    0x0000000000000000, // Rev
6051    0x0000000000000000, // Rev16
6052    0x0000000000000000, // Rev32
6053    0x0000000000000000, // Rev64
6054    0x0000000000000000, // Ror
6055    0x0000000000000000, // Rorv
6056    0x0000000000000000, // Sbc
6057    0x0000000000000000, // Sbcs
6058    0x0000000000000000, // Sbfiz
6059    0x0000000000000000, // Sbfm
6060    0x0000000000000000, // Sbfx
6061    0x0000000000000000, // Sdiv
6062    0x0000000000001000, // Setf8
6063    0x0000000000001000, // Setf16
6064    0x0000000000000000, // Sev
6065    0x0000000000000000, // Sevl
6066    0x0000000000000000, // Smaddl
6067    0x0000000000000080, // Smax
6068    0x0000000000000000, // Smc
6069    0x0000000000000080, // Smin
6070    0x0000000000000000, // Smnegl
6071    0x0000000000000000, // Smsubl
6072    0x0000000000000000, // Smulh
6073    0x0000000000000000, // Smull
6074    0x0000000000000000, // Ssbb
6075    0x0000000000200000, // St2g
6076    0x0000000000100000, // Stadd
6077    0x0000000000100000, // Staddl
6078    0x0000000000100000, // Staddb
6079    0x0000000000100000, // Staddlb
6080    0x0000000000100000, // Staddh
6081    0x0000000000100000, // Staddlh
6082    0x0000000000100000, // Stclr
6083    0x0000000000100000, // Stclrl
6084    0x0000000000100000, // Stclrb
6085    0x0000000000100000, // Stclrlb
6086    0x0000000000100000, // Stclrh
6087    0x0000000000100000, // Stclrlh
6088    0x0000000000100000, // Steor
6089    0x0000000000100000, // Steorl
6090    0x0000000000100000, // Steorb
6091    0x0000000000100000, // Steorlb
6092    0x0000000000100000, // Steorh
6093    0x0000000000100000, // Steorlh
6094    0x0000000000200000, // Stg
6095    0x0000000000400000, // Stgm
6096    0x0000000000200000, // Stgp
6097    0x0000000000080000, // Stllr
6098    0x0000000000080000, // Stllrb
6099    0x0000000000080000, // Stllrh
6100    0x0000000000000000, // Stlr
6101    0x0000000000000000, // Stlrb
6102    0x0000000000000000, // Stlrh
6103    0x0000000000000000, // Stlxp
6104    0x0000000000000000, // Stlxr
6105    0x0000000000000000, // Stlxrb
6106    0x0000000000000000, // Stlxrh
6107    0x0000000000000000, // Stnp
6108    0x0000000000000000, // Stp
6109    0x0000000000000000, // Str
6110    0x0000000000000000, // Strb
6111    0x0000000000000000, // Strh
6112    0x0000000000100000, // Stset
6113    0x0000000000100000, // Stsetl
6114    0x0000000000100000, // Stsetb
6115    0x0000000000100000, // Stsetlb
6116    0x0000000000100000, // Stseth
6117    0x0000000000100000, // Stsetlh
6118    0x0000000000100000, // Stsmax
6119    0x0000000000100000, // Stsmaxl
6120    0x0000000000100000, // Stsmaxb
6121    0x0000000000100000, // Stsmaxlb
6122    0x0000000000100000, // Stsmaxh
6123    0x0000000000100000, // Stsmaxlh
6124    0x0000000000100000, // Stsmin
6125    0x0000000000100000, // Stsminl
6126    0x0000000000100000, // Stsminb
6127    0x0000000000100000, // Stsminlb
6128    0x0000000000100000, // Stsminh
6129    0x0000000000100000, // Stsminlh
6130    0x0000000000000000, // Sttr
6131    0x0000000000000000, // Sttrb
6132    0x0000000000000000, // Sttrh
6133    0x0000000000100000, // Stumax
6134    0x0000000000100000, // Stumaxl
6135    0x0000000000100000, // Stumaxb
6136    0x0000000000100000, // Stumaxlb
6137    0x0000000000100000, // Stumaxh
6138    0x0000000000100000, // Stumaxlh
6139    0x0000000000100000, // Stumin
6140    0x0000000000100000, // Stuminl
6141    0x0000000000100000, // Stuminb
6142    0x0000000000100000, // Stuminlb
6143    0x0000000000100000, // Stuminh
6144    0x0000000000100000, // Stuminlh
6145    0x0000000000000000, // Stur
6146    0x0000000000000000, // Sturb
6147    0x0000000000000000, // Sturh
6148    0x0000000000000000, // Stxp
6149    0x0000000000000000, // Stxr
6150    0x0000000000000000, // Stxrb
6151    0x0000000000000000, // Stxrh
6152    0x0000000000200000, // Stz2g
6153    0x0000000000200000, // Stzg
6154    0x0000000000400000, // Stzgm
6155    0x0000000000000000, // Sub
6156    0x0000000000200000, // Subg
6157    0x0000000000200000, // Subp
6158    0x0000000000200000, // Subps
6159    0x0000000000000000, // Subs
6160    0x0000000000000000, // Svc
6161    0x0000000000100000, // Swp
6162    0x0000000000100000, // Swpa
6163    0x0000000000100000, // Swpab
6164    0x0000000000100000, // Swpah
6165    0x0000000000100000, // Swpal
6166    0x0000000000100000, // Swpalb
6167    0x0000000000100000, // Swpalh
6168    0x0000000000100000, // Swpb
6169    0x0000000000100000, // Swph
6170    0x0000000000100000, // Swpl
6171    0x0000000000100000, // Swplb
6172    0x0000000000100000, // Swplh
6173    0x0000000000000000, // Sxtb
6174    0x0000000000000000, // Sxth
6175    0x0000000000000000, // Sxtw
6176    0x0000000000000000, // Sys
6177    0x0000000000000000, // Tlbi
6178    0x0000000000000000, // Tst
6179    0x0000000000000000, // Tbnz
6180    0x0000000000000000, // Tbz
6181    0x0000000000000000, // Ubfiz
6182    0x0000000000000000, // Ubfm
6183    0x0000000000000000, // Ubfx
6184    0x0000000000000000, // Udf
6185    0x0000000000000000, // Udiv
6186    0x0000000000000000, // Umaddl
6187    0x0000000000000080, // Umax
6188    0x0000000000000080, // Umin
6189    0x0000000000000000, // Umnegl
6190    0x0000000000000000, // Umull
6191    0x0000000000000000, // Umulh
6192    0x0000000000000000, // Umsubl
6193    0x0000000000000000, // Uxtb
6194    0x0000000000000000, // Uxth
6195    0x0000000000000000, // Wfe
6196    0x0000000000000000, // Wfi
6197    0x0000000000002000, // Xaflag
6198    0x0000000000800000, // Xpacd
6199    0x0000000000800000, // Xpaci
6200    0x0000000000800000, // Xpaclri
6201    0x0000000000000000, // Yield
6202    0x0000000000000002, // Abs_v
6203    0x0000000000000002, // Add_v
6204    0x0000000000000002, // Addhn_v
6205    0x0000000000000002, // Addhn2_v
6206    0x0000000000000002, // Addp_v
6207    0x0000000000000002, // Addv_v
6208    0x0000000000000003, // Aesd_v
6209    0x0000000000000003, // Aese_v
6210    0x0000000000000003, // Aesimc_v
6211    0x0000000000000003, // Aesmc_v
6212    0x0000000000000002, // And_v
6213    0x0000000010000002, // Bcax_v
6214    0x0000000000000006, // Bfcvt_v
6215    0x0000000000000006, // Bfcvtn_v
6216    0x0000000000000006, // Bfcvtn2_v
6217    0x0000000000000006, // Bfdot_v
6218    0x0000000000000006, // Bfmlalb_v
6219    0x0000000000000006, // Bfmlalt_v
6220    0x0000000000000006, // Bfmmla_v
6221    0x0000000000000002, // Bic_v
6222    0x0000000000000002, // Bif_v
6223    0x0000000000000002, // Bit_v
6224    0x0000000000000002, // Bsl_v
6225    0x0000000000000002, // Cls_v
6226    0x0000000000000002, // Clz_v
6227    0x0000000000000002, // Cmeq_v
6228    0x0000000000000002, // Cmge_v
6229    0x0000000000000002, // Cmgt_v
6230    0x0000000000000002, // Cmhi_v
6231    0x0000000000000002, // Cmhs_v
6232    0x0000000000000002, // Cmle_v
6233    0x0000000000000002, // Cmlt_v
6234    0x0000000000000002, // Cmtst_v
6235    0x0000000000000002, // Cnt_v
6236    0x0000000000000002, // Dup_v
6237    0x0000000000000002, // Eor_v
6238    0x0000000010000002, // Eor3_v
6239    0x0000000000000002, // Ext_v
6240    0x0000000000000002, // Fabd_v
6241    0x0000000000000002, // Fabs_v
6242    0x0000000000000002, // Facge_v
6243    0x0000000000000002, // Facgt_v
6244    0x0000000000000002, // Fadd_v
6245    0x0000000000000002, // Faddp_v
6246    0x0000000000000402, // Fcadd_v
6247    0x0000000000000002, // Fccmp_v
6248    0x0000000000000002, // Fccmpe_v
6249    0x0000000000000002, // Fcmeq_v
6250    0x0000000000000002, // Fcmge_v
6251    0x0000000000000002, // Fcmgt_v
6252    0x0000000000000402, // Fcmla_v
6253    0x0000000000000002, // Fcmle_v
6254    0x0000000000000002, // Fcmlt_v
6255    0x0000000000000002, // Fcmp_v
6256    0x0000000000000002, // Fcmpe_v
6257    0x0000000000000002, // Fcsel_v
6258    0x0000000000000002, // Fcvt_v
6259    0x0000000000000002, // Fcvtas_v
6260    0x0000000000000002, // Fcvtau_v
6261    0x0000000000000002, // Fcvtl_v
6262    0x0000000000000002, // Fcvtl2_v
6263    0x0000000000000002, // Fcvtms_v
6264    0x0000000000000002, // Fcvtmu_v
6265    0x0000000000000002, // Fcvtn_v
6266    0x0000000000000002, // Fcvtn2_v
6267    0x0000000000000002, // Fcvtns_v
6268    0x0000000000000002, // Fcvtnu_v
6269    0x0000000000000002, // Fcvtps_v
6270    0x0000000000000002, // Fcvtpu_v
6271    0x0000000000000000, // Fcvtxn_v
6272    0x0000000000000000, // Fcvtxn2_v
6273    0x0000000000000002, // Fcvtzs_v
6274    0x0000000000000002, // Fcvtzu_v
6275    0x0000000000000002, // Fdiv_v
6276    0x0000000000040002, // Fjcvtzs_v
6277    0x0000000000000002, // Fmadd_v
6278    0x0000000000000002, // Fmax_v
6279    0x0000000000000002, // Fmaxnm_v
6280    0x0000000000000002, // Fmaxnmp_v
6281    0x0000000000000002, // Fmaxnmv_v
6282    0x0000000000000002, // Fmaxp_v
6283    0x0000000000000002, // Fmaxv_v
6284    0x0000000000000002, // Fmin_v
6285    0x0000000000000002, // Fminnm_v
6286    0x0000000000000002, // Fminnmp_v
6287    0x0000000000000002, // Fminnmv_v
6288    0x0000000000000002, // Fminp_v
6289    0x0000000000000002, // Fminv_v
6290    0x0000000000000002, // Fmla_v
6291    0x0000000000000802, // Fmlal_v
6292    0x0000000000000802, // Fmlal2_v
6293    0x0000000000000002, // Fmls_v
6294    0x0000000000000802, // Fmlsl_v
6295    0x0000000000000802, // Fmlsl2_v
6296    0x0000000000000002, // Fmov_v
6297    0x0000000000000002, // Fmsub_v
6298    0x0000000000000002, // Fmul_v
6299    0x0000000000000002, // Fmulx_v
6300    0x0000000000000002, // Fneg_v
6301    0x0000000000000002, // Fnmadd_v
6302    0x0000000000000002, // Fnmsub_v
6303    0x0000000000000002, // Fnmul_v
6304    0x0000000000000002, // Frecpe_v
6305    0x0000000000000002, // Frecps_v
6306    0x0000000000000002, // Frecpx_v
6307    0x0000000000010002, // Frint32x_v
6308    0x0000000000010002, // Frint32z_v
6309    0x0000000000010002, // Frint64x_v
6310    0x0000000000010002, // Frint64z_v
6311    0x0000000000000002, // Frinta_v
6312    0x0000000000000002, // Frinti_v
6313    0x0000000000000002, // Frintm_v
6314    0x0000000000000002, // Frintn_v
6315    0x0000000000000002, // Frintp_v
6316    0x0000000000000002, // Frintx_v
6317    0x0000000000000002, // Frintz_v
6318    0x0000000000000002, // Frsqrte_v
6319    0x0000000000000002, // Frsqrts_v
6320    0x0000000000000002, // Fsqrt_v
6321    0x0000000000000002, // Fsub_v
6322    0x0000000000000002, // Ins_v
6323    0x0000000000000002, // Ld1_v
6324    0x0000000000000002, // Ld1r_v
6325    0x0000000000000002, // Ld2_v
6326    0x0000000000000002, // Ld2r_v
6327    0x0000000000000002, // Ld3_v
6328    0x0000000000000002, // Ld3r_v
6329    0x0000000000000002, // Ld4_v
6330    0x0000000000000002, // Ld4r_v
6331    0x0000000000000002, // Ldnp_v
6332    0x0000000000000002, // Ldp_v
6333    0x0000000000000002, // Ldr_v
6334    0x0000000000000002, // Ldur_v
6335    0x0000000000000002, // Mla_v
6336    0x0000000000000002, // Mls_v
6337    0x0000000000000002, // Mov_v
6338    0x0000000000000002, // Movi_v
6339    0x0000000000000002, // Mul_v
6340    0x0000000000000002, // Mvn_v
6341    0x0000000000000002, // Mvni_v
6342    0x0000000000000002, // Neg_v
6343    0x0000000000000002, // Not_v
6344    0x0000000000000002, // Orn_v
6345    0x0000000000000002, // Orr_v
6346    0x0000000000000002, // Pmul_v
6347    0x0000000000000002, // Pmull_v
6348    0x0000000000000002, // Pmull2_v
6349    0x0000000000000002, // Raddhn_v
6350    0x0000000000000002, // Raddhn2_v
6351    0x0000000010000002, // Rax1_v
6352    0x0000000000000002, // Rbit_v
6353    0x0000000000000002, // Rev16_v
6354    0x0000000000000002, // Rev32_v
6355    0x0000000000000002, // Rev64_v
6356    0x0000000000000002, // Rshrn_v
6357    0x0000000000000002, // Rshrn2_v
6358    0x0000000000000002, // Rsubhn_v
6359    0x0000000000000002, // Rsubhn2_v
6360    0x0000000000000002, // Saba_v
6361    0x0000000000000002, // Sabal_v
6362    0x0000000000000002, // Sabal2_v
6363    0x0000000000000002, // Sabd_v
6364    0x0000000000000002, // Sabdl_v
6365    0x0000000000000002, // Sabdl2_v
6366    0x0000000000000002, // Sadalp_v
6367    0x0000000000000002, // Saddl_v
6368    0x0000000000000002, // Saddl2_v
6369    0x0000000000000002, // Saddlp_v
6370    0x0000000000000002, // Saddlv_v
6371    0x0000000000000002, // Saddw_v
6372    0x0000000000000002, // Saddw2_v
6373    0x0000000000000002, // Scvtf_v
6374    0x0000000000000202, // Sdot_v
6375    0x0000000004000002, // Sha1c_v
6376    0x0000000004000002, // Sha1h_v
6377    0x0000000004000002, // Sha1m_v
6378    0x0000000004000002, // Sha1p_v
6379    0x0000000004000002, // Sha1su0_v
6380    0x0000000004000002, // Sha1su1_v
6381    0x0000000008000002, // Sha256h_v
6382    0x0000000008000002, // Sha256h2_v
6383    0x0000000008000002, // Sha256su0_v
6384    0x0000000008000002, // Sha256su1_v
6385    0x0000000020000002, // Sha512h_v
6386    0x0000000020000002, // Sha512h2_v
6387    0x0000000020000002, // Sha512su0_v
6388    0x0000000020000002, // Sha512su1_v
6389    0x0000000000000002, // Shadd_v
6390    0x0000000000000002, // Shl_v
6391    0x0000000000000002, // Shll_v
6392    0x0000000000000002, // Shll2_v
6393    0x0000000000000002, // Shrn_v
6394    0x0000000000000002, // Shrn2_v
6395    0x0000000000000002, // Shsub_v
6396    0x0000000000000002, // Sli_v
6397    0x0000000040000002, // Sm3partw1_v
6398    0x0000000040000002, // Sm3partw2_v
6399    0x0000000040000002, // Sm3ss1_v
6400    0x0000000040000002, // Sm3tt1a_v
6401    0x0000000040000002, // Sm3tt1b_v
6402    0x0000000040000002, // Sm3tt2a_v
6403    0x0000000040000002, // Sm3tt2b_v
6404    0x0000000080000002, // Sm4e_v
6405    0x0000000080000002, // Sm4ekey_v
6406    0x0000000000000002, // Smax_v
6407    0x0000000000000002, // Smaxp_v
6408    0x0000000000000002, // Smaxv_v
6409    0x0000000000000002, // Smin_v
6410    0x0000000000000002, // Sminp_v
6411    0x0000000000000002, // Sminv_v
6412    0x0000000000000002, // Smlal_v
6413    0x0000000000000002, // Smlal2_v
6414    0x0000000000000002, // Smlsl_v
6415    0x0000000000000002, // Smlsl2_v
6416    0x0000000000020002, // Smmla_v
6417    0x0000000000000002, // Smov_v
6418    0x0000000000000002, // Smull_v
6419    0x0000000000000002, // Smull2_v
6420    0x0000000000000002, // Sqabs_v
6421    0x0000000000000002, // Sqadd_v
6422    0x0000000000000002, // Sqdmlal_v
6423    0x0000000000000002, // Sqdmlal2_v
6424    0x0000000000000002, // Sqdmlsl_v
6425    0x0000000000000002, // Sqdmlsl2_v
6426    0x0000000000000002, // Sqdmulh_v
6427    0x0000000000000002, // Sqdmull_v
6428    0x0000000000000002, // Sqdmull2_v
6429    0x0000000000000002, // Sqneg_v
6430    0x0000000002000002, // Sqrdmlah_v
6431    0x0000000002000002, // Sqrdmlsh_v
6432    0x0000000000000002, // Sqrdmulh_v
6433    0x0000000000000002, // Sqrshl_v
6434    0x0000000000000002, // Sqrshrn_v
6435    0x0000000000000002, // Sqrshrn2_v
6436    0x0000000000000002, // Sqrshrun_v
6437    0x0000000000000002, // Sqrshrun2_v
6438    0x0000000000000002, // Sqshl_v
6439    0x0000000000000002, // Sqshlu_v
6440    0x0000000000000002, // Sqshrn_v
6441    0x0000000000000002, // Sqshrn2_v
6442    0x0000000000000002, // Sqshrun_v
6443    0x0000000000000002, // Sqshrun2_v
6444    0x0000000000000002, // Sqsub_v
6445    0x0000000000000002, // Sqxtn_v
6446    0x0000000000000002, // Sqxtn2_v
6447    0x0000000000000002, // Sqxtun_v
6448    0x0000000000000002, // Sqxtun2_v
6449    0x0000000000000002, // Srhadd_v
6450    0x0000000000000002, // Sri_v
6451    0x0000000000000002, // Srshl_v
6452    0x0000000000000002, // Srshr_v
6453    0x0000000000000002, // Srsra_v
6454    0x0000000000000002, // Sshl_v
6455    0x0000000000000002, // Sshll_v
6456    0x0000000000000002, // Sshll2_v
6457    0x0000000000000002, // Sshr_v
6458    0x0000000000000002, // Ssra_v
6459    0x0000000000000002, // Ssubl_v
6460    0x0000000000000002, // Ssubl2_v
6461    0x0000000000000002, // Ssubw_v
6462    0x0000000000000002, // Ssubw2_v
6463    0x0000000000000002, // St1_v
6464    0x0000000000000002, // St2_v
6465    0x0000000000000002, // St3_v
6466    0x0000000000000002, // St4_v
6467    0x0000000000000002, // Stnp_v
6468    0x0000000000000002, // Stp_v
6469    0x0000000000000002, // Str_v
6470    0x0000000000000002, // Stur_v
6471    0x0000000000000002, // Sub_v
6472    0x0000000000000002, // Subhn_v
6473    0x0000000000000002, // Subhn2_v
6474    0x0000000000020002, // Sudot_v
6475    0x0000000000000002, // Suqadd_v
6476    0x0000000000000002, // Sxtl_v
6477    0x0000000000000002, // Sxtl2_v
6478    0x0000000000000002, // Tbl_v
6479    0x0000000000000002, // Tbx_v
6480    0x0000000000000002, // Trn1_v
6481    0x0000000000000002, // Trn2_v
6482    0x0000000000000002, // Uaba_v
6483    0x0000000000000002, // Uabal_v
6484    0x0000000000000002, // Uabal2_v
6485    0x0000000000000002, // Uabd_v
6486    0x0000000000000002, // Uabdl_v
6487    0x0000000000000002, // Uabdl2_v
6488    0x0000000000000002, // Uadalp_v
6489    0x0000000000000002, // Uaddl_v
6490    0x0000000000000002, // Uaddl2_v
6491    0x0000000000000002, // Uaddlp_v
6492    0x0000000000000002, // Uaddlv_v
6493    0x0000000000000002, // Uaddw_v
6494    0x0000000000000002, // Uaddw2_v
6495    0x0000000000000002, // Ucvtf_v
6496    0x0000000000000202, // Udot_v
6497    0x0000000000000002, // Uhadd_v
6498    0x0000000000000002, // Uhsub_v
6499    0x0000000000000002, // Umax_v
6500    0x0000000000000002, // Umaxp_v
6501    0x0000000000000002, // Umaxv_v
6502    0x0000000000000002, // Umin_v
6503    0x0000000000000002, // Uminp_v
6504    0x0000000000000002, // Uminv_v
6505    0x0000000000000002, // Umlal_v
6506    0x0000000000000002, // Umlal2_v
6507    0x0000000000000002, // Umlsl_v
6508    0x0000000000000002, // Umlsl2_v
6509    0x0000000000020002, // Ummla_v
6510    0x0000000000000002, // Umov_v
6511    0x0000000000000002, // Umull_v
6512    0x0000000000000002, // Umull2_v
6513    0x0000000000000002, // Uqadd_v
6514    0x0000000000000002, // Uqrshl_v
6515    0x0000000000000002, // Uqrshrn_v
6516    0x0000000000000002, // Uqrshrn2_v
6517    0x0000000000000002, // Uqshl_v
6518    0x0000000000000002, // Uqshrn_v
6519    0x0000000000000002, // Uqshrn2_v
6520    0x0000000000000002, // Uqsub_v
6521    0x0000000000000002, // Uqxtn_v
6522    0x0000000000000002, // Uqxtn2_v
6523    0x0000000000000002, // Urecpe_v
6524    0x0000000000000002, // Urhadd_v
6525    0x0000000000000002, // Urshl_v
6526    0x0000000000000002, // Urshr_v
6527    0x0000000000000002, // Ursqrte_v
6528    0x0000000000000002, // Ursra_v
6529    0x0000000000020002, // Usdot_v
6530    0x0000000000000002, // Ushl_v
6531    0x0000000000000002, // Ushll_v
6532    0x0000000000000002, // Ushll2_v
6533    0x0000000000000002, // Ushr_v
6534    0x0000000000020002, // Usmmla_v
6535    0x0000000000000002, // Usqadd_v
6536    0x0000000000000002, // Usra_v
6537    0x0000000000000002, // Usubl_v
6538    0x0000000000000002, // Usubl2_v
6539    0x0000000000000002, // Usubw_v
6540    0x0000000000000002, // Usubw2_v
6541    0x0000000000000002, // Uxtl_v
6542    0x0000000000000002, // Uxtl2_v
6543    0x0000000000000002, // Uzp1_v
6544    0x0000000000000002, // Uzp2_v
6545    0x0000000010000002, // Xar_v
6546    0x0000000000000002, // Xtn_v
6547    0x0000000000000002, // Xtn2_v
6548    0x0000000000000002, // Zip1_v
6549    0x0000000000000002, // Zip2_v
6550];
6551
6552static INST_BASE_FEATURE_CONTEXT: [&str; InstId::_Count as usize] = [
6553    "",
6554    "abs requires: CSSC",
6555    "",
6556    "",
6557    "",
6558    "addg requires: MTE",
6559    "",
6560    "",
6561    "",
6562    "",
6563    "",
6564    "",
6565    "",
6566    "",
6567    "autda requires: PAUTH",
6568    "autdza requires: PAUTH",
6569    "autdb requires: PAUTH",
6570    "autdzb requires: PAUTH",
6571    "autia requires: PAUTH",
6572    "autia1716 requires: PAUTH",
6573    "autiasp requires: PAUTH",
6574    "autiaz requires: PAUTH",
6575    "autib requires: PAUTH",
6576    "autib1716 requires: PAUTH",
6577    "autibsp requires: PAUTH",
6578    "autibz requires: PAUTH",
6579    "autiza requires: PAUTH",
6580    "autizb requires: PAUTH",
6581    "axflag requires: FLAGM2",
6582    "",
6583    "",
6584    "",
6585    "",
6586    "",
6587    "",
6588    "",
6589    "",
6590    "",
6591    "",
6592    "",
6593    "",
6594    "bti requires: BTI",
6595    "cas requires: LSE",
6596    "casa requires: LSE",
6597    "casab requires: LSE",
6598    "casah requires: LSE",
6599    "casal requires: LSE",
6600    "casalb requires: LSE",
6601    "casalh requires: LSE",
6602    "casb requires: LSE",
6603    "cash requires: LSE",
6604    "casl requires: LSE",
6605    "caslb requires: LSE",
6606    "caslh requires: LSE",
6607    "casp requires: LSE",
6608    "caspa requires: LSE",
6609    "caspal requires: LSE",
6610    "caspl requires: LSE",
6611    "",
6612    "",
6613    "",
6614    "",
6615    "cfinv requires: FLAGM",
6616    "chkfeat requires: CHK",
6617    "",
6618    "",
6619    "clrbhb requires: CLRBHB",
6620    "",
6621    "",
6622    "",
6623    "",
6624    "",
6625    "cmpp requires: MTE",
6626    "",
6627    "cnt requires: CSSC",
6628    "crc32b requires: CRC32",
6629    "crc32cb requires: CRC32",
6630    "crc32ch requires: CRC32",
6631    "crc32cw requires: CRC32",
6632    "crc32cx requires: CRC32",
6633    "crc32h requires: CRC32",
6634    "crc32w requires: CRC32",
6635    "crc32x requires: CRC32",
6636    "",
6637    "",
6638    "",
6639    "",
6640    "",
6641    "",
6642    "",
6643    "ctz requires: CSSC",
6644    "",
6645    "",
6646    "",
6647    "",
6648    "dgh requires: DGH",
6649    "",
6650    "",
6651    "",
6652    "",
6653    "",
6654    "esb requires: RAS",
6655    "",
6656    "",
6657    "gmi requires: MTE",
6658    "",
6659    "",
6660    "",
6661    "",
6662    "",
6663    "ldadd requires: LSE",
6664    "ldadda requires: LSE",
6665    "ldaddab requires: LSE",
6666    "ldaddah requires: LSE",
6667    "ldaddal requires: LSE",
6668    "ldaddalb requires: LSE",
6669    "ldaddalh requires: LSE",
6670    "ldaddb requires: LSE",
6671    "ldaddh requires: LSE",
6672    "ldaddl requires: LSE",
6673    "ldaddlb requires: LSE",
6674    "ldaddlh requires: LSE",
6675    "",
6676    "",
6677    "",
6678    "",
6679    "",
6680    "",
6681    "",
6682    "ldclr requires: LSE",
6683    "ldclra requires: LSE",
6684    "ldclrab requires: LSE",
6685    "ldclrah requires: LSE",
6686    "ldclral requires: LSE",
6687    "ldclralb requires: LSE",
6688    "ldclralh requires: LSE",
6689    "ldclrb requires: LSE",
6690    "ldclrh requires: LSE",
6691    "ldclrl requires: LSE",
6692    "ldclrlb requires: LSE",
6693    "ldclrlh requires: LSE",
6694    "ldeor requires: LSE",
6695    "ldeora requires: LSE",
6696    "ldeorab requires: LSE",
6697    "ldeorah requires: LSE",
6698    "ldeoral requires: LSE",
6699    "ldeoralb requires: LSE",
6700    "ldeoralh requires: LSE",
6701    "ldeorb requires: LSE",
6702    "ldeorh requires: LSE",
6703    "ldeorl requires: LSE",
6704    "ldeorlb requires: LSE",
6705    "ldeorlh requires: LSE",
6706    "ldg requires: MTE",
6707    "ldgm requires: MTE2",
6708    "ldlar requires: LOR",
6709    "ldlarb requires: LOR",
6710    "ldlarh requires: LOR",
6711    "",
6712    "",
6713    "",
6714    "",
6715    "ldraa requires: PAUTH",
6716    "ldrab requires: PAUTH",
6717    "",
6718    "",
6719    "",
6720    "",
6721    "",
6722    "ldset requires: LSE",
6723    "ldseta requires: LSE",
6724    "ldsetab requires: LSE",
6725    "ldsetah requires: LSE",
6726    "ldsetal requires: LSE",
6727    "ldsetalb requires: LSE",
6728    "ldsetalh requires: LSE",
6729    "ldsetb requires: LSE",
6730    "ldseth requires: LSE",
6731    "ldsetl requires: LSE",
6732    "ldsetlb requires: LSE",
6733    "ldsetlh requires: LSE",
6734    "ldsmax requires: LSE",
6735    "ldsmaxa requires: LSE",
6736    "ldsmaxab requires: LSE",
6737    "ldsmaxah requires: LSE",
6738    "ldsmaxal requires: LSE",
6739    "ldsmaxalb requires: LSE",
6740    "ldsmaxalh requires: LSE",
6741    "ldsmaxb requires: LSE",
6742    "ldsmaxh requires: LSE",
6743    "ldsmaxl requires: LSE",
6744    "ldsmaxlb requires: LSE",
6745    "ldsmaxlh requires: LSE",
6746    "ldsmin requires: LSE",
6747    "ldsmina requires: LSE",
6748    "ldsminab requires: LSE",
6749    "ldsminah requires: LSE",
6750    "ldsminal requires: LSE",
6751    "ldsminalb requires: LSE",
6752    "ldsminalh requires: LSE",
6753    "ldsminb requires: LSE",
6754    "ldsminh requires: LSE",
6755    "ldsminl requires: LSE",
6756    "ldsminlb requires: LSE",
6757    "ldsminlh requires: LSE",
6758    "",
6759    "",
6760    "",
6761    "",
6762    "",
6763    "",
6764    "ldumax requires: LSE",
6765    "ldumaxa requires: LSE",
6766    "ldumaxab requires: LSE",
6767    "ldumaxah requires: LSE",
6768    "ldumaxal requires: LSE",
6769    "ldumaxalb requires: LSE",
6770    "ldumaxalh requires: LSE",
6771    "ldumaxb requires: LSE",
6772    "ldumaxh requires: LSE",
6773    "ldumaxl requires: LSE",
6774    "ldumaxlb requires: LSE",
6775    "ldumaxlh requires: LSE",
6776    "ldumin requires: LSE",
6777    "ldumina requires: LSE",
6778    "lduminab requires: LSE",
6779    "lduminah requires: LSE",
6780    "lduminal requires: LSE",
6781    "lduminalb requires: LSE",
6782    "lduminalh requires: LSE",
6783    "lduminb requires: LSE",
6784    "lduminh requires: LSE",
6785    "lduminl requires: LSE",
6786    "lduminlb requires: LSE",
6787    "lduminlh requires: LSE",
6788    "",
6789    "",
6790    "",
6791    "",
6792    "",
6793    "",
6794    "",
6795    "",
6796    "",
6797    "",
6798    "",
6799    "",
6800    "",
6801    "",
6802    "",
6803    "",
6804    "",
6805    "",
6806    "",
6807    "",
6808    "",
6809    "",
6810    "",
6811    "",
6812    "",
6813    "",
6814    "",
6815    "",
6816    "",
6817    "",
6818    "",
6819    "",
6820    "pacda requires: PAUTH",
6821    "pacdb requires: PAUTH",
6822    "pacdza requires: PAUTH",
6823    "pacdzb requires: PAUTH",
6824    "pacga requires: PAUTH",
6825    "",
6826    "",
6827    "",
6828    "",
6829    "",
6830    "",
6831    "",
6832    "",
6833    "",
6834    "",
6835    "",
6836    "",
6837    "",
6838    "",
6839    "",
6840    "",
6841    "setf8 requires: FLAGM",
6842    "setf16 requires: FLAGM",
6843    "",
6844    "",
6845    "",
6846    "smax requires: CSSC",
6847    "",
6848    "smin requires: CSSC",
6849    "",
6850    "",
6851    "",
6852    "",
6853    "",
6854    "st2g requires: MTE",
6855    "stadd requires: LSE",
6856    "staddl requires: LSE",
6857    "staddb requires: LSE",
6858    "staddlb requires: LSE",
6859    "staddh requires: LSE",
6860    "staddlh requires: LSE",
6861    "stclr requires: LSE",
6862    "stclrl requires: LSE",
6863    "stclrb requires: LSE",
6864    "stclrlb requires: LSE",
6865    "stclrh requires: LSE",
6866    "stclrlh requires: LSE",
6867    "steor requires: LSE",
6868    "steorl requires: LSE",
6869    "steorb requires: LSE",
6870    "steorlb requires: LSE",
6871    "steorh requires: LSE",
6872    "steorlh requires: LSE",
6873    "stg requires: MTE",
6874    "stgm requires: MTE2",
6875    "stgp requires: MTE",
6876    "stllr requires: LOR",
6877    "stllrb requires: LOR",
6878    "stllrh requires: LOR",
6879    "",
6880    "",
6881    "",
6882    "",
6883    "",
6884    "",
6885    "",
6886    "",
6887    "",
6888    "",
6889    "",
6890    "",
6891    "stset requires: LSE",
6892    "stsetl requires: LSE",
6893    "stsetb requires: LSE",
6894    "stsetlb requires: LSE",
6895    "stseth requires: LSE",
6896    "stsetlh requires: LSE",
6897    "stsmax requires: LSE",
6898    "stsmaxl requires: LSE",
6899    "stsmaxb requires: LSE",
6900    "stsmaxlb requires: LSE",
6901    "stsmaxh requires: LSE",
6902    "stsmaxlh requires: LSE",
6903    "stsmin requires: LSE",
6904    "stsminl requires: LSE",
6905    "stsminb requires: LSE",
6906    "stsminlb requires: LSE",
6907    "stsminh requires: LSE",
6908    "stsminlh requires: LSE",
6909    "",
6910    "",
6911    "",
6912    "stumax requires: LSE",
6913    "stumaxl requires: LSE",
6914    "stumaxb requires: LSE",
6915    "stumaxlb requires: LSE",
6916    "stumaxh requires: LSE",
6917    "stumaxlh requires: LSE",
6918    "stumin requires: LSE",
6919    "stuminl requires: LSE",
6920    "stuminb requires: LSE",
6921    "stuminlb requires: LSE",
6922    "stuminh requires: LSE",
6923    "stuminlh requires: LSE",
6924    "",
6925    "",
6926    "",
6927    "",
6928    "",
6929    "",
6930    "",
6931    "stz2g requires: MTE",
6932    "stzg requires: MTE",
6933    "stzgm requires: MTE2",
6934    "",
6935    "subg requires: MTE",
6936    "subp requires: MTE",
6937    "subps requires: MTE",
6938    "",
6939    "",
6940    "swp requires: LSE",
6941    "swpa requires: LSE",
6942    "swpab requires: LSE",
6943    "swpah requires: LSE",
6944    "swpal requires: LSE",
6945    "swpalb requires: LSE",
6946    "swpalh requires: LSE",
6947    "swpb requires: LSE",
6948    "swph requires: LSE",
6949    "swpl requires: LSE",
6950    "swplb requires: LSE",
6951    "swplh requires: LSE",
6952    "",
6953    "",
6954    "",
6955    "",
6956    "",
6957    "",
6958    "",
6959    "",
6960    "",
6961    "",
6962    "",
6963    "",
6964    "",
6965    "",
6966    "umax requires: CSSC",
6967    "umin requires: CSSC",
6968    "",
6969    "",
6970    "",
6971    "",
6972    "",
6973    "",
6974    "",
6975    "",
6976    "xaflag requires: FLAGM2",
6977    "xpacd requires: PAUTH",
6978    "xpaci requires: PAUTH",
6979    "xpaclri requires: PAUTH",
6980    "",
6981    "abs requires: ASIMD",
6982    "add requires: ASIMD",
6983    "addhn requires: ASIMD",
6984    "addhn2 requires: ASIMD",
6985    "addp requires: ASIMD",
6986    "addv requires: ASIMD",
6987    "aesd requires: AES, ASIMD",
6988    "aese requires: AES, ASIMD",
6989    "aesimc requires: AES, ASIMD",
6990    "aesmc requires: AES, ASIMD",
6991    "and requires: ASIMD",
6992    "bcax requires: ASIMD, SHA3",
6993    "bfcvt requires: ASIMD, BF16",
6994    "bfcvtn requires: ASIMD, BF16",
6995    "bfcvtn2 requires: ASIMD, BF16",
6996    "bfdot requires: ASIMD, BF16",
6997    "bfmlalb requires: ASIMD, BF16",
6998    "bfmlalt requires: ASIMD, BF16",
6999    "bfmmla requires: ASIMD, BF16",
7000    "bic requires: ASIMD",
7001    "bif requires: ASIMD",
7002    "bit requires: ASIMD",
7003    "bsl requires: ASIMD",
7004    "cls requires: ASIMD",
7005    "clz requires: ASIMD",
7006    "cmeq requires: ASIMD",
7007    "cmge requires: ASIMD",
7008    "cmgt requires: ASIMD",
7009    "cmhi requires: ASIMD",
7010    "cmhs requires: ASIMD",
7011    "cmle requires: ASIMD",
7012    "cmlt requires: ASIMD",
7013    "cmtst requires: ASIMD",
7014    "cnt requires: ASIMD",
7015    "dup requires: ASIMD",
7016    "eor requires: ASIMD",
7017    "eor3 requires: ASIMD, SHA3",
7018    "ext requires: ASIMD",
7019    "fabd requires: ASIMD",
7020    "fabs requires: ASIMD",
7021    "facge requires: ASIMD",
7022    "facgt requires: ASIMD",
7023    "fadd requires: ASIMD",
7024    "faddp requires: ASIMD",
7025    "fcadd requires: ASIMD, FCMA",
7026    "fccmp requires: ASIMD",
7027    "fccmpe requires: ASIMD",
7028    "fcmeq requires: ASIMD",
7029    "fcmge requires: ASIMD",
7030    "fcmgt requires: ASIMD",
7031    "fcmla requires: ASIMD, FCMA",
7032    "fcmle requires: ASIMD",
7033    "fcmlt requires: ASIMD",
7034    "fcmp requires: ASIMD",
7035    "fcmpe requires: ASIMD",
7036    "fcsel requires: ASIMD",
7037    "fcvt requires: ASIMD",
7038    "fcvtas requires: ASIMD",
7039    "fcvtau requires: ASIMD",
7040    "fcvtl requires: ASIMD",
7041    "fcvtl2 requires: ASIMD",
7042    "fcvtms requires: ASIMD",
7043    "fcvtmu requires: ASIMD",
7044    "fcvtn requires: ASIMD",
7045    "fcvtn2 requires: ASIMD",
7046    "fcvtns requires: ASIMD",
7047    "fcvtnu requires: ASIMD",
7048    "fcvtps requires: ASIMD",
7049    "fcvtpu requires: ASIMD",
7050    "",
7051    "",
7052    "fcvtzs requires: ASIMD",
7053    "fcvtzu requires: ASIMD",
7054    "fdiv requires: ASIMD",
7055    "fjcvtzs requires: ASIMD, JSCVT",
7056    "fmadd requires: ASIMD",
7057    "fmax requires: ASIMD",
7058    "fmaxnm requires: ASIMD",
7059    "fmaxnmp requires: ASIMD",
7060    "fmaxnmv requires: ASIMD",
7061    "fmaxp requires: ASIMD",
7062    "fmaxv requires: ASIMD",
7063    "fmin requires: ASIMD",
7064    "fminnm requires: ASIMD",
7065    "fminnmp requires: ASIMD",
7066    "fminnmv requires: ASIMD",
7067    "fminp requires: ASIMD",
7068    "fminv requires: ASIMD",
7069    "fmla requires: ASIMD",
7070    "fmlal requires: ASIMD, FHM",
7071    "fmlal2 requires: ASIMD, FHM",
7072    "fmls requires: ASIMD",
7073    "fmlsl requires: ASIMD, FHM",
7074    "fmlsl2 requires: ASIMD, FHM",
7075    "fmov requires: ASIMD",
7076    "fmsub requires: ASIMD",
7077    "fmul requires: ASIMD",
7078    "fmulx requires: ASIMD",
7079    "fneg requires: ASIMD",
7080    "fnmadd requires: ASIMD",
7081    "fnmsub requires: ASIMD",
7082    "fnmul requires: ASIMD",
7083    "frecpe requires: ASIMD",
7084    "frecps requires: ASIMD",
7085    "frecpx requires: ASIMD",
7086    "frint32x requires: ASIMD, FRINTTS",
7087    "frint32z requires: ASIMD, FRINTTS",
7088    "frint64x requires: ASIMD, FRINTTS",
7089    "frint64z requires: ASIMD, FRINTTS",
7090    "frinta requires: ASIMD",
7091    "frinti requires: ASIMD",
7092    "frintm requires: ASIMD",
7093    "frintn requires: ASIMD",
7094    "frintp requires: ASIMD",
7095    "frintx requires: ASIMD",
7096    "frintz requires: ASIMD",
7097    "frsqrte requires: ASIMD",
7098    "frsqrts requires: ASIMD",
7099    "fsqrt requires: ASIMD",
7100    "fsub requires: ASIMD",
7101    "ins requires: ASIMD",
7102    "ld1 requires: ASIMD",
7103    "ld1r requires: ASIMD",
7104    "ld2 requires: ASIMD",
7105    "ld2r requires: ASIMD",
7106    "ld3 requires: ASIMD",
7107    "ld3r requires: ASIMD",
7108    "ld4 requires: ASIMD",
7109    "ld4r requires: ASIMD",
7110    "ldnp requires: ASIMD",
7111    "ldp requires: ASIMD",
7112    "ldr requires: ASIMD",
7113    "ldur requires: ASIMD",
7114    "mla requires: ASIMD",
7115    "mls requires: ASIMD",
7116    "mov requires: ASIMD",
7117    "movi requires: ASIMD",
7118    "mul requires: ASIMD",
7119    "mvn requires: ASIMD",
7120    "mvni requires: ASIMD",
7121    "neg requires: ASIMD",
7122    "not requires: ASIMD",
7123    "orn requires: ASIMD",
7124    "orr requires: ASIMD",
7125    "pmul requires: ASIMD",
7126    "pmull requires: ASIMD",
7127    "pmull2 requires: ASIMD",
7128    "raddhn requires: ASIMD",
7129    "raddhn2 requires: ASIMD",
7130    "rax1 requires: ASIMD, SHA3",
7131    "rbit requires: ASIMD",
7132    "rev16 requires: ASIMD",
7133    "rev32 requires: ASIMD",
7134    "rev64 requires: ASIMD",
7135    "rshrn requires: ASIMD",
7136    "rshrn2 requires: ASIMD",
7137    "rsubhn requires: ASIMD",
7138    "rsubhn2 requires: ASIMD",
7139    "saba requires: ASIMD",
7140    "sabal requires: ASIMD",
7141    "sabal2 requires: ASIMD",
7142    "sabd requires: ASIMD",
7143    "sabdl requires: ASIMD",
7144    "sabdl2 requires: ASIMD",
7145    "sadalp requires: ASIMD",
7146    "saddl requires: ASIMD",
7147    "saddl2 requires: ASIMD",
7148    "saddlp requires: ASIMD",
7149    "saddlv requires: ASIMD",
7150    "saddw requires: ASIMD",
7151    "saddw2 requires: ASIMD",
7152    "scvtf requires: ASIMD",
7153    "sdot requires: ASIMD, DOTPROD",
7154    "sha1c requires: ASIMD, SHA1",
7155    "sha1h requires: ASIMD, SHA1",
7156    "sha1m requires: ASIMD, SHA1",
7157    "sha1p requires: ASIMD, SHA1",
7158    "sha1su0 requires: ASIMD, SHA1",
7159    "sha1su1 requires: ASIMD, SHA1",
7160    "sha256h requires: ASIMD, SHA256",
7161    "sha256h2 requires: ASIMD, SHA256",
7162    "sha256su0 requires: ASIMD, SHA256",
7163    "sha256su1 requires: ASIMD, SHA256",
7164    "sha512h requires: ASIMD, SHA512",
7165    "sha512h2 requires: ASIMD, SHA512",
7166    "sha512su0 requires: ASIMD, SHA512",
7167    "sha512su1 requires: ASIMD, SHA512",
7168    "shadd requires: ASIMD",
7169    "shl requires: ASIMD",
7170    "shll requires: ASIMD",
7171    "shll2 requires: ASIMD",
7172    "shrn requires: ASIMD",
7173    "shrn2 requires: ASIMD",
7174    "shsub requires: ASIMD",
7175    "sli requires: ASIMD",
7176    "sm3partw1 requires: ASIMD, SM3",
7177    "sm3partw2 requires: ASIMD, SM3",
7178    "sm3ss1 requires: ASIMD, SM3",
7179    "sm3tt1a requires: ASIMD, SM3",
7180    "sm3tt1b requires: ASIMD, SM3",
7181    "sm3tt2a requires: ASIMD, SM3",
7182    "sm3tt2b requires: ASIMD, SM3",
7183    "sm4e requires: ASIMD, SM4",
7184    "sm4ekey requires: ASIMD, SM4",
7185    "smax requires: ASIMD",
7186    "smaxp requires: ASIMD",
7187    "smaxv requires: ASIMD",
7188    "smin requires: ASIMD",
7189    "sminp requires: ASIMD",
7190    "sminv requires: ASIMD",
7191    "smlal requires: ASIMD",
7192    "smlal2 requires: ASIMD",
7193    "smlsl requires: ASIMD",
7194    "smlsl2 requires: ASIMD",
7195    "smmla requires: ASIMD, I8MM",
7196    "smov requires: ASIMD",
7197    "smull requires: ASIMD",
7198    "smull2 requires: ASIMD",
7199    "sqabs requires: ASIMD",
7200    "sqadd requires: ASIMD",
7201    "sqdmlal requires: ASIMD",
7202    "sqdmlal2 requires: ASIMD",
7203    "sqdmlsl requires: ASIMD",
7204    "sqdmlsl2 requires: ASIMD",
7205    "sqdmulh requires: ASIMD",
7206    "sqdmull requires: ASIMD",
7207    "sqdmull2 requires: ASIMD",
7208    "sqneg requires: ASIMD",
7209    "sqrdmlah requires: ASIMD, RDM",
7210    "sqrdmlsh requires: ASIMD, RDM",
7211    "sqrdmulh requires: ASIMD",
7212    "sqrshl requires: ASIMD",
7213    "sqrshrn requires: ASIMD",
7214    "sqrshrn2 requires: ASIMD",
7215    "sqrshrun requires: ASIMD",
7216    "sqrshrun2 requires: ASIMD",
7217    "sqshl requires: ASIMD",
7218    "sqshlu requires: ASIMD",
7219    "sqshrn requires: ASIMD",
7220    "sqshrn2 requires: ASIMD",
7221    "sqshrun requires: ASIMD",
7222    "sqshrun2 requires: ASIMD",
7223    "sqsub requires: ASIMD",
7224    "sqxtn requires: ASIMD",
7225    "sqxtn2 requires: ASIMD",
7226    "sqxtun requires: ASIMD",
7227    "sqxtun2 requires: ASIMD",
7228    "srhadd requires: ASIMD",
7229    "sri requires: ASIMD",
7230    "srshl requires: ASIMD",
7231    "srshr requires: ASIMD",
7232    "srsra requires: ASIMD",
7233    "sshl requires: ASIMD",
7234    "sshll requires: ASIMD",
7235    "sshll2 requires: ASIMD",
7236    "sshr requires: ASIMD",
7237    "ssra requires: ASIMD",
7238    "ssubl requires: ASIMD",
7239    "ssubl2 requires: ASIMD",
7240    "ssubw requires: ASIMD",
7241    "ssubw2 requires: ASIMD",
7242    "st1 requires: ASIMD",
7243    "st2 requires: ASIMD",
7244    "st3 requires: ASIMD",
7245    "st4 requires: ASIMD",
7246    "stnp requires: ASIMD",
7247    "stp requires: ASIMD",
7248    "str requires: ASIMD",
7249    "stur requires: ASIMD",
7250    "sub requires: ASIMD",
7251    "subhn requires: ASIMD",
7252    "subhn2 requires: ASIMD",
7253    "sudot requires: ASIMD, I8MM",
7254    "suqadd requires: ASIMD",
7255    "sxtl requires: ASIMD",
7256    "sxtl2 requires: ASIMD",
7257    "tbl requires: ASIMD",
7258    "tbx requires: ASIMD",
7259    "trn1 requires: ASIMD",
7260    "trn2 requires: ASIMD",
7261    "uaba requires: ASIMD",
7262    "uabal requires: ASIMD",
7263    "uabal2 requires: ASIMD",
7264    "uabd requires: ASIMD",
7265    "uabdl requires: ASIMD",
7266    "uabdl2 requires: ASIMD",
7267    "uadalp requires: ASIMD",
7268    "uaddl requires: ASIMD",
7269    "uaddl2 requires: ASIMD",
7270    "uaddlp requires: ASIMD",
7271    "uaddlv requires: ASIMD",
7272    "uaddw requires: ASIMD",
7273    "uaddw2 requires: ASIMD",
7274    "ucvtf requires: ASIMD",
7275    "udot requires: ASIMD, DOTPROD",
7276    "uhadd requires: ASIMD",
7277    "uhsub requires: ASIMD",
7278    "umax requires: ASIMD",
7279    "umaxp requires: ASIMD",
7280    "umaxv requires: ASIMD",
7281    "umin requires: ASIMD",
7282    "uminp requires: ASIMD",
7283    "uminv requires: ASIMD",
7284    "umlal requires: ASIMD",
7285    "umlal2 requires: ASIMD",
7286    "umlsl requires: ASIMD",
7287    "umlsl2 requires: ASIMD",
7288    "ummla requires: ASIMD, I8MM",
7289    "umov requires: ASIMD",
7290    "umull requires: ASIMD",
7291    "umull2 requires: ASIMD",
7292    "uqadd requires: ASIMD",
7293    "uqrshl requires: ASIMD",
7294    "uqrshrn requires: ASIMD",
7295    "uqrshrn2 requires: ASIMD",
7296    "uqshl requires: ASIMD",
7297    "uqshrn requires: ASIMD",
7298    "uqshrn2 requires: ASIMD",
7299    "uqsub requires: ASIMD",
7300    "uqxtn requires: ASIMD",
7301    "uqxtn2 requires: ASIMD",
7302    "urecpe requires: ASIMD",
7303    "urhadd requires: ASIMD",
7304    "urshl requires: ASIMD",
7305    "urshr requires: ASIMD",
7306    "ursqrte requires: ASIMD",
7307    "ursra requires: ASIMD",
7308    "usdot requires: ASIMD, I8MM",
7309    "ushl requires: ASIMD",
7310    "ushll requires: ASIMD",
7311    "ushll2 requires: ASIMD",
7312    "ushr requires: ASIMD",
7313    "usmmla requires: ASIMD, I8MM",
7314    "usqadd requires: ASIMD",
7315    "usra requires: ASIMD",
7316    "usubl requires: ASIMD",
7317    "usubl2 requires: ASIMD",
7318    "usubw requires: ASIMD",
7319    "usubw2 requires: ASIMD",
7320    "uxtl requires: ASIMD",
7321    "uxtl2 requires: ASIMD",
7322    "uzp1 requires: ASIMD",
7323    "uzp2 requires: ASIMD",
7324    "xar requires: ASIMD, SHA3",
7325    "xtn requires: ASIMD",
7326    "xtn2 requires: ASIMD",
7327    "zip1 requires: ASIMD",
7328    "zip2 requires: ASIMD",
7329];
7330
7331static INST_FEATURE_FORM_OFFSETS: [u16; InstId::_Count as usize + 1] = [
7332    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7333    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7334    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7335    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7336    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7337    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7338    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7339    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7340    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7341    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7342    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7343    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7344    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7345    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7346    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 6, 9, 12, 15, 18, 18, 19, 20, 26,
7347    32, 38, 38, 41, 44, 46, 48, 49, 49, 54, 59, 59, 59, 64, 69, 72, 73, 78, 83, 88, 93, 93, 93,
7348    103, 113, 116, 116, 117, 120, 123, 126, 128, 131, 133, 136, 139, 142, 144, 147, 149, 154, 154,
7349    154, 159, 159, 159, 167, 168, 174, 180, 183, 184, 185, 186, 189, 192, 193, 193, 193, 193, 193,
7350    196, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7351    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7352    226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226, 226,
7353    226, 226, 226, 226, 226, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7354    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7355    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7356    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7357    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7358    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236,
7359    236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 236, 246, 246, 246, 246, 246, 246,
7360    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7361    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7362    246, 246, 246, 246, 246, 246, 246, 246, 246, 246, 246,
7363];
7364
7365static INST_FEATURE_FORMS: [InstFeatureForm; 246] = [
7366    InstFeatureForm {
7367        opcode_mask: 0xffe0fc00,
7368        opcode_value: 0x7ec01400,
7369        operand_signatures: [
7370            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7371            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7372            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7373            0,
7374            0,
7375            0,
7376        ],
7377        required: 0x0000000000004002,
7378        context: "fabd Hd, Hn, Hm requires: ASIMD, FP16",
7379    },
7380    InstFeatureForm {
7381        opcode_mask: 0xffe0fc00,
7382        opcode_value: 0x2ec01400,
7383        operand_signatures: [
7384            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7385            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7386            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7387            0,
7388            0,
7389            0,
7390        ],
7391        required: 0x0000000000004002,
7392        context: "fabd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7393    },
7394    InstFeatureForm {
7395        opcode_mask: 0xffe0fc00,
7396        opcode_value: 0x6ec01400,
7397        operand_signatures: [
7398            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7399            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7400            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7401            0,
7402            0,
7403            0,
7404        ],
7405        required: 0x0000000000004002,
7406        context: "fabd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7407    },
7408    InstFeatureForm {
7409        opcode_mask: 0xfffffc00,
7410        opcode_value: 0x1ee0c000,
7411        operand_signatures: [
7412            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7413            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7414            0,
7415            0,
7416            0,
7417            0,
7418        ],
7419        required: 0x0000000000004002,
7420        context: "fabs Hd, Hn requires: ASIMD, FP16",
7421    },
7422    InstFeatureForm {
7423        opcode_mask: 0xfffffc00,
7424        opcode_value: 0x0ef8f800,
7425        operand_signatures: [
7426            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7427            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7428            0,
7429            0,
7430            0,
7431            0,
7432        ],
7433        required: 0x0000000000004002,
7434        context: "fabs Vd.4H, Vn.4H requires: ASIMD, FP16",
7435    },
7436    InstFeatureForm {
7437        opcode_mask: 0xfffffc00,
7438        opcode_value: 0x4ef8f800,
7439        operand_signatures: [
7440            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7441            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7442            0,
7443            0,
7444            0,
7445            0,
7446        ],
7447        required: 0x0000000000004002,
7448        context: "fabs Vd.8H, Vn.8H requires: ASIMD, FP16",
7449    },
7450    InstFeatureForm {
7451        opcode_mask: 0xffe0fc00,
7452        opcode_value: 0x7e402c00,
7453        operand_signatures: [
7454            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7455            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7456            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7457            0,
7458            0,
7459            0,
7460        ],
7461        required: 0x0000000000004002,
7462        context: "facge Hd, Hn, Hm requires: ASIMD, FP16",
7463    },
7464    InstFeatureForm {
7465        opcode_mask: 0xffe0fc00,
7466        opcode_value: 0x2e402c00,
7467        operand_signatures: [
7468            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7469            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7470            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7471            0,
7472            0,
7473            0,
7474        ],
7475        required: 0x0000000000004002,
7476        context: "facge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7477    },
7478    InstFeatureForm {
7479        opcode_mask: 0xffe0fc00,
7480        opcode_value: 0x6e402c00,
7481        operand_signatures: [
7482            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7483            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7484            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7485            0,
7486            0,
7487            0,
7488        ],
7489        required: 0x0000000000004002,
7490        context: "facge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7491    },
7492    InstFeatureForm {
7493        opcode_mask: 0xffe0fc00,
7494        opcode_value: 0x7ec02c00,
7495        operand_signatures: [
7496            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7497            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7498            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7499            0,
7500            0,
7501            0,
7502        ],
7503        required: 0x0000000000004002,
7504        context: "facgt Hd, Hn, Hm requires: ASIMD, FP16",
7505    },
7506    InstFeatureForm {
7507        opcode_mask: 0xffe0fc00,
7508        opcode_value: 0x2ec02c00,
7509        operand_signatures: [
7510            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7511            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7512            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7513            0,
7514            0,
7515            0,
7516        ],
7517        required: 0x0000000000004002,
7518        context: "facgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7519    },
7520    InstFeatureForm {
7521        opcode_mask: 0xffe0fc00,
7522        opcode_value: 0x6ec02c00,
7523        operand_signatures: [
7524            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7525            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7526            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7527            0,
7528            0,
7529            0,
7530        ],
7531        required: 0x0000000000004002,
7532        context: "facgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7533    },
7534    InstFeatureForm {
7535        opcode_mask: 0xffe0fc00,
7536        opcode_value: 0x1ee02800,
7537        operand_signatures: [
7538            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7539            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7540            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7541            0,
7542            0,
7543            0,
7544        ],
7545        required: 0x0000000000004002,
7546        context: "fadd Hd, Hn, Hm requires: ASIMD, FP16",
7547    },
7548    InstFeatureForm {
7549        opcode_mask: 0xffe0fc00,
7550        opcode_value: 0x0e401400,
7551        operand_signatures: [
7552            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7553            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7554            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7555            0,
7556            0,
7557            0,
7558        ],
7559        required: 0x0000000000004002,
7560        context: "fadd Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7561    },
7562    InstFeatureForm {
7563        opcode_mask: 0xffe0fc00,
7564        opcode_value: 0x4e401400,
7565        operand_signatures: [
7566            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7567            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7568            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7569            0,
7570            0,
7571            0,
7572        ],
7573        required: 0x0000000000004002,
7574        context: "fadd Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7575    },
7576    InstFeatureForm {
7577        opcode_mask: 0xfffffc00,
7578        opcode_value: 0x5e30d800,
7579        operand_signatures: [
7580            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7581            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
7582            0,
7583            0,
7584            0,
7585            0,
7586        ],
7587        required: 0x0000000000004002,
7588        context: "faddp Hd, Vn.2H requires: ASIMD, FP16",
7589    },
7590    InstFeatureForm {
7591        opcode_mask: 0xffe0fc00,
7592        opcode_value: 0x2e401400,
7593        operand_signatures: [
7594            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7595            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7596            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7597            0,
7598            0,
7599            0,
7600        ],
7601        required: 0x0000000000004002,
7602        context: "faddp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7603    },
7604    InstFeatureForm {
7605        opcode_mask: 0xffe0fc00,
7606        opcode_value: 0x6e401400,
7607        operand_signatures: [
7608            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7609            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7610            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7611            0,
7612            0,
7613            0,
7614        ],
7615        required: 0x0000000000004002,
7616        context: "faddp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7617    },
7618    InstFeatureForm {
7619        opcode_mask: 0xffe00c10,
7620        opcode_value: 0x1ee00400,
7621        operand_signatures: [
7622            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7623            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7624            OperandType::Imm as u32,
7625            OperandType::Imm as u32,
7626            0,
7627            0,
7628        ],
7629        required: 0x0000000000004002,
7630        context: "fccmp Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7631    },
7632    InstFeatureForm {
7633        opcode_mask: 0xffe00c10,
7634        opcode_value: 0x1ee00410,
7635        operand_signatures: [
7636            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7637            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7638            OperandType::Imm as u32,
7639            OperandType::Imm as u32,
7640            0,
7641            0,
7642        ],
7643        required: 0x0000000000004002,
7644        context: "fccmpe Hn, Hm, #nzcv, #cond requires: ASIMD, FP16",
7645    },
7646    InstFeatureForm {
7647        opcode_mask: 0xfffffc00,
7648        opcode_value: 0x5ef8d800,
7649        operand_signatures: [
7650            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7651            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7652            OperandType::Imm as u32,
7653            0,
7654            0,
7655            0,
7656        ],
7657        required: 0x0000000000004002,
7658        context: "fcmeq Hd, Hn, #0 requires: ASIMD, FP16",
7659    },
7660    InstFeatureForm {
7661        opcode_mask: 0xfffffc00,
7662        opcode_value: 0x0ef8d800,
7663        operand_signatures: [
7664            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7665            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7666            OperandType::Imm as u32,
7667            0,
7668            0,
7669            0,
7670        ],
7671        required: 0x0000000000004002,
7672        context: "fcmeq Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7673    },
7674    InstFeatureForm {
7675        opcode_mask: 0xfffffc00,
7676        opcode_value: 0x4ef8d800,
7677        operand_signatures: [
7678            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7679            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7680            OperandType::Imm as u32,
7681            0,
7682            0,
7683            0,
7684        ],
7685        required: 0x0000000000004002,
7686        context: "fcmeq Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7687    },
7688    InstFeatureForm {
7689        opcode_mask: 0xffe0fc00,
7690        opcode_value: 0x5e402400,
7691        operand_signatures: [
7692            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7693            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7694            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7695            0,
7696            0,
7697            0,
7698        ],
7699        required: 0x0000000000004002,
7700        context: "fcmeq Hd, Hn, Hm requires: ASIMD, FP16",
7701    },
7702    InstFeatureForm {
7703        opcode_mask: 0xffe0fc00,
7704        opcode_value: 0x0e402400,
7705        operand_signatures: [
7706            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7707            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7708            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7709            0,
7710            0,
7711            0,
7712        ],
7713        required: 0x0000000000004002,
7714        context: "fcmeq Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7715    },
7716    InstFeatureForm {
7717        opcode_mask: 0xffe0fc00,
7718        opcode_value: 0x4e402400,
7719        operand_signatures: [
7720            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7721            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7722            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7723            0,
7724            0,
7725            0,
7726        ],
7727        required: 0x0000000000004002,
7728        context: "fcmeq Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7729    },
7730    InstFeatureForm {
7731        opcode_mask: 0xfffffc00,
7732        opcode_value: 0x7ef8c800,
7733        operand_signatures: [
7734            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7735            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7736            OperandType::Imm as u32,
7737            0,
7738            0,
7739            0,
7740        ],
7741        required: 0x0000000000004002,
7742        context: "fcmge Hd, Hn, #0 requires: ASIMD, FP16",
7743    },
7744    InstFeatureForm {
7745        opcode_mask: 0xfffffc00,
7746        opcode_value: 0x2ef8c800,
7747        operand_signatures: [
7748            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7749            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7750            OperandType::Imm as u32,
7751            0,
7752            0,
7753            0,
7754        ],
7755        required: 0x0000000000004002,
7756        context: "fcmge Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7757    },
7758    InstFeatureForm {
7759        opcode_mask: 0xfffffc00,
7760        opcode_value: 0x6ef8c800,
7761        operand_signatures: [
7762            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7763            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7764            OperandType::Imm as u32,
7765            0,
7766            0,
7767            0,
7768        ],
7769        required: 0x0000000000004002,
7770        context: "fcmge Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7771    },
7772    InstFeatureForm {
7773        opcode_mask: 0xffe0fc00,
7774        opcode_value: 0x7e402400,
7775        operand_signatures: [
7776            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7777            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7778            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7779            0,
7780            0,
7781            0,
7782        ],
7783        required: 0x0000000000004002,
7784        context: "fcmge Hd, Hn, Hm requires: ASIMD, FP16",
7785    },
7786    InstFeatureForm {
7787        opcode_mask: 0xffe0fc00,
7788        opcode_value: 0x2e402400,
7789        operand_signatures: [
7790            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7791            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7792            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7793            0,
7794            0,
7795            0,
7796        ],
7797        required: 0x0000000000004002,
7798        context: "fcmge Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7799    },
7800    InstFeatureForm {
7801        opcode_mask: 0xffe0fc00,
7802        opcode_value: 0x6e402400,
7803        operand_signatures: [
7804            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7805            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7806            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7807            0,
7808            0,
7809            0,
7810        ],
7811        required: 0x0000000000004002,
7812        context: "fcmge Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7813    },
7814    InstFeatureForm {
7815        opcode_mask: 0xfffffc00,
7816        opcode_value: 0x5ef8c800,
7817        operand_signatures: [
7818            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7819            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7820            OperandType::Imm as u32,
7821            0,
7822            0,
7823            0,
7824        ],
7825        required: 0x0000000000004002,
7826        context: "fcmgt Hd, Hn, #0 requires: ASIMD, FP16",
7827    },
7828    InstFeatureForm {
7829        opcode_mask: 0xfffffc00,
7830        opcode_value: 0x0ef8c800,
7831        operand_signatures: [
7832            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7833            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7834            OperandType::Imm as u32,
7835            0,
7836            0,
7837            0,
7838        ],
7839        required: 0x0000000000004002,
7840        context: "fcmgt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7841    },
7842    InstFeatureForm {
7843        opcode_mask: 0xfffffc00,
7844        opcode_value: 0x4ef8c800,
7845        operand_signatures: [
7846            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7847            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7848            OperandType::Imm as u32,
7849            0,
7850            0,
7851            0,
7852        ],
7853        required: 0x0000000000004002,
7854        context: "fcmgt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7855    },
7856    InstFeatureForm {
7857        opcode_mask: 0xffe0fc00,
7858        opcode_value: 0x7ec02400,
7859        operand_signatures: [
7860            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7861            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7862            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7863            0,
7864            0,
7865            0,
7866        ],
7867        required: 0x0000000000004002,
7868        context: "fcmgt Hd, Hn, Hm requires: ASIMD, FP16",
7869    },
7870    InstFeatureForm {
7871        opcode_mask: 0xffe0fc00,
7872        opcode_value: 0x2ec02400,
7873        operand_signatures: [
7874            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7875            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7876            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7877            0,
7878            0,
7879            0,
7880        ],
7881        required: 0x0000000000004002,
7882        context: "fcmgt Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
7883    },
7884    InstFeatureForm {
7885        opcode_mask: 0xffe0fc00,
7886        opcode_value: 0x6ec02400,
7887        operand_signatures: [
7888            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7889            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7890            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7891            0,
7892            0,
7893            0,
7894        ],
7895        required: 0x0000000000004002,
7896        context: "fcmgt Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
7897    },
7898    InstFeatureForm {
7899        opcode_mask: 0xfffffc00,
7900        opcode_value: 0x7ef8d800,
7901        operand_signatures: [
7902            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7903            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7904            OperandType::Imm as u32,
7905            0,
7906            0,
7907            0,
7908        ],
7909        required: 0x0000000000004002,
7910        context: "fcmle Hd, Hn, #0 requires: ASIMD, FP16",
7911    },
7912    InstFeatureForm {
7913        opcode_mask: 0xfffffc00,
7914        opcode_value: 0x2ef8d800,
7915        operand_signatures: [
7916            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7917            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7918            OperandType::Imm as u32,
7919            0,
7920            0,
7921            0,
7922        ],
7923        required: 0x0000000000004002,
7924        context: "fcmle Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7925    },
7926    InstFeatureForm {
7927        opcode_mask: 0xfffffc00,
7928        opcode_value: 0x6ef8d800,
7929        operand_signatures: [
7930            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7931            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7932            OperandType::Imm as u32,
7933            0,
7934            0,
7935            0,
7936        ],
7937        required: 0x0000000000004002,
7938        context: "fcmle Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7939    },
7940    InstFeatureForm {
7941        opcode_mask: 0xfffffc00,
7942        opcode_value: 0x5ef8e800,
7943        operand_signatures: [
7944            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7945            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7946            OperandType::Imm as u32,
7947            0,
7948            0,
7949            0,
7950        ],
7951        required: 0x0000000000004002,
7952        context: "fcmlt Hd, Hn, #0 requires: ASIMD, FP16",
7953    },
7954    InstFeatureForm {
7955        opcode_mask: 0xfffffc00,
7956        opcode_value: 0x0ef8e800,
7957        operand_signatures: [
7958            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7959            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
7960            OperandType::Imm as u32,
7961            0,
7962            0,
7963            0,
7964        ],
7965        required: 0x0000000000004002,
7966        context: "fcmlt Vd.4H, Vn.4H, #0 requires: ASIMD, FP16",
7967    },
7968    InstFeatureForm {
7969        opcode_mask: 0xfffffc00,
7970        opcode_value: 0x4ef8e800,
7971        operand_signatures: [
7972            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7973            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
7974            OperandType::Imm as u32,
7975            0,
7976            0,
7977            0,
7978        ],
7979        required: 0x0000000000004002,
7980        context: "fcmlt Vd.8H, Vn.8H, #0 requires: ASIMD, FP16",
7981    },
7982    InstFeatureForm {
7983        opcode_mask: 0xfffffc1f,
7984        opcode_value: 0x1ee02008,
7985        operand_signatures: [
7986            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
7987            OperandType::Imm as u32,
7988            0,
7989            0,
7990            0,
7991            0,
7992        ],
7993        required: 0x0000000000004002,
7994        context: "fcmp Hn, #0 requires: ASIMD, FP16",
7995    },
7996    InstFeatureForm {
7997        opcode_mask: 0xffe0fc1f,
7998        opcode_value: 0x1ee02000,
7999        operand_signatures: [
8000            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8001            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8002            0,
8003            0,
8004            0,
8005            0,
8006        ],
8007        required: 0x0000000000004002,
8008        context: "fcmp Hn, Hm requires: ASIMD, FP16",
8009    },
8010    InstFeatureForm {
8011        opcode_mask: 0xfffffc1f,
8012        opcode_value: 0x1ee02018,
8013        operand_signatures: [
8014            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8015            OperandType::Imm as u32,
8016            0,
8017            0,
8018            0,
8019            0,
8020        ],
8021        required: 0x0000000000004002,
8022        context: "fcmpe Hn, #0 requires: ASIMD, FP16",
8023    },
8024    InstFeatureForm {
8025        opcode_mask: 0xffe0fc1f,
8026        opcode_value: 0x1ee02010,
8027        operand_signatures: [
8028            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8029            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8030            0,
8031            0,
8032            0,
8033            0,
8034        ],
8035        required: 0x0000000000004002,
8036        context: "fcmpe Hn, Hm requires: ASIMD, FP16",
8037    },
8038    InstFeatureForm {
8039        opcode_mask: 0xffe00c00,
8040        opcode_value: 0x1ee00c00,
8041        operand_signatures: [
8042            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8043            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8044            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8045            OperandType::Imm as u32,
8046            0,
8047            0,
8048        ],
8049        required: 0x0000000000004002,
8050        context: "fcsel Hd, Hn, Hm, #cond requires: ASIMD, FP16",
8051    },
8052    InstFeatureForm {
8053        opcode_mask: 0xfffffc00,
8054        opcode_value: 0x1ee40000,
8055        operand_signatures: [
8056            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8057            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8058            0,
8059            0,
8060            0,
8061            0,
8062        ],
8063        required: 0x0000000000004002,
8064        context: "fcvtas Wd, Hn requires: ASIMD, FP16",
8065    },
8066    InstFeatureForm {
8067        opcode_mask: 0xfffffc00,
8068        opcode_value: 0x9ee40000,
8069        operand_signatures: [
8070            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8071            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8072            0,
8073            0,
8074            0,
8075            0,
8076        ],
8077        required: 0x0000000000004002,
8078        context: "fcvtas Xd, Hn requires: ASIMD, FP16",
8079    },
8080    InstFeatureForm {
8081        opcode_mask: 0xfffffc00,
8082        opcode_value: 0x5e79c800,
8083        operand_signatures: [
8084            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8085            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8086            0,
8087            0,
8088            0,
8089            0,
8090        ],
8091        required: 0x0000000000004002,
8092        context: "fcvtas Hd, Hn requires: ASIMD, FP16",
8093    },
8094    InstFeatureForm {
8095        opcode_mask: 0xfffffc00,
8096        opcode_value: 0x0e79c800,
8097        operand_signatures: [
8098            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8099            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8100            0,
8101            0,
8102            0,
8103            0,
8104        ],
8105        required: 0x0000000000004002,
8106        context: "fcvtas Vd.4H, Vn.4H requires: ASIMD, FP16",
8107    },
8108    InstFeatureForm {
8109        opcode_mask: 0xfffffc00,
8110        opcode_value: 0x4e79c800,
8111        operand_signatures: [
8112            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8113            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8114            0,
8115            0,
8116            0,
8117            0,
8118        ],
8119        required: 0x0000000000004002,
8120        context: "fcvtas Vd.8H, Vn.8H requires: ASIMD, FP16",
8121    },
8122    InstFeatureForm {
8123        opcode_mask: 0xfffffc00,
8124        opcode_value: 0x1ee50000,
8125        operand_signatures: [
8126            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8127            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8128            0,
8129            0,
8130            0,
8131            0,
8132        ],
8133        required: 0x0000000000004002,
8134        context: "fcvtau Wd, Hn requires: ASIMD, FP16",
8135    },
8136    InstFeatureForm {
8137        opcode_mask: 0xfffffc00,
8138        opcode_value: 0x9ee50000,
8139        operand_signatures: [
8140            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8141            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8142            0,
8143            0,
8144            0,
8145            0,
8146        ],
8147        required: 0x0000000000004002,
8148        context: "fcvtau Xd, Hn requires: ASIMD, FP16",
8149    },
8150    InstFeatureForm {
8151        opcode_mask: 0xfffffc00,
8152        opcode_value: 0x7e79c800,
8153        operand_signatures: [
8154            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8155            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8156            0,
8157            0,
8158            0,
8159            0,
8160        ],
8161        required: 0x0000000000004002,
8162        context: "fcvtau Hd, Hn requires: ASIMD, FP16",
8163    },
8164    InstFeatureForm {
8165        opcode_mask: 0xfffffc00,
8166        opcode_value: 0x2e79c800,
8167        operand_signatures: [
8168            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8169            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8170            0,
8171            0,
8172            0,
8173            0,
8174        ],
8175        required: 0x0000000000004002,
8176        context: "fcvtau Vd.4H, Vn.4H requires: ASIMD, FP16",
8177    },
8178    InstFeatureForm {
8179        opcode_mask: 0xfffffc00,
8180        opcode_value: 0x6e79c800,
8181        operand_signatures: [
8182            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8183            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8184            0,
8185            0,
8186            0,
8187            0,
8188        ],
8189        required: 0x0000000000004002,
8190        context: "fcvtau Vd.8H, Vn.8H requires: ASIMD, FP16",
8191    },
8192    InstFeatureForm {
8193        opcode_mask: 0xfffffc00,
8194        opcode_value: 0x1ef00000,
8195        operand_signatures: [
8196            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8197            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8198            0,
8199            0,
8200            0,
8201            0,
8202        ],
8203        required: 0x0000000000004002,
8204        context: "fcvtms Wd, Hn requires: ASIMD, FP16",
8205    },
8206    InstFeatureForm {
8207        opcode_mask: 0xfffffc00,
8208        opcode_value: 0x9ef00000,
8209        operand_signatures: [
8210            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8211            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8212            0,
8213            0,
8214            0,
8215            0,
8216        ],
8217        required: 0x0000000000004002,
8218        context: "fcvtms Xd, Hn requires: ASIMD, FP16",
8219    },
8220    InstFeatureForm {
8221        opcode_mask: 0xfffffc00,
8222        opcode_value: 0x5e79b800,
8223        operand_signatures: [
8224            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8225            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8226            0,
8227            0,
8228            0,
8229            0,
8230        ],
8231        required: 0x0000000000004002,
8232        context: "fcvtms Hd, Hn requires: ASIMD, FP16",
8233    },
8234    InstFeatureForm {
8235        opcode_mask: 0xfffffc00,
8236        opcode_value: 0x0e79b800,
8237        operand_signatures: [
8238            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8239            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8240            0,
8241            0,
8242            0,
8243            0,
8244        ],
8245        required: 0x0000000000004002,
8246        context: "fcvtms Vd.4H, Vn.4H requires: ASIMD, FP16",
8247    },
8248    InstFeatureForm {
8249        opcode_mask: 0xfffffc00,
8250        opcode_value: 0x4e79b800,
8251        operand_signatures: [
8252            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8253            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8254            0,
8255            0,
8256            0,
8257            0,
8258        ],
8259        required: 0x0000000000004002,
8260        context: "fcvtms Vd.8H, Vn.8H requires: ASIMD, FP16",
8261    },
8262    InstFeatureForm {
8263        opcode_mask: 0xfffffc00,
8264        opcode_value: 0x1ef10000,
8265        operand_signatures: [
8266            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8267            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8268            0,
8269            0,
8270            0,
8271            0,
8272        ],
8273        required: 0x0000000000004002,
8274        context: "fcvtmu Wd, Hn requires: ASIMD, FP16",
8275    },
8276    InstFeatureForm {
8277        opcode_mask: 0xfffffc00,
8278        opcode_value: 0x9ef10000,
8279        operand_signatures: [
8280            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8281            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8282            0,
8283            0,
8284            0,
8285            0,
8286        ],
8287        required: 0x0000000000004002,
8288        context: "fcvtmu Xd, Hn requires: ASIMD, FP16",
8289    },
8290    InstFeatureForm {
8291        opcode_mask: 0xfffffc00,
8292        opcode_value: 0x7e79b800,
8293        operand_signatures: [
8294            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8295            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8296            0,
8297            0,
8298            0,
8299            0,
8300        ],
8301        required: 0x0000000000004002,
8302        context: "fcvtmu Hd, Hn requires: ASIMD, FP16",
8303    },
8304    InstFeatureForm {
8305        opcode_mask: 0xfffffc00,
8306        opcode_value: 0x2e79b800,
8307        operand_signatures: [
8308            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8309            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8310            0,
8311            0,
8312            0,
8313            0,
8314        ],
8315        required: 0x0000000000004002,
8316        context: "fcvtmu Vd.4H, Vn.4H requires: ASIMD, FP16",
8317    },
8318    InstFeatureForm {
8319        opcode_mask: 0xfffffc00,
8320        opcode_value: 0x6e79b800,
8321        operand_signatures: [
8322            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8323            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8324            0,
8325            0,
8326            0,
8327            0,
8328        ],
8329        required: 0x0000000000004002,
8330        context: "fcvtmu Vd.8H, Vn.8H requires: ASIMD, FP16",
8331    },
8332    InstFeatureForm {
8333        opcode_mask: 0xffe0fc00,
8334        opcode_value: 0x0e40f400,
8335        operand_signatures: [
8336            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8337            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8338            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8339            0,
8340            0,
8341            0,
8342        ],
8343        required: 0x0000000000008002,
8344        context: "fcvtn Vd.8B, Vn.4H, Vm.4H requires: ASIMD, FP8",
8345    },
8346    InstFeatureForm {
8347        opcode_mask: 0xffe0fc00,
8348        opcode_value: 0x4e40f400,
8349        operand_signatures: [
8350            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8351            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8352            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8353            0,
8354            0,
8355            0,
8356        ],
8357        required: 0x0000000000008002,
8358        context: "fcvtn Vd.16B, Vn.8H, Vm.8H requires: ASIMD, FP8",
8359    },
8360    InstFeatureForm {
8361        opcode_mask: 0xffe0fc00,
8362        opcode_value: 0x0e00f400,
8363        operand_signatures: [
8364            feature_reg_signature(RegType::Vec64, VecElementType::B, false),
8365            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8366            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8367            0,
8368            0,
8369            0,
8370        ],
8371        required: 0x0000000000008002,
8372        context: "fcvtn Vd.8B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8373    },
8374    InstFeatureForm {
8375        opcode_mask: 0xffe0fc00,
8376        opcode_value: 0x4e00f400,
8377        operand_signatures: [
8378            feature_reg_signature(RegType::Vec128, VecElementType::B, false),
8379            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8380            feature_reg_signature(RegType::Vec128, VecElementType::S, false),
8381            0,
8382            0,
8383            0,
8384        ],
8385        required: 0x0000000000008002,
8386        context: "fcvtn2 Vx.16B, Vn.4S, Vm.4S requires: ASIMD, FP8",
8387    },
8388    InstFeatureForm {
8389        opcode_mask: 0xfffffc00,
8390        opcode_value: 0x1ee00000,
8391        operand_signatures: [
8392            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8393            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8394            0,
8395            0,
8396            0,
8397            0,
8398        ],
8399        required: 0x0000000000004002,
8400        context: "fcvtns Wd, Hn requires: ASIMD, FP16",
8401    },
8402    InstFeatureForm {
8403        opcode_mask: 0xfffffc00,
8404        opcode_value: 0x9ee00000,
8405        operand_signatures: [
8406            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8407            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8408            0,
8409            0,
8410            0,
8411            0,
8412        ],
8413        required: 0x0000000000004002,
8414        context: "fcvtns Xd, Hn requires: ASIMD, FP16",
8415    },
8416    InstFeatureForm {
8417        opcode_mask: 0xfffffc00,
8418        opcode_value: 0x5e79a800,
8419        operand_signatures: [
8420            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8421            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8422            0,
8423            0,
8424            0,
8425            0,
8426        ],
8427        required: 0x0000000000004002,
8428        context: "fcvtns Hd, Hn requires: ASIMD, FP16",
8429    },
8430    InstFeatureForm {
8431        opcode_mask: 0xfffffc00,
8432        opcode_value: 0x0e79a800,
8433        operand_signatures: [
8434            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8435            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8436            0,
8437            0,
8438            0,
8439            0,
8440        ],
8441        required: 0x0000000000004002,
8442        context: "fcvtns Vd.4H, Vn.4H requires: ASIMD, FP16",
8443    },
8444    InstFeatureForm {
8445        opcode_mask: 0xfffffc00,
8446        opcode_value: 0x4e79a800,
8447        operand_signatures: [
8448            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8449            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8450            0,
8451            0,
8452            0,
8453            0,
8454        ],
8455        required: 0x0000000000004002,
8456        context: "fcvtns Vd.8H, Vn.8H requires: ASIMD, FP16",
8457    },
8458    InstFeatureForm {
8459        opcode_mask: 0xfffffc00,
8460        opcode_value: 0x1ee10000,
8461        operand_signatures: [
8462            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8463            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8464            0,
8465            0,
8466            0,
8467            0,
8468        ],
8469        required: 0x0000000000004002,
8470        context: "fcvtnu Wd, Hn requires: ASIMD, FP16",
8471    },
8472    InstFeatureForm {
8473        opcode_mask: 0xfffffc00,
8474        opcode_value: 0x9ee10000,
8475        operand_signatures: [
8476            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8477            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8478            0,
8479            0,
8480            0,
8481            0,
8482        ],
8483        required: 0x0000000000004002,
8484        context: "fcvtnu Xd, Hn requires: ASIMD, FP16",
8485    },
8486    InstFeatureForm {
8487        opcode_mask: 0xfffffc00,
8488        opcode_value: 0x7e79a800,
8489        operand_signatures: [
8490            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8491            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8492            0,
8493            0,
8494            0,
8495            0,
8496        ],
8497        required: 0x0000000000004002,
8498        context: "fcvtnu Hd, Hn requires: ASIMD, FP16",
8499    },
8500    InstFeatureForm {
8501        opcode_mask: 0xfffffc00,
8502        opcode_value: 0x2e79a800,
8503        operand_signatures: [
8504            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8505            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8506            0,
8507            0,
8508            0,
8509            0,
8510        ],
8511        required: 0x0000000000004002,
8512        context: "fcvtnu Vd.4H, Vn.4H requires: ASIMD, FP16",
8513    },
8514    InstFeatureForm {
8515        opcode_mask: 0xfffffc00,
8516        opcode_value: 0x6e79a800,
8517        operand_signatures: [
8518            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8519            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8520            0,
8521            0,
8522            0,
8523            0,
8524        ],
8525        required: 0x0000000000004002,
8526        context: "fcvtnu Vd.8H, Vn.8H requires: ASIMD, FP16",
8527    },
8528    InstFeatureForm {
8529        opcode_mask: 0xfffffc00,
8530        opcode_value: 0x1ee80000,
8531        operand_signatures: [
8532            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8533            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8534            0,
8535            0,
8536            0,
8537            0,
8538        ],
8539        required: 0x0000000000004002,
8540        context: "fcvtps Wd, Hn requires: ASIMD, FP16",
8541    },
8542    InstFeatureForm {
8543        opcode_mask: 0xfffffc00,
8544        opcode_value: 0x9ee80000,
8545        operand_signatures: [
8546            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8547            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8548            0,
8549            0,
8550            0,
8551            0,
8552        ],
8553        required: 0x0000000000004002,
8554        context: "fcvtps Xd, Hn requires: ASIMD, FP16",
8555    },
8556    InstFeatureForm {
8557        opcode_mask: 0xfffffc00,
8558        opcode_value: 0x5ef9a800,
8559        operand_signatures: [
8560            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8561            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8562            0,
8563            0,
8564            0,
8565            0,
8566        ],
8567        required: 0x0000000000004002,
8568        context: "fcvtps Hd, Hn requires: ASIMD, FP16",
8569    },
8570    InstFeatureForm {
8571        opcode_mask: 0xfffffc00,
8572        opcode_value: 0x0ef9a800,
8573        operand_signatures: [
8574            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8575            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8576            0,
8577            0,
8578            0,
8579            0,
8580        ],
8581        required: 0x0000000000004002,
8582        context: "fcvtps Vd.4H, Vn.4H requires: ASIMD, FP16",
8583    },
8584    InstFeatureForm {
8585        opcode_mask: 0xfffffc00,
8586        opcode_value: 0x4ef9a800,
8587        operand_signatures: [
8588            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8589            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8590            0,
8591            0,
8592            0,
8593            0,
8594        ],
8595        required: 0x0000000000004002,
8596        context: "fcvtps Vd.8H, Vn.8H requires: ASIMD, FP16",
8597    },
8598    InstFeatureForm {
8599        opcode_mask: 0xfffffc00,
8600        opcode_value: 0x1ee90000,
8601        operand_signatures: [
8602            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8603            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8604            0,
8605            0,
8606            0,
8607            0,
8608        ],
8609        required: 0x0000000000004002,
8610        context: "fcvtpu Wd, Hn requires: ASIMD, FP16",
8611    },
8612    InstFeatureForm {
8613        opcode_mask: 0xfffffc00,
8614        opcode_value: 0x9ee90000,
8615        operand_signatures: [
8616            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8617            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8618            0,
8619            0,
8620            0,
8621            0,
8622        ],
8623        required: 0x0000000000004002,
8624        context: "fcvtpu Xd, Hn requires: ASIMD, FP16",
8625    },
8626    InstFeatureForm {
8627        opcode_mask: 0xfffffc00,
8628        opcode_value: 0x7ef9a800,
8629        operand_signatures: [
8630            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8631            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8632            0,
8633            0,
8634            0,
8635            0,
8636        ],
8637        required: 0x0000000000004002,
8638        context: "fcvtpu Hd, Hn requires: ASIMD, FP16",
8639    },
8640    InstFeatureForm {
8641        opcode_mask: 0xfffffc00,
8642        opcode_value: 0x2ef9a800,
8643        operand_signatures: [
8644            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8645            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8646            0,
8647            0,
8648            0,
8649            0,
8650        ],
8651        required: 0x0000000000004002,
8652        context: "fcvtpu Vd.4H, Vn.4H requires: ASIMD, FP16",
8653    },
8654    InstFeatureForm {
8655        opcode_mask: 0xfffffc00,
8656        opcode_value: 0x6ef9a800,
8657        operand_signatures: [
8658            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8659            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8660            0,
8661            0,
8662            0,
8663            0,
8664        ],
8665        required: 0x0000000000004002,
8666        context: "fcvtpu Vd.8H, Vn.8H requires: ASIMD, FP16",
8667    },
8668    InstFeatureForm {
8669        opcode_mask: 0xfffffc00,
8670        opcode_value: 0x1ef80000,
8671        operand_signatures: [
8672            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8673            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8674            0,
8675            0,
8676            0,
8677            0,
8678        ],
8679        required: 0x0000000000004002,
8680        context: "fcvtzs Wd, Hn requires: ASIMD, FP16",
8681    },
8682    InstFeatureForm {
8683        opcode_mask: 0xfffffc00,
8684        opcode_value: 0x9ef80000,
8685        operand_signatures: [
8686            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8687            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8688            0,
8689            0,
8690            0,
8691            0,
8692        ],
8693        required: 0x0000000000004002,
8694        context: "fcvtzs Xd, Hn requires: ASIMD, FP16",
8695    },
8696    InstFeatureForm {
8697        opcode_mask: 0xfffffc00,
8698        opcode_value: 0x5ef9b800,
8699        operand_signatures: [
8700            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8701            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8702            0,
8703            0,
8704            0,
8705            0,
8706        ],
8707        required: 0x0000000000004002,
8708        context: "fcvtzs Hd, Hn requires: ASIMD, FP16",
8709    },
8710    InstFeatureForm {
8711        opcode_mask: 0xfffffc00,
8712        opcode_value: 0x0ef9b800,
8713        operand_signatures: [
8714            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8715            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8716            0,
8717            0,
8718            0,
8719            0,
8720        ],
8721        required: 0x0000000000004002,
8722        context: "fcvtzs Vd.4H, Vn.4H requires: ASIMD, FP16",
8723    },
8724    InstFeatureForm {
8725        opcode_mask: 0xfffffc00,
8726        opcode_value: 0x4ef9b800,
8727        operand_signatures: [
8728            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8729            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8730            0,
8731            0,
8732            0,
8733            0,
8734        ],
8735        required: 0x0000000000004002,
8736        context: "fcvtzs Vd.8H, Vn.8H requires: ASIMD, FP16",
8737    },
8738    InstFeatureForm {
8739        opcode_mask: 0xffff0000,
8740        opcode_value: 0x1ed80000,
8741        operand_signatures: [
8742            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8743            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8744            OperandType::Imm as u32,
8745            0,
8746            0,
8747            0,
8748        ],
8749        required: 0x0000000000004002,
8750        context: "fcvtzs Wd, Hn, #fbits requires: ASIMD, FP16",
8751    },
8752    InstFeatureForm {
8753        opcode_mask: 0xffff0000,
8754        opcode_value: 0x9ed80000,
8755        operand_signatures: [
8756            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8757            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8758            OperandType::Imm as u32,
8759            0,
8760            0,
8761            0,
8762        ],
8763        required: 0x0000000000004002,
8764        context: "fcvtzs Xd, Hn, #fbits requires: ASIMD, FP16",
8765    },
8766    InstFeatureForm {
8767        opcode_mask: 0xff80fc00,
8768        opcode_value: 0x5f00fc00,
8769        operand_signatures: [
8770            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8771            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8772            OperandType::Imm as u32,
8773            0,
8774            0,
8775            0,
8776        ],
8777        required: 0x0000000000004002,
8778        context: "fcvtzs Hd, Hn, #fbits requires: ASIMD, FP16",
8779    },
8780    InstFeatureForm {
8781        opcode_mask: 0xff80fc00,
8782        opcode_value: 0x0f00fc00,
8783        operand_signatures: [
8784            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8785            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8786            OperandType::Imm as u32,
8787            0,
8788            0,
8789            0,
8790        ],
8791        required: 0x0000000000004002,
8792        context: "fcvtzs Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8793    },
8794    InstFeatureForm {
8795        opcode_mask: 0xff80fc00,
8796        opcode_value: 0x4f00fc00,
8797        operand_signatures: [
8798            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8799            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8800            OperandType::Imm as u32,
8801            0,
8802            0,
8803            0,
8804        ],
8805        required: 0x0000000000004002,
8806        context: "fcvtzs Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8807    },
8808    InstFeatureForm {
8809        opcode_mask: 0xfffffc00,
8810        opcode_value: 0x1ef90000,
8811        operand_signatures: [
8812            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8813            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8814            0,
8815            0,
8816            0,
8817            0,
8818        ],
8819        required: 0x0000000000004002,
8820        context: "fcvtzu Wd, Hn requires: ASIMD, FP16",
8821    },
8822    InstFeatureForm {
8823        opcode_mask: 0xfffffc00,
8824        opcode_value: 0x9ef90000,
8825        operand_signatures: [
8826            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8827            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8828            0,
8829            0,
8830            0,
8831            0,
8832        ],
8833        required: 0x0000000000004002,
8834        context: "fcvtzu Xd, Hn requires: ASIMD, FP16",
8835    },
8836    InstFeatureForm {
8837        opcode_mask: 0xfffffc00,
8838        opcode_value: 0x7ef9b800,
8839        operand_signatures: [
8840            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8841            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8842            0,
8843            0,
8844            0,
8845            0,
8846        ],
8847        required: 0x0000000000004002,
8848        context: "fcvtzu Hd, Hn requires: ASIMD, FP16",
8849    },
8850    InstFeatureForm {
8851        opcode_mask: 0xfffffc00,
8852        opcode_value: 0x2ef9b800,
8853        operand_signatures: [
8854            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8855            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8856            0,
8857            0,
8858            0,
8859            0,
8860        ],
8861        required: 0x0000000000004002,
8862        context: "fcvtzu Vd.4H, Vn.4H requires: ASIMD, FP16",
8863    },
8864    InstFeatureForm {
8865        opcode_mask: 0xfffffc00,
8866        opcode_value: 0x6ef9b800,
8867        operand_signatures: [
8868            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8869            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8870            0,
8871            0,
8872            0,
8873            0,
8874        ],
8875        required: 0x0000000000004002,
8876        context: "fcvtzu Vd.8H, Vn.8H requires: ASIMD, FP16",
8877    },
8878    InstFeatureForm {
8879        opcode_mask: 0xffff0000,
8880        opcode_value: 0x1ed90000,
8881        operand_signatures: [
8882            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
8883            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8884            OperandType::Imm as u32,
8885            0,
8886            0,
8887            0,
8888        ],
8889        required: 0x0000000000004002,
8890        context: "fcvtzu Wd, Hn, #fbits requires: ASIMD, FP16",
8891    },
8892    InstFeatureForm {
8893        opcode_mask: 0xffff0000,
8894        opcode_value: 0x9ed90000,
8895        operand_signatures: [
8896            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
8897            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8898            OperandType::Imm as u32,
8899            0,
8900            0,
8901            0,
8902        ],
8903        required: 0x0000000000004002,
8904        context: "fcvtzu Xd, Hn, #fbits requires: ASIMD, FP16",
8905    },
8906    InstFeatureForm {
8907        opcode_mask: 0xff80fc00,
8908        opcode_value: 0x7f00fc00,
8909        operand_signatures: [
8910            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8911            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8912            OperandType::Imm as u32,
8913            0,
8914            0,
8915            0,
8916        ],
8917        required: 0x0000000000004002,
8918        context: "fcvtzu Hd, Hn, #fbits requires: ASIMD, FP16",
8919    },
8920    InstFeatureForm {
8921        opcode_mask: 0xff80fc00,
8922        opcode_value: 0x2f00fc00,
8923        operand_signatures: [
8924            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8925            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8926            OperandType::Imm as u32,
8927            0,
8928            0,
8929            0,
8930        ],
8931        required: 0x0000000000004002,
8932        context: "fcvtzu Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
8933    },
8934    InstFeatureForm {
8935        opcode_mask: 0xff80fc00,
8936        opcode_value: 0x6f00fc00,
8937        operand_signatures: [
8938            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8939            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8940            OperandType::Imm as u32,
8941            0,
8942            0,
8943            0,
8944        ],
8945        required: 0x0000000000004002,
8946        context: "fcvtzu Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
8947    },
8948    InstFeatureForm {
8949        opcode_mask: 0xffe0fc00,
8950        opcode_value: 0x1ee01800,
8951        operand_signatures: [
8952            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8953            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8954            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8955            0,
8956            0,
8957            0,
8958        ],
8959        required: 0x0000000000004002,
8960        context: "fdiv Hd, Hn, Hm requires: ASIMD, FP16",
8961    },
8962    InstFeatureForm {
8963        opcode_mask: 0xffe0fc00,
8964        opcode_value: 0x2e403c00,
8965        operand_signatures: [
8966            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8967            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8968            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
8969            0,
8970            0,
8971            0,
8972        ],
8973        required: 0x0000000000004002,
8974        context: "fdiv Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
8975    },
8976    InstFeatureForm {
8977        opcode_mask: 0xffe0fc00,
8978        opcode_value: 0x6e403c00,
8979        operand_signatures: [
8980            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8981            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8982            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
8983            0,
8984            0,
8985            0,
8986        ],
8987        required: 0x0000000000004002,
8988        context: "fdiv Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
8989    },
8990    InstFeatureForm {
8991        opcode_mask: 0xffe08000,
8992        opcode_value: 0x1fc00000,
8993        operand_signatures: [
8994            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8995            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8996            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8997            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
8998            0,
8999            0,
9000        ],
9001        required: 0x0000000000004002,
9002        context: "fmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9003    },
9004    InstFeatureForm {
9005        opcode_mask: 0xffe0fc00,
9006        opcode_value: 0x1ee04800,
9007        operand_signatures: [
9008            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9009            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9010            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9011            0,
9012            0,
9013            0,
9014        ],
9015        required: 0x0000000000004002,
9016        context: "fmax Hd, Hn, Hm requires: ASIMD, FP16",
9017    },
9018    InstFeatureForm {
9019        opcode_mask: 0xffe0fc00,
9020        opcode_value: 0x0e403400,
9021        operand_signatures: [
9022            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9023            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9024            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9025            0,
9026            0,
9027            0,
9028        ],
9029        required: 0x0000000000004002,
9030        context: "fmax Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9031    },
9032    InstFeatureForm {
9033        opcode_mask: 0xffe0fc00,
9034        opcode_value: 0x4e403400,
9035        operand_signatures: [
9036            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9037            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9038            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9039            0,
9040            0,
9041            0,
9042        ],
9043        required: 0x0000000000004002,
9044        context: "fmax Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9045    },
9046    InstFeatureForm {
9047        opcode_mask: 0xffe0fc00,
9048        opcode_value: 0x1ee06800,
9049        operand_signatures: [
9050            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9051            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9052            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9053            0,
9054            0,
9055            0,
9056        ],
9057        required: 0x0000000000004002,
9058        context: "fmaxnm Hd, Hn, Hm requires: ASIMD, FP16",
9059    },
9060    InstFeatureForm {
9061        opcode_mask: 0xffe0fc00,
9062        opcode_value: 0x0e400400,
9063        operand_signatures: [
9064            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9065            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9066            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9067            0,
9068            0,
9069            0,
9070        ],
9071        required: 0x0000000000004002,
9072        context: "fmaxnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9073    },
9074    InstFeatureForm {
9075        opcode_mask: 0xffe0fc00,
9076        opcode_value: 0x4e400400,
9077        operand_signatures: [
9078            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9079            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9080            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9081            0,
9082            0,
9083            0,
9084        ],
9085        required: 0x0000000000004002,
9086        context: "fmaxnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9087    },
9088    InstFeatureForm {
9089        opcode_mask: 0xfffffc00,
9090        opcode_value: 0x5e30c800,
9091        operand_signatures: [
9092            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9093            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9094            0,
9095            0,
9096            0,
9097            0,
9098        ],
9099        required: 0x0000000000004002,
9100        context: "fmaxnmp Hd, Vn.2H requires: ASIMD, FP16",
9101    },
9102    InstFeatureForm {
9103        opcode_mask: 0xffe0fc00,
9104        opcode_value: 0x2e400400,
9105        operand_signatures: [
9106            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9107            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9108            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9109            0,
9110            0,
9111            0,
9112        ],
9113        required: 0x0000000000004002,
9114        context: "fmaxnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9115    },
9116    InstFeatureForm {
9117        opcode_mask: 0xffe0fc00,
9118        opcode_value: 0x6e400400,
9119        operand_signatures: [
9120            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9121            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9122            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9123            0,
9124            0,
9125            0,
9126        ],
9127        required: 0x0000000000004002,
9128        context: "fmaxnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9129    },
9130    InstFeatureForm {
9131        opcode_mask: 0xfffffc00,
9132        opcode_value: 0x0e30c800,
9133        operand_signatures: [
9134            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9135            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9136            0,
9137            0,
9138            0,
9139            0,
9140        ],
9141        required: 0x0000000000004002,
9142        context: "fmaxnmv Hd, Vn.4H requires: ASIMD, FP16",
9143    },
9144    InstFeatureForm {
9145        opcode_mask: 0xfffffc00,
9146        opcode_value: 0x4e30c800,
9147        operand_signatures: [
9148            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9149            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9150            0,
9151            0,
9152            0,
9153            0,
9154        ],
9155        required: 0x0000000000004002,
9156        context: "fmaxnmv Hd, Vn.8H requires: ASIMD, FP16",
9157    },
9158    InstFeatureForm {
9159        opcode_mask: 0xfffffc00,
9160        opcode_value: 0x5e30f800,
9161        operand_signatures: [
9162            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9163            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9164            0,
9165            0,
9166            0,
9167            0,
9168        ],
9169        required: 0x0000000000004002,
9170        context: "fmaxp Hd, Vn.2H requires: ASIMD, FP16",
9171    },
9172    InstFeatureForm {
9173        opcode_mask: 0xffe0fc00,
9174        opcode_value: 0x2e403400,
9175        operand_signatures: [
9176            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9177            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9178            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9179            0,
9180            0,
9181            0,
9182        ],
9183        required: 0x0000000000004002,
9184        context: "fmaxp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9185    },
9186    InstFeatureForm {
9187        opcode_mask: 0xffe0fc00,
9188        opcode_value: 0x6e403400,
9189        operand_signatures: [
9190            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9191            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9192            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9193            0,
9194            0,
9195            0,
9196        ],
9197        required: 0x0000000000004002,
9198        context: "fmaxp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9199    },
9200    InstFeatureForm {
9201        opcode_mask: 0xfffffc00,
9202        opcode_value: 0x0e30f800,
9203        operand_signatures: [
9204            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9205            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9206            0,
9207            0,
9208            0,
9209            0,
9210        ],
9211        required: 0x0000000000004002,
9212        context: "fmaxv Hd, Vn.4H requires: ASIMD, FP16",
9213    },
9214    InstFeatureForm {
9215        opcode_mask: 0xfffffc00,
9216        opcode_value: 0x4e30f800,
9217        operand_signatures: [
9218            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9219            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9220            0,
9221            0,
9222            0,
9223            0,
9224        ],
9225        required: 0x0000000000004002,
9226        context: "fmaxv Hd, Vn.8H requires: ASIMD, FP16",
9227    },
9228    InstFeatureForm {
9229        opcode_mask: 0xffe0fc00,
9230        opcode_value: 0x1ee05800,
9231        operand_signatures: [
9232            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9233            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9234            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9235            0,
9236            0,
9237            0,
9238        ],
9239        required: 0x0000000000004002,
9240        context: "fmin Hd, Hn, Hm requires: ASIMD, FP16",
9241    },
9242    InstFeatureForm {
9243        opcode_mask: 0xffe0fc00,
9244        opcode_value: 0x0ec03400,
9245        operand_signatures: [
9246            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9247            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9248            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9249            0,
9250            0,
9251            0,
9252        ],
9253        required: 0x0000000000004002,
9254        context: "fmin Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9255    },
9256    InstFeatureForm {
9257        opcode_mask: 0xffe0fc00,
9258        opcode_value: 0x4ec03400,
9259        operand_signatures: [
9260            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9261            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9262            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9263            0,
9264            0,
9265            0,
9266        ],
9267        required: 0x0000000000004002,
9268        context: "fmin Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9269    },
9270    InstFeatureForm {
9271        opcode_mask: 0xffe0fc00,
9272        opcode_value: 0x1ee07800,
9273        operand_signatures: [
9274            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9275            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9276            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9277            0,
9278            0,
9279            0,
9280        ],
9281        required: 0x0000000000004002,
9282        context: "fminnm Hd, Hn, Hm requires: ASIMD, FP16",
9283    },
9284    InstFeatureForm {
9285        opcode_mask: 0xffe0fc00,
9286        opcode_value: 0x0ec00400,
9287        operand_signatures: [
9288            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9289            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9290            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9291            0,
9292            0,
9293            0,
9294        ],
9295        required: 0x0000000000004002,
9296        context: "fminnm Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9297    },
9298    InstFeatureForm {
9299        opcode_mask: 0xffe0fc00,
9300        opcode_value: 0x4ec00400,
9301        operand_signatures: [
9302            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9303            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9304            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9305            0,
9306            0,
9307            0,
9308        ],
9309        required: 0x0000000000004002,
9310        context: "fminnm Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9311    },
9312    InstFeatureForm {
9313        opcode_mask: 0xfffffc00,
9314        opcode_value: 0x5eb0c800,
9315        operand_signatures: [
9316            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9317            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9318            0,
9319            0,
9320            0,
9321            0,
9322        ],
9323        required: 0x0000000000004002,
9324        context: "fminnmp Hd, Vn.2H requires: ASIMD, FP16",
9325    },
9326    InstFeatureForm {
9327        opcode_mask: 0xffe0fc00,
9328        opcode_value: 0x2ec00400,
9329        operand_signatures: [
9330            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9331            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9332            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9333            0,
9334            0,
9335            0,
9336        ],
9337        required: 0x0000000000004002,
9338        context: "fminnmp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9339    },
9340    InstFeatureForm {
9341        opcode_mask: 0xffe0fc00,
9342        opcode_value: 0x6ec00400,
9343        operand_signatures: [
9344            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9345            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9346            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9347            0,
9348            0,
9349            0,
9350        ],
9351        required: 0x0000000000004002,
9352        context: "fminnmp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9353    },
9354    InstFeatureForm {
9355        opcode_mask: 0xfffffc00,
9356        opcode_value: 0x0eb0c800,
9357        operand_signatures: [
9358            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9359            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9360            0,
9361            0,
9362            0,
9363            0,
9364        ],
9365        required: 0x0000000000004002,
9366        context: "fminnmv Hd, Vn.4H requires: ASIMD, FP16",
9367    },
9368    InstFeatureForm {
9369        opcode_mask: 0xfffffc00,
9370        opcode_value: 0x4eb0c800,
9371        operand_signatures: [
9372            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9373            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9374            0,
9375            0,
9376            0,
9377            0,
9378        ],
9379        required: 0x0000000000004002,
9380        context: "fminnmv Hd, Vn.8H requires: ASIMD, FP16",
9381    },
9382    InstFeatureForm {
9383        opcode_mask: 0xfffffc00,
9384        opcode_value: 0x5eb0f800,
9385        operand_signatures: [
9386            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9387            feature_reg_signature(RegType::Vec32, VecElementType::H, false),
9388            0,
9389            0,
9390            0,
9391            0,
9392        ],
9393        required: 0x0000000000004002,
9394        context: "fminp Hd, Vn.2H requires: ASIMD, FP16",
9395    },
9396    InstFeatureForm {
9397        opcode_mask: 0xffe0fc00,
9398        opcode_value: 0x2ec03400,
9399        operand_signatures: [
9400            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9401            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9402            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9403            0,
9404            0,
9405            0,
9406        ],
9407        required: 0x0000000000004002,
9408        context: "fminp Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9409    },
9410    InstFeatureForm {
9411        opcode_mask: 0xffe0fc00,
9412        opcode_value: 0x6ec03400,
9413        operand_signatures: [
9414            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9415            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9416            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9417            0,
9418            0,
9419            0,
9420        ],
9421        required: 0x0000000000004002,
9422        context: "fminp Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9423    },
9424    InstFeatureForm {
9425        opcode_mask: 0xfffffc00,
9426        opcode_value: 0x0eb0f800,
9427        operand_signatures: [
9428            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9429            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9430            0,
9431            0,
9432            0,
9433            0,
9434        ],
9435        required: 0x0000000000004002,
9436        context: "fminv Hd, Vn.4H requires: ASIMD, FP16",
9437    },
9438    InstFeatureForm {
9439        opcode_mask: 0xfffffc00,
9440        opcode_value: 0x4eb0f800,
9441        operand_signatures: [
9442            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9443            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9444            0,
9445            0,
9446            0,
9447            0,
9448        ],
9449        required: 0x0000000000004002,
9450        context: "fminv Hd, Vn.8H requires: ASIMD, FP16",
9451    },
9452    InstFeatureForm {
9453        opcode_mask: 0xffe0fc00,
9454        opcode_value: 0x0e400c00,
9455        operand_signatures: [
9456            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9457            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9458            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9459            0,
9460            0,
9461            0,
9462        ],
9463        required: 0x0000000000004002,
9464        context: "fmla Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9465    },
9466    InstFeatureForm {
9467        opcode_mask: 0xffe0fc00,
9468        opcode_value: 0x4e400c00,
9469        operand_signatures: [
9470            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9471            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9472            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9473            0,
9474            0,
9475            0,
9476        ],
9477        required: 0x0000000000004002,
9478        context: "fmla Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9479    },
9480    InstFeatureForm {
9481        opcode_mask: 0xffc0f400,
9482        opcode_value: 0x5f001000,
9483        operand_signatures: [
9484            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9485            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9486            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9487            0,
9488            0,
9489            0,
9490        ],
9491        required: 0x0000000000004002,
9492        context: "fmla Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9493    },
9494    InstFeatureForm {
9495        opcode_mask: 0xffc0f400,
9496        opcode_value: 0x0f001000,
9497        operand_signatures: [
9498            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9499            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9500            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9501            0,
9502            0,
9503            0,
9504        ],
9505        required: 0x0000000000004002,
9506        context: "fmla Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9507    },
9508    InstFeatureForm {
9509        opcode_mask: 0xffc0f400,
9510        opcode_value: 0x4f001000,
9511        operand_signatures: [
9512            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9513            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9514            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9515            0,
9516            0,
9517            0,
9518        ],
9519        required: 0x0000000000004002,
9520        context: "fmla Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9521    },
9522    InstFeatureForm {
9523        opcode_mask: 0xffe0fc00,
9524        opcode_value: 0x0ec00c00,
9525        operand_signatures: [
9526            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9527            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9528            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9529            0,
9530            0,
9531            0,
9532        ],
9533        required: 0x0000000000004002,
9534        context: "fmls Vx.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9535    },
9536    InstFeatureForm {
9537        opcode_mask: 0xffe0fc00,
9538        opcode_value: 0x4ec00c00,
9539        operand_signatures: [
9540            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9541            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9542            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9543            0,
9544            0,
9545            0,
9546        ],
9547        required: 0x0000000000004002,
9548        context: "fmls Vx.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9549    },
9550    InstFeatureForm {
9551        opcode_mask: 0xffc0f400,
9552        opcode_value: 0x5f005000,
9553        operand_signatures: [
9554            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9555            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9556            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9557            0,
9558            0,
9559            0,
9560        ],
9561        required: 0x0000000000004002,
9562        context: "fmls Hx, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9563    },
9564    InstFeatureForm {
9565        opcode_mask: 0xffc0f400,
9566        opcode_value: 0x0f005000,
9567        operand_signatures: [
9568            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9569            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9570            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9571            0,
9572            0,
9573            0,
9574        ],
9575        required: 0x0000000000004002,
9576        context: "fmls Vx.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9577    },
9578    InstFeatureForm {
9579        opcode_mask: 0xffc0f400,
9580        opcode_value: 0x4f005000,
9581        operand_signatures: [
9582            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9583            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9584            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9585            0,
9586            0,
9587            0,
9588        ],
9589        required: 0x0000000000004002,
9590        context: "fmls Vx.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9591    },
9592    InstFeatureForm {
9593        opcode_mask: 0xfffffc00,
9594        opcode_value: 0x1ee60000,
9595        operand_signatures: [
9596            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9597            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9598            0,
9599            0,
9600            0,
9601            0,
9602        ],
9603        required: 0x0000000000004002,
9604        context: "fmov Wd, Hn requires: ASIMD, FP16",
9605    },
9606    InstFeatureForm {
9607        opcode_mask: 0xfffffc00,
9608        opcode_value: 0x9ee60000,
9609        operand_signatures: [
9610            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9611            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9612            0,
9613            0,
9614            0,
9615            0,
9616        ],
9617        required: 0x0000000000004002,
9618        context: "fmov Xd, Hn requires: ASIMD, FP16",
9619    },
9620    InstFeatureForm {
9621        opcode_mask: 0xfffffc00,
9622        opcode_value: 0x1ee70000,
9623        operand_signatures: [
9624            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9625            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
9626            0,
9627            0,
9628            0,
9629            0,
9630        ],
9631        required: 0x0000000000004002,
9632        context: "fmov Hd, Wn requires: ASIMD, FP16",
9633    },
9634    InstFeatureForm {
9635        opcode_mask: 0xfffffc00,
9636        opcode_value: 0x9ee70000,
9637        operand_signatures: [
9638            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9639            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
9640            0,
9641            0,
9642            0,
9643            0,
9644        ],
9645        required: 0x0000000000004002,
9646        context: "fmov Hd, Xn requires: ASIMD, FP16",
9647    },
9648    InstFeatureForm {
9649        opcode_mask: 0xfffffc00,
9650        opcode_value: 0x1ee04000,
9651        operand_signatures: [
9652            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9653            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9654            0,
9655            0,
9656            0,
9657            0,
9658        ],
9659        required: 0x0000000000004002,
9660        context: "fmov Hd, Hn requires: ASIMD, FP16",
9661    },
9662    InstFeatureForm {
9663        opcode_mask: 0xffe01fe0,
9664        opcode_value: 0x1ee01000,
9665        operand_signatures: [
9666            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9667            OperandType::Imm as u32,
9668            0,
9669            0,
9670            0,
9671            0,
9672        ],
9673        required: 0x0000000000004002,
9674        context: "fmov Hd, #fimm requires: ASIMD, FP16",
9675    },
9676    InstFeatureForm {
9677        opcode_mask: 0xfff8fc00,
9678        opcode_value: 0x0f00fc00,
9679        operand_signatures: [
9680            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9681            OperandType::Imm as u32,
9682            0,
9683            0,
9684            0,
9685            0,
9686        ],
9687        required: 0x0000000000004002,
9688        context: "fmov Vd.4H, #fimm requires: ASIMD, FP16",
9689    },
9690    InstFeatureForm {
9691        opcode_mask: 0xfff8fc00,
9692        opcode_value: 0x4f00fc00,
9693        operand_signatures: [
9694            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9695            OperandType::Imm as u32,
9696            0,
9697            0,
9698            0,
9699            0,
9700        ],
9701        required: 0x0000000000004002,
9702        context: "fmov Vd.8H, #fimm requires: ASIMD, FP16",
9703    },
9704    InstFeatureForm {
9705        opcode_mask: 0xffe08000,
9706        opcode_value: 0x1fc08000,
9707        operand_signatures: [
9708            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9709            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9710            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9711            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9712            0,
9713            0,
9714        ],
9715        required: 0x0000000000004002,
9716        context: "fmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9717    },
9718    InstFeatureForm {
9719        opcode_mask: 0xffe0fc00,
9720        opcode_value: 0x1ee00800,
9721        operand_signatures: [
9722            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9723            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9724            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9725            0,
9726            0,
9727            0,
9728        ],
9729        required: 0x0000000000004002,
9730        context: "fmul Hd, Hn, Hm requires: ASIMD, FP16",
9731    },
9732    InstFeatureForm {
9733        opcode_mask: 0xffe0fc00,
9734        opcode_value: 0x2e401c00,
9735        operand_signatures: [
9736            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9737            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9738            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9739            0,
9740            0,
9741            0,
9742        ],
9743        required: 0x0000000000004002,
9744        context: "fmul Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9745    },
9746    InstFeatureForm {
9747        opcode_mask: 0xffe0fc00,
9748        opcode_value: 0x6e401c00,
9749        operand_signatures: [
9750            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9751            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9752            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9753            0,
9754            0,
9755            0,
9756        ],
9757        required: 0x0000000000004002,
9758        context: "fmul Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9759    },
9760    InstFeatureForm {
9761        opcode_mask: 0xffc0f400,
9762        opcode_value: 0x5f009000,
9763        operand_signatures: [
9764            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9765            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9766            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9767            0,
9768            0,
9769            0,
9770        ],
9771        required: 0x0000000000004002,
9772        context: "fmul Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9773    },
9774    InstFeatureForm {
9775        opcode_mask: 0xffc0f400,
9776        opcode_value: 0x0f009000,
9777        operand_signatures: [
9778            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9779            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9780            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9781            0,
9782            0,
9783            0,
9784        ],
9785        required: 0x0000000000004002,
9786        context: "fmul Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9787    },
9788    InstFeatureForm {
9789        opcode_mask: 0xffc0f400,
9790        opcode_value: 0x4f009000,
9791        operand_signatures: [
9792            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9793            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9794            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9795            0,
9796            0,
9797            0,
9798        ],
9799        required: 0x0000000000004002,
9800        context: "fmul Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9801    },
9802    InstFeatureForm {
9803        opcode_mask: 0xffe0fc00,
9804        opcode_value: 0x5e401c00,
9805        operand_signatures: [
9806            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9807            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9808            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9809            0,
9810            0,
9811            0,
9812        ],
9813        required: 0x0000000000004002,
9814        context: "fmulx Hd, Hn, Hm requires: ASIMD, FP16",
9815    },
9816    InstFeatureForm {
9817        opcode_mask: 0xffe0fc00,
9818        opcode_value: 0x0e401c00,
9819        operand_signatures: [
9820            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9821            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9822            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9823            0,
9824            0,
9825            0,
9826        ],
9827        required: 0x0000000000004002,
9828        context: "fmulx Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
9829    },
9830    InstFeatureForm {
9831        opcode_mask: 0xffe0fc00,
9832        opcode_value: 0x4e401c00,
9833        operand_signatures: [
9834            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9835            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9836            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9837            0,
9838            0,
9839            0,
9840        ],
9841        required: 0x0000000000004002,
9842        context: "fmulx Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
9843    },
9844    InstFeatureForm {
9845        opcode_mask: 0xffc0f400,
9846        opcode_value: 0x7f009000,
9847        operand_signatures: [
9848            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9849            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9850            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9851            0,
9852            0,
9853            0,
9854        ],
9855        required: 0x0000000000004002,
9856        context: "fmulx Hd, Hn, Vm.H[#idx] requires: ASIMD, FP16",
9857    },
9858    InstFeatureForm {
9859        opcode_mask: 0xffc0f400,
9860        opcode_value: 0x2f009000,
9861        operand_signatures: [
9862            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9863            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9864            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9865            0,
9866            0,
9867            0,
9868        ],
9869        required: 0x0000000000004002,
9870        context: "fmulx Vd.4H, Vn.4H, Vm.H[#idx] requires: ASIMD, FP16",
9871    },
9872    InstFeatureForm {
9873        opcode_mask: 0xffc0f400,
9874        opcode_value: 0x6f009000,
9875        operand_signatures: [
9876            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9877            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9878            feature_reg_signature(RegType::Vec128, VecElementType::H, true),
9879            0,
9880            0,
9881            0,
9882        ],
9883        required: 0x0000000000004002,
9884        context: "fmulx Vd.8H, Vn.8H, Vm.H[#idx] requires: ASIMD, FP16",
9885    },
9886    InstFeatureForm {
9887        opcode_mask: 0xfffffc00,
9888        opcode_value: 0x1ee14000,
9889        operand_signatures: [
9890            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9891            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9892            0,
9893            0,
9894            0,
9895            0,
9896        ],
9897        required: 0x0000000000004002,
9898        context: "fneg Hd, Hn requires: ASIMD, FP16",
9899    },
9900    InstFeatureForm {
9901        opcode_mask: 0xfffffc00,
9902        opcode_value: 0x2ef8f800,
9903        operand_signatures: [
9904            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9905            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9906            0,
9907            0,
9908            0,
9909            0,
9910        ],
9911        required: 0x0000000000004002,
9912        context: "fneg Vd.4H, Vn.4H requires: ASIMD, FP16",
9913    },
9914    InstFeatureForm {
9915        opcode_mask: 0xfffffc00,
9916        opcode_value: 0x6ef8f800,
9917        operand_signatures: [
9918            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9919            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
9920            0,
9921            0,
9922            0,
9923            0,
9924        ],
9925        required: 0x0000000000004002,
9926        context: "fneg Vd.8H, Vn.8H requires: ASIMD, FP16",
9927    },
9928    InstFeatureForm {
9929        opcode_mask: 0xffe08000,
9930        opcode_value: 0x1fe00000,
9931        operand_signatures: [
9932            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9933            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9934            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9935            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9936            0,
9937            0,
9938        ],
9939        required: 0x0000000000004002,
9940        context: "fnmadd Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9941    },
9942    InstFeatureForm {
9943        opcode_mask: 0xffe08000,
9944        opcode_value: 0x1fe08000,
9945        operand_signatures: [
9946            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9947            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9948            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9949            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9950            0,
9951            0,
9952        ],
9953        required: 0x0000000000004002,
9954        context: "fnmsub Hd, Hn, Hm, Ha requires: ASIMD, FP16",
9955    },
9956    InstFeatureForm {
9957        opcode_mask: 0xffe0fc00,
9958        opcode_value: 0x1ee08800,
9959        operand_signatures: [
9960            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9961            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9962            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9963            0,
9964            0,
9965            0,
9966        ],
9967        required: 0x0000000000004002,
9968        context: "fnmul Hd, Hn, Hm requires: ASIMD, FP16",
9969    },
9970    InstFeatureForm {
9971        opcode_mask: 0xfffffc00,
9972        opcode_value: 0x5ef9d800,
9973        operand_signatures: [
9974            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9975            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
9976            0,
9977            0,
9978            0,
9979            0,
9980        ],
9981        required: 0x0000000000004002,
9982        context: "frecpe Hd, Hn requires: ASIMD, FP16",
9983    },
9984    InstFeatureForm {
9985        opcode_mask: 0xfffffc00,
9986        opcode_value: 0x0ef9d800,
9987        operand_signatures: [
9988            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9989            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
9990            0,
9991            0,
9992            0,
9993            0,
9994        ],
9995        required: 0x0000000000004002,
9996        context: "frecpe Vd.4H, Vn.4H requires: ASIMD, FP16",
9997    },
9998    InstFeatureForm {
9999        opcode_mask: 0xfffffc00,
10000        opcode_value: 0x4ef9d800,
10001        operand_signatures: [
10002            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10003            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10004            0,
10005            0,
10006            0,
10007            0,
10008        ],
10009        required: 0x0000000000004002,
10010        context: "frecpe Vd.8H, Vn.8H requires: ASIMD, FP16",
10011    },
10012    InstFeatureForm {
10013        opcode_mask: 0xffe0fc00,
10014        opcode_value: 0x5e403c00,
10015        operand_signatures: [
10016            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10017            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10018            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10019            0,
10020            0,
10021            0,
10022        ],
10023        required: 0x0000000000004002,
10024        context: "frecps Hd, Hn, Hm requires: ASIMD, FP16",
10025    },
10026    InstFeatureForm {
10027        opcode_mask: 0xffe0fc00,
10028        opcode_value: 0x0e403c00,
10029        operand_signatures: [
10030            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10031            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10032            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10033            0,
10034            0,
10035            0,
10036        ],
10037        required: 0x0000000000004002,
10038        context: "frecps Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10039    },
10040    InstFeatureForm {
10041        opcode_mask: 0xffe0fc00,
10042        opcode_value: 0x4e403c00,
10043        operand_signatures: [
10044            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10045            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10046            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10047            0,
10048            0,
10049            0,
10050        ],
10051        required: 0x0000000000004002,
10052        context: "frecps Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10053    },
10054    InstFeatureForm {
10055        opcode_mask: 0xfffffc00,
10056        opcode_value: 0x5ef9f800,
10057        operand_signatures: [
10058            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10059            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10060            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10061            0,
10062            0,
10063            0,
10064        ],
10065        required: 0x0000000000004002,
10066        context: "frecpx Hd, Hn, Hm requires: ASIMD, FP16",
10067    },
10068    InstFeatureForm {
10069        opcode_mask: 0xfffffc00,
10070        opcode_value: 0x1ee64000,
10071        operand_signatures: [
10072            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10073            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10074            0,
10075            0,
10076            0,
10077            0,
10078        ],
10079        required: 0x0000000000004002,
10080        context: "frinta Hd, Hn requires: ASIMD, FP16",
10081    },
10082    InstFeatureForm {
10083        opcode_mask: 0xfffffc00,
10084        opcode_value: 0x2e798800,
10085        operand_signatures: [
10086            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10087            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10088            0,
10089            0,
10090            0,
10091            0,
10092        ],
10093        required: 0x0000000000004002,
10094        context: "frinta Vd.4H, Vn.4H requires: ASIMD, FP16",
10095    },
10096    InstFeatureForm {
10097        opcode_mask: 0xfffffc00,
10098        opcode_value: 0x6e798800,
10099        operand_signatures: [
10100            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10101            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10102            0,
10103            0,
10104            0,
10105            0,
10106        ],
10107        required: 0x0000000000004002,
10108        context: "frinta Vd.8H, Vn.8H requires: ASIMD, FP16",
10109    },
10110    InstFeatureForm {
10111        opcode_mask: 0xfffffc00,
10112        opcode_value: 0x1ee7c000,
10113        operand_signatures: [
10114            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10115            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10116            0,
10117            0,
10118            0,
10119            0,
10120        ],
10121        required: 0x0000000000004002,
10122        context: "frinti Hd, Hn requires: ASIMD, FP16",
10123    },
10124    InstFeatureForm {
10125        opcode_mask: 0xfffffc00,
10126        opcode_value: 0x2ef99800,
10127        operand_signatures: [
10128            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10129            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10130            0,
10131            0,
10132            0,
10133            0,
10134        ],
10135        required: 0x0000000000004002,
10136        context: "frinti Vd.4H, Vn.4H requires: ASIMD, FP16",
10137    },
10138    InstFeatureForm {
10139        opcode_mask: 0xfffffc00,
10140        opcode_value: 0x6ef99800,
10141        operand_signatures: [
10142            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10143            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10144            0,
10145            0,
10146            0,
10147            0,
10148        ],
10149        required: 0x0000000000004002,
10150        context: "frinti Vd.8H, Vn.8H requires: ASIMD, FP16",
10151    },
10152    InstFeatureForm {
10153        opcode_mask: 0xfffffc00,
10154        opcode_value: 0x1ee54000,
10155        operand_signatures: [
10156            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10157            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10158            0,
10159            0,
10160            0,
10161            0,
10162        ],
10163        required: 0x0000000000004002,
10164        context: "frintm Hd, Hn requires: ASIMD, FP16",
10165    },
10166    InstFeatureForm {
10167        opcode_mask: 0xfffffc00,
10168        opcode_value: 0x0e799800,
10169        operand_signatures: [
10170            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10171            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10172            0,
10173            0,
10174            0,
10175            0,
10176        ],
10177        required: 0x0000000000004002,
10178        context: "frintm Vd.4H, Vn.4H requires: ASIMD, FP16",
10179    },
10180    InstFeatureForm {
10181        opcode_mask: 0xfffffc00,
10182        opcode_value: 0x4e799800,
10183        operand_signatures: [
10184            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10185            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10186            0,
10187            0,
10188            0,
10189            0,
10190        ],
10191        required: 0x0000000000004002,
10192        context: "frintm Vd.8H, Vn.8H requires: ASIMD, FP16",
10193    },
10194    InstFeatureForm {
10195        opcode_mask: 0xfffffc00,
10196        opcode_value: 0x1ee44000,
10197        operand_signatures: [
10198            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10199            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10200            0,
10201            0,
10202            0,
10203            0,
10204        ],
10205        required: 0x0000000000004002,
10206        context: "frintn Hd, Hn requires: ASIMD, FP16",
10207    },
10208    InstFeatureForm {
10209        opcode_mask: 0xfffffc00,
10210        opcode_value: 0x0e798800,
10211        operand_signatures: [
10212            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10213            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10214            0,
10215            0,
10216            0,
10217            0,
10218        ],
10219        required: 0x0000000000004002,
10220        context: "frintn Vd.4H, Vn.4H requires: ASIMD, FP16",
10221    },
10222    InstFeatureForm {
10223        opcode_mask: 0xfffffc00,
10224        opcode_value: 0x4e798800,
10225        operand_signatures: [
10226            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10227            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10228            0,
10229            0,
10230            0,
10231            0,
10232        ],
10233        required: 0x0000000000004002,
10234        context: "frintn Vd.8H, Vn.8H requires: ASIMD, FP16",
10235    },
10236    InstFeatureForm {
10237        opcode_mask: 0xfffffc00,
10238        opcode_value: 0x1ee4c000,
10239        operand_signatures: [
10240            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10241            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10242            0,
10243            0,
10244            0,
10245            0,
10246        ],
10247        required: 0x0000000000004002,
10248        context: "frintp Hd, Hn requires: ASIMD, FP16",
10249    },
10250    InstFeatureForm {
10251        opcode_mask: 0xfffffc00,
10252        opcode_value: 0x0ef98800,
10253        operand_signatures: [
10254            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10255            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10256            0,
10257            0,
10258            0,
10259            0,
10260        ],
10261        required: 0x0000000000004002,
10262        context: "frintp Vd.4H, Vn.4H requires: ASIMD, FP16",
10263    },
10264    InstFeatureForm {
10265        opcode_mask: 0xfffffc00,
10266        opcode_value: 0x4ef98800,
10267        operand_signatures: [
10268            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10269            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10270            0,
10271            0,
10272            0,
10273            0,
10274        ],
10275        required: 0x0000000000004002,
10276        context: "frintp Vd.8H, Vn.8H requires: ASIMD, FP16",
10277    },
10278    InstFeatureForm {
10279        opcode_mask: 0xfffffc00,
10280        opcode_value: 0x1ee74000,
10281        operand_signatures: [
10282            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10283            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10284            0,
10285            0,
10286            0,
10287            0,
10288        ],
10289        required: 0x0000000000004002,
10290        context: "frintx Hd, Hn requires: ASIMD, FP16",
10291    },
10292    InstFeatureForm {
10293        opcode_mask: 0xfffffc00,
10294        opcode_value: 0x2e799800,
10295        operand_signatures: [
10296            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10297            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10298            0,
10299            0,
10300            0,
10301            0,
10302        ],
10303        required: 0x0000000000004002,
10304        context: "frintx Vd.4H, Vn.4H requires: ASIMD, FP16",
10305    },
10306    InstFeatureForm {
10307        opcode_mask: 0xfffffc00,
10308        opcode_value: 0x6e799800,
10309        operand_signatures: [
10310            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10311            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10312            0,
10313            0,
10314            0,
10315            0,
10316        ],
10317        required: 0x0000000000004002,
10318        context: "frintx Vd.8H, Vn.8H requires: ASIMD, FP16",
10319    },
10320    InstFeatureForm {
10321        opcode_mask: 0xfffffc00,
10322        opcode_value: 0x1ee5c000,
10323        operand_signatures: [
10324            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10325            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10326            0,
10327            0,
10328            0,
10329            0,
10330        ],
10331        required: 0x0000000000004002,
10332        context: "frintz Hd, Hn requires: ASIMD, FP16",
10333    },
10334    InstFeatureForm {
10335        opcode_mask: 0xfffffc00,
10336        opcode_value: 0x0ef99800,
10337        operand_signatures: [
10338            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10339            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10340            0,
10341            0,
10342            0,
10343            0,
10344        ],
10345        required: 0x0000000000004002,
10346        context: "frintz Vd.4H, Vn.4H requires: ASIMD, FP16",
10347    },
10348    InstFeatureForm {
10349        opcode_mask: 0xfffffc00,
10350        opcode_value: 0x4ef99800,
10351        operand_signatures: [
10352            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10353            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10354            0,
10355            0,
10356            0,
10357            0,
10358        ],
10359        required: 0x0000000000004002,
10360        context: "frintz Vd.8H, Vn.8H requires: ASIMD, FP16",
10361    },
10362    InstFeatureForm {
10363        opcode_mask: 0xfffffc00,
10364        opcode_value: 0x7ef9d800,
10365        operand_signatures: [
10366            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10367            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10368            0,
10369            0,
10370            0,
10371            0,
10372        ],
10373        required: 0x0000000000004002,
10374        context: "frsqrte Hd, Hn requires: ASIMD, FP16",
10375    },
10376    InstFeatureForm {
10377        opcode_mask: 0xfffffc00,
10378        opcode_value: 0x2ef9d800,
10379        operand_signatures: [
10380            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10381            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10382            0,
10383            0,
10384            0,
10385            0,
10386        ],
10387        required: 0x0000000000004002,
10388        context: "frsqrte Vd.4H, Vn.4H requires: ASIMD, FP16",
10389    },
10390    InstFeatureForm {
10391        opcode_mask: 0xfffffc00,
10392        opcode_value: 0x6ef9d800,
10393        operand_signatures: [
10394            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10395            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10396            0,
10397            0,
10398            0,
10399            0,
10400        ],
10401        required: 0x0000000000004002,
10402        context: "frsqrte Vd.8H, Vn.8H requires: ASIMD, FP16",
10403    },
10404    InstFeatureForm {
10405        opcode_mask: 0xffe0fc00,
10406        opcode_value: 0x5ec03c00,
10407        operand_signatures: [
10408            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10409            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10410            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10411            0,
10412            0,
10413            0,
10414        ],
10415        required: 0x0000000000004002,
10416        context: "frsqrts Hd, Hn, Hm requires: ASIMD, FP16",
10417    },
10418    InstFeatureForm {
10419        opcode_mask: 0xffe0fc00,
10420        opcode_value: 0x0ec03c00,
10421        operand_signatures: [
10422            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10423            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10424            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10425            0,
10426            0,
10427            0,
10428        ],
10429        required: 0x0000000000004002,
10430        context: "frsqrts Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10431    },
10432    InstFeatureForm {
10433        opcode_mask: 0xffe0fc00,
10434        opcode_value: 0x4ec03c00,
10435        operand_signatures: [
10436            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10437            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10438            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10439            0,
10440            0,
10441            0,
10442        ],
10443        required: 0x0000000000004002,
10444        context: "frsqrts Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10445    },
10446    InstFeatureForm {
10447        opcode_mask: 0xfffffc00,
10448        opcode_value: 0x1ee1c000,
10449        operand_signatures: [
10450            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10451            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10452            0,
10453            0,
10454            0,
10455            0,
10456        ],
10457        required: 0x0000000000004002,
10458        context: "fsqrt Hd, Hn requires: ASIMD, FP16",
10459    },
10460    InstFeatureForm {
10461        opcode_mask: 0xfffffc00,
10462        opcode_value: 0x2ef9f800,
10463        operand_signatures: [
10464            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10465            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10466            0,
10467            0,
10468            0,
10469            0,
10470        ],
10471        required: 0x0000000000004002,
10472        context: "fsqrt Vd.4H, Vn.4H requires: ASIMD, FP16",
10473    },
10474    InstFeatureForm {
10475        opcode_mask: 0xfffffc00,
10476        opcode_value: 0x6ef9f800,
10477        operand_signatures: [
10478            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10479            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10480            0,
10481            0,
10482            0,
10483            0,
10484        ],
10485        required: 0x0000000000004002,
10486        context: "fsqrt Vd.8H, Vn.8H requires: ASIMD, FP16",
10487    },
10488    InstFeatureForm {
10489        opcode_mask: 0xffe0fc00,
10490        opcode_value: 0x1ee03800,
10491        operand_signatures: [
10492            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10493            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10494            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10495            0,
10496            0,
10497            0,
10498        ],
10499        required: 0x0000000000004002,
10500        context: "fsub Hd, Hn, Hm requires: ASIMD, FP16",
10501    },
10502    InstFeatureForm {
10503        opcode_mask: 0xffe0fc00,
10504        opcode_value: 0x0ec01400,
10505        operand_signatures: [
10506            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10507            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10508            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10509            0,
10510            0,
10511            0,
10512        ],
10513        required: 0x0000000000004002,
10514        context: "fsub Vd.4H, Vn.4H, Vm.4H requires: ASIMD, FP16",
10515    },
10516    InstFeatureForm {
10517        opcode_mask: 0xffe0fc00,
10518        opcode_value: 0x4ec01400,
10519        operand_signatures: [
10520            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10521            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10522            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10523            0,
10524            0,
10525            0,
10526        ],
10527        required: 0x0000000000004002,
10528        context: "fsub Vd.8H, Vn.8H, Vm.8H requires: ASIMD, FP16",
10529    },
10530    InstFeatureForm {
10531        opcode_mask: 0xfffffc00,
10532        opcode_value: 0x1ee20000,
10533        operand_signatures: [
10534            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10535            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10536            0,
10537            0,
10538            0,
10539            0,
10540        ],
10541        required: 0x0000000000004002,
10542        context: "scvtf Hd, Wn requires: ASIMD, FP16",
10543    },
10544    InstFeatureForm {
10545        opcode_mask: 0xfffffc00,
10546        opcode_value: 0x9ee20000,
10547        operand_signatures: [
10548            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10549            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10550            0,
10551            0,
10552            0,
10553            0,
10554        ],
10555        required: 0x0000000000004002,
10556        context: "scvtf Hd, Xn requires: ASIMD, FP16",
10557    },
10558    InstFeatureForm {
10559        opcode_mask: 0xfffffc00,
10560        opcode_value: 0x5e79d800,
10561        operand_signatures: [
10562            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10563            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10564            0,
10565            0,
10566            0,
10567            0,
10568        ],
10569        required: 0x0000000000004002,
10570        context: "scvtf Hd, Hn requires: ASIMD, FP16",
10571    },
10572    InstFeatureForm {
10573        opcode_mask: 0xfffffc00,
10574        opcode_value: 0x0e79d800,
10575        operand_signatures: [
10576            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10577            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10578            0,
10579            0,
10580            0,
10581            0,
10582        ],
10583        required: 0x0000000000004002,
10584        context: "scvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10585    },
10586    InstFeatureForm {
10587        opcode_mask: 0xfffffc00,
10588        opcode_value: 0x4e79d800,
10589        operand_signatures: [
10590            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10591            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10592            0,
10593            0,
10594            0,
10595            0,
10596        ],
10597        required: 0x0000000000004002,
10598        context: "scvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10599    },
10600    InstFeatureForm {
10601        opcode_mask: 0xffff0000,
10602        opcode_value: 0x1ec20000,
10603        operand_signatures: [
10604            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10605            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10606            OperandType::Imm as u32,
10607            0,
10608            0,
10609            0,
10610        ],
10611        required: 0x0000000000004002,
10612        context: "scvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10613    },
10614    InstFeatureForm {
10615        opcode_mask: 0xffff0000,
10616        opcode_value: 0x9ec20000,
10617        operand_signatures: [
10618            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10619            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10620            OperandType::Imm as u32,
10621            0,
10622            0,
10623            0,
10624        ],
10625        required: 0x0000000000004002,
10626        context: "scvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10627    },
10628    InstFeatureForm {
10629        opcode_mask: 0xff80fc00,
10630        opcode_value: 0x5f00e400,
10631        operand_signatures: [
10632            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10633            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10634            OperandType::Imm as u32,
10635            0,
10636            0,
10637            0,
10638        ],
10639        required: 0x0000000000004002,
10640        context: "scvtf Hd, Hn, #bits requires: ASIMD, FP16",
10641    },
10642    InstFeatureForm {
10643        opcode_mask: 0xff80fc00,
10644        opcode_value: 0x0f00e400,
10645        operand_signatures: [
10646            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10647            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10648            OperandType::Imm as u32,
10649            0,
10650            0,
10651            0,
10652        ],
10653        required: 0x0000000000004002,
10654        context: "scvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10655    },
10656    InstFeatureForm {
10657        opcode_mask: 0xff80fc00,
10658        opcode_value: 0x4f00e400,
10659        operand_signatures: [
10660            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10661            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10662            OperandType::Imm as u32,
10663            0,
10664            0,
10665            0,
10666        ],
10667        required: 0x0000000000004002,
10668        context: "scvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10669    },
10670    InstFeatureForm {
10671        opcode_mask: 0xfffffc00,
10672        opcode_value: 0x1ee30000,
10673        operand_signatures: [
10674            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10675            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10676            0,
10677            0,
10678            0,
10679            0,
10680        ],
10681        required: 0x0000000000004002,
10682        context: "ucvtf Hd, Wn requires: ASIMD, FP16",
10683    },
10684    InstFeatureForm {
10685        opcode_mask: 0xfffffc00,
10686        opcode_value: 0x9ee30000,
10687        operand_signatures: [
10688            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10689            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10690            0,
10691            0,
10692            0,
10693            0,
10694        ],
10695        required: 0x0000000000004002,
10696        context: "ucvtf Hd, Xn requires: ASIMD, FP16",
10697    },
10698    InstFeatureForm {
10699        opcode_mask: 0xfffffc00,
10700        opcode_value: 0x7e79d800,
10701        operand_signatures: [
10702            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10703            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10704            0,
10705            0,
10706            0,
10707            0,
10708        ],
10709        required: 0x0000000000004002,
10710        context: "ucvtf Hd, Hn requires: ASIMD, FP16",
10711    },
10712    InstFeatureForm {
10713        opcode_mask: 0xfffffc00,
10714        opcode_value: 0x2e79d800,
10715        operand_signatures: [
10716            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10717            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10718            0,
10719            0,
10720            0,
10721            0,
10722        ],
10723        required: 0x0000000000004002,
10724        context: "ucvtf Vd.4H, Vn.4H requires: ASIMD, FP16",
10725    },
10726    InstFeatureForm {
10727        opcode_mask: 0xfffffc00,
10728        opcode_value: 0x6e79d800,
10729        operand_signatures: [
10730            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10731            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10732            0,
10733            0,
10734            0,
10735            0,
10736        ],
10737        required: 0x0000000000004002,
10738        context: "ucvtf Vd.8H, Vn.8H requires: ASIMD, FP16",
10739    },
10740    InstFeatureForm {
10741        opcode_mask: 0xffff0000,
10742        opcode_value: 0x1ec30000,
10743        operand_signatures: [
10744            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10745            feature_reg_signature(RegType::Gp32, VecElementType::None, false),
10746            OperandType::Imm as u32,
10747            0,
10748            0,
10749            0,
10750        ],
10751        required: 0x0000000000004002,
10752        context: "ucvtf Hd, Wn, #fbits requires: ASIMD, FP16",
10753    },
10754    InstFeatureForm {
10755        opcode_mask: 0xffff0000,
10756        opcode_value: 0x9ec30000,
10757        operand_signatures: [
10758            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10759            feature_reg_signature(RegType::Gp64, VecElementType::None, false),
10760            OperandType::Imm as u32,
10761            0,
10762            0,
10763            0,
10764        ],
10765        required: 0x0000000000004002,
10766        context: "ucvtf Hd, Xn, #fbits requires: ASIMD, FP16",
10767    },
10768    InstFeatureForm {
10769        opcode_mask: 0xff80fc00,
10770        opcode_value: 0x7f00e400,
10771        operand_signatures: [
10772            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10773            feature_reg_signature(RegType::Vec16, VecElementType::None, false),
10774            OperandType::Imm as u32,
10775            0,
10776            0,
10777            0,
10778        ],
10779        required: 0x0000000000004002,
10780        context: "ucvtf Hd, Hn, #bits requires: ASIMD, FP16",
10781    },
10782    InstFeatureForm {
10783        opcode_mask: 0xff80fc00,
10784        opcode_value: 0x2f00e400,
10785        operand_signatures: [
10786            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10787            feature_reg_signature(RegType::Vec64, VecElementType::H, false),
10788            OperandType::Imm as u32,
10789            0,
10790            0,
10791            0,
10792        ],
10793        required: 0x0000000000004002,
10794        context: "ucvtf Vd.4H, Vn.4H, #fbits requires: ASIMD, FP16",
10795    },
10796    InstFeatureForm {
10797        opcode_mask: 0xff80fc00,
10798        opcode_value: 0x6f00e400,
10799        operand_signatures: [
10800            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10801            feature_reg_signature(RegType::Vec128, VecElementType::H, false),
10802            OperandType::Imm as u32,
10803            0,
10804            0,
10805            0,
10806        ],
10807        required: 0x0000000000004002,
10808        context: "ucvtf Vd.8H, Vn.8H, #fbits requires: ASIMD, FP16",
10809    },
10810];
10811
10812fn required_features_for_form(
10813    inst_id: usize,
10814    opcode: u32,
10815    ops: &[&Operand],
10816) -> (u64, &'static str) {
10817    let start = INST_FEATURE_FORM_OFFSETS[inst_id] as usize;
10818    let end = INST_FEATURE_FORM_OFFSETS[inst_id + 1] as usize;
10819    for form in &INST_FEATURE_FORMS[start..end] {
10820        if form.matches(opcode, ops) {
10821            return (form.required, form.context);
10822        }
10823    }
10824    (
10825        INST_BASE_FEATURE_MASKS[inst_id],
10826        INST_BASE_FEATURE_CONTEXT[inst_id],
10827    )
10828}
10829
10830/// One instruction carrying each represented feature.
10831pub static CPU_FEATURE_REPRESENTATIVE: [InstId; CPU_FEATURE_COUNT] = [
10832    InstId::Aesd_v,
10833    InstId::Abs_v,
10834    InstId::Bfcvt_v,
10835    InstId::Bti,
10836    InstId::Chkfeat,
10837    InstId::Clrbhb,
10838    InstId::Crc32b,
10839    InstId::Abs,
10840    InstId::Dgh,
10841    InstId::Sdot_v,
10842    InstId::Fcadd_v,
10843    InstId::Fmlal_v,
10844    InstId::Cfinv,
10845    InstId::Axflag,
10846    InstId::Fabd_v,
10847    InstId::Fcvtn_v,
10848    InstId::Frint32x_v,
10849    InstId::Smmla_v,
10850    InstId::Fjcvtzs_v,
10851    InstId::Ldlar,
10852    InstId::Cas,
10853    InstId::Addg,
10854    InstId::Ldgm,
10855    InstId::Autda,
10856    InstId::Esb,
10857    InstId::Sqrdmlah_v,
10858    InstId::Sha1c_v,
10859    InstId::Sha256h_v,
10860    InstId::Bcax_v,
10861    InstId::Sha512h_v,
10862    InstId::Sm3partw1_v,
10863    InstId::Sm4e_v,
10864];
10865// @generated AArch64 target features end